From dd433c1296bbd82e5e42bf8de1731a4eaadcfdb5 Mon Sep 17 00:00:00 2001
From: riperiperi <rhy3756547@hotmail.com>
Date: Fri, 13 Mar 2020 23:29:58 +0000
Subject: Implement AESMC, AESIMC, AESE, AESD and VEOR AArch32 instructions
 (#982)

* Add VEOR and AES instructions.

* Add tests for crypto instructions.

* Update ValueSource name.
---
 ARMeilleure/Instructions/InstEmitSimdCrypto32.cs  | 49 +++++++++++++++++++++++
 ARMeilleure/Instructions/InstEmitSimdLogical32.cs | 12 ++++++
 ARMeilleure/Instructions/InstName.cs              |  1 +
 3 files changed, 62 insertions(+)
 create mode 100644 ARMeilleure/Instructions/InstEmitSimdCrypto32.cs

(limited to 'ARMeilleure/Instructions')

diff --git a/ARMeilleure/Instructions/InstEmitSimdCrypto32.cs b/ARMeilleure/Instructions/InstEmitSimdCrypto32.cs
new file mode 100644
index 00000000..1cfce3ad
--- /dev/null
+++ b/ARMeilleure/Instructions/InstEmitSimdCrypto32.cs
@@ -0,0 +1,49 @@
+using ARMeilleure.Decoders;
+using ARMeilleure.IntermediateRepresentation;
+using ARMeilleure.Translation;
+
+using static ARMeilleure.Instructions.InstEmitHelper;
+
+namespace ARMeilleure.Instructions
+{
+    partial class InstEmit32
+    {
+        public static void Aesd_V(ArmEmitterContext context)
+        {
+            OpCode32Simd op = (OpCode32Simd)context.CurrOp;
+
+            Operand d = GetVecA32(op.Qd);
+            Operand n = GetVecA32(op.Qm);
+
+            context.Copy(d, context.Call(new _V128_V128_V128(SoftFallback.Decrypt), d, n));
+        }
+
+        public static void Aese_V(ArmEmitterContext context)
+        {
+            OpCode32Simd op = (OpCode32Simd)context.CurrOp;
+
+            Operand d = GetVecA32(op.Qd);
+            Operand n = GetVecA32(op.Qm);
+
+            context.Copy(d, context.Call(new _V128_V128_V128(SoftFallback.Encrypt), d, n));
+        }
+
+        public static void Aesimc_V(ArmEmitterContext context)
+        {
+            OpCode32Simd op = (OpCode32Simd)context.CurrOp;
+
+            Operand n = GetVecA32(op.Qm);
+
+            context.Copy(GetVec(op.Qd), context.Call(new _V128_V128(SoftFallback.InverseMixColumns), n));
+        }
+
+        public static void Aesmc_V(ArmEmitterContext context)
+        {
+            OpCode32Simd op = (OpCode32Simd)context.CurrOp;
+
+            Operand n = GetVecA32(op.Qm);
+
+            context.Copy(GetVec(op.Qd), context.Call(new _V128_V128(SoftFallback.MixColumns), n));
+        }
+    }
+}
diff --git a/ARMeilleure/Instructions/InstEmitSimdLogical32.cs b/ARMeilleure/Instructions/InstEmitSimdLogical32.cs
index 3698f332..6505e834 100644
--- a/ARMeilleure/Instructions/InstEmitSimdLogical32.cs
+++ b/ARMeilleure/Instructions/InstEmitSimdLogical32.cs
@@ -55,6 +55,18 @@ namespace ARMeilleure.Instructions
             }
         }
 
+        public static void Veor_I(ArmEmitterContext context)
+        {
+            if (Optimizations.UseSse2)
+            {
+                EmitVectorBinaryOpF32(context, Intrinsic.X86Pxor, Intrinsic.X86Pxor);
+            }
+            else
+            {
+                EmitVectorBinaryOpZx32(context, (op1, op2) => context.BitwiseExclusiveOr(op1, op2));
+            }
+        }
+
         public static void Vorr_I(ArmEmitterContext context)
         {
             if (Optimizations.UseSse2)
diff --git a/ARMeilleure/Instructions/InstName.cs b/ARMeilleure/Instructions/InstName.cs
index 5e92da0a..e217c6ec 100644
--- a/ARMeilleure/Instructions/InstName.cs
+++ b/ARMeilleure/Instructions/InstName.cs
@@ -547,6 +547,7 @@ namespace ARMeilleure.Instructions
         Vcvt,
         Vdiv,
         Vdup,
+        Veor,
         Vext,
         Vld1,
         Vld2,
-- 
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