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authorgdkchan <gab.dark.100@gmail.com>2022-09-09 22:09:11 -0300
committerGitHub <noreply@github.com>2022-09-09 22:09:11 -0300
commitc64524a240671cb3f8609e3454576e69e5948a60 (patch)
treeb02fe220963b33b4292adf7b4a5236dae6bc0b05 /ARMeilleure/Instructions/InstEmitMemory32.cs
parentdb45688aa8d0e63d3ffbe50351722ef32f8360f8 (diff)
Add ADD (zx imm12), NOP, MOV (rs), LDA, TBB, TBH, MOV (zx imm16) and CLZ thumb instructions (#3683)
* Add ADD (zx imm12), NOP, MOV (register shifted), LDA, TBB, TBH, MOV (zx imm16) and CLZ thumb instructions, fix LDRD, STRD, CBZ, CBNZ and BLX (reg) * Bump PPTC version
Diffstat (limited to 'ARMeilleure/Instructions/InstEmitMemory32.cs')
-rw-r--r--ARMeilleure/Instructions/InstEmitMemory32.cs16
1 files changed, 8 insertions, 8 deletions
diff --git a/ARMeilleure/Instructions/InstEmitMemory32.cs b/ARMeilleure/Instructions/InstEmitMemory32.cs
index e15f6a5b..17ec97aa 100644
--- a/ARMeilleure/Instructions/InstEmitMemory32.cs
+++ b/ARMeilleure/Instructions/InstEmitMemory32.cs
@@ -204,15 +204,15 @@ namespace ARMeilleure.Instructions
context.BranchIfTrue(lblBigEndian, GetFlag(PState.EFlag));
- Load(op.Rt, 0, WordSizeLog2);
- Load(op.Rt | 1, 4, WordSizeLog2);
+ Load(op.Rt, 0, WordSizeLog2);
+ Load(op.Rt2, 4, WordSizeLog2);
context.Branch(lblEnd);
context.MarkLabel(lblBigEndian);
- Load(op.Rt | 1, 0, WordSizeLog2);
- Load(op.Rt, 4, WordSizeLog2);
+ Load(op.Rt2, 0, WordSizeLog2);
+ Load(op.Rt, 4, WordSizeLog2);
context.MarkLabel(lblEnd);
}
@@ -237,15 +237,15 @@ namespace ARMeilleure.Instructions
context.BranchIfTrue(lblBigEndian, GetFlag(PState.EFlag));
- Store(op.Rt, 0, WordSizeLog2);
- Store(op.Rt | 1, 4, WordSizeLog2);
+ Store(op.Rt, 0, WordSizeLog2);
+ Store(op.Rt2, 4, WordSizeLog2);
context.Branch(lblEnd);
context.MarkLabel(lblBigEndian);
- Store(op.Rt | 1, 0, WordSizeLog2);
- Store(op.Rt, 4, WordSizeLog2);
+ Store(op.Rt2, 0, WordSizeLog2);
+ Store(op.Rt, 4, WordSizeLog2);
context.MarkLabel(lblEnd);
}