diff options
| author | merry <git@mary.rs> | 2022-09-13 22:25:37 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-09-13 18:25:37 -0300 |
| commit | e05bf90af600f5c75a13a0b4113b7fc6a641ff6a (patch) | |
| tree | 87c8d482dcba254aa39221a406490d23378a3f87 /ARMeilleure/Decoders/OpCode32SimdReg.cs | |
| parent | 66f16f43921bdd6d0f706d09aa37166d374dec2e (diff) | |
T32: Implement Asimd instructions (#3692)
Diffstat (limited to 'ARMeilleure/Decoders/OpCode32SimdReg.cs')
| -rw-r--r-- | ARMeilleure/Decoders/OpCode32SimdReg.cs | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/ARMeilleure/Decoders/OpCode32SimdReg.cs b/ARMeilleure/Decoders/OpCode32SimdReg.cs index 50d1d24d..1c46b0e0 100644 --- a/ARMeilleure/Decoders/OpCode32SimdReg.cs +++ b/ARMeilleure/Decoders/OpCode32SimdReg.cs @@ -8,9 +8,10 @@ public int In => GetQuadwordSubindex(Vn) << (3 - Size); public int Fn => GetQuadwordSubindex(Vn) << (1 - (Size & 1)); - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdReg(inst, address, opCode); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdReg(inst, address, opCode, false); + public new static OpCode CreateT32(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdReg(inst, address, opCode, true); - public OpCode32SimdReg(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) + public OpCode32SimdReg(InstDescriptor inst, ulong address, int opCode, bool isThumb) : base(inst, address, opCode, isThumb) { Vn = ((opCode >> 3) & 0x10) | ((opCode >> 16) & 0xf); |