From e05bf90af600f5c75a13a0b4113b7fc6a641ff6a Mon Sep 17 00:00:00 2001 From: merry Date: Tue, 13 Sep 2022 22:25:37 +0100 Subject: T32: Implement Asimd instructions (#3692) --- ARMeilleure/Decoders/OpCode32SimdReg.cs | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) (limited to 'ARMeilleure/Decoders/OpCode32SimdReg.cs') diff --git a/ARMeilleure/Decoders/OpCode32SimdReg.cs b/ARMeilleure/Decoders/OpCode32SimdReg.cs index 50d1d24d..1c46b0e0 100644 --- a/ARMeilleure/Decoders/OpCode32SimdReg.cs +++ b/ARMeilleure/Decoders/OpCode32SimdReg.cs @@ -8,9 +8,10 @@ public int In => GetQuadwordSubindex(Vn) << (3 - Size); public int Fn => GetQuadwordSubindex(Vn) << (1 - (Size & 1)); - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdReg(inst, address, opCode); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdReg(inst, address, opCode, false); + public new static OpCode CreateT32(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdReg(inst, address, opCode, true); - public OpCode32SimdReg(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) + public OpCode32SimdReg(InstDescriptor inst, ulong address, int opCode, bool isThumb) : base(inst, address, opCode, isThumb) { Vn = ((opCode >> 3) & 0x10) | ((opCode >> 16) & 0xf); -- cgit v1.2.3