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authorTSR Berry <20988865+TSRBerry@users.noreply.github.com>2023-04-08 01:22:00 +0200
committerMary <thog@protonmail.com>2023-04-27 23:51:14 +0200
commitcee712105850ac3385cd0091a923438167433f9f (patch)
tree4a5274b21d8b7f938c0d0ce18736d3f2993b11b1 /ARMeilleure/Decoders/OpCode32SimdLong.cs
parentcd124bda587ef09668a971fa1cac1c3f0cfc9f21 (diff)
Move solution and projects to src
Diffstat (limited to 'ARMeilleure/Decoders/OpCode32SimdLong.cs')
-rw-r--r--ARMeilleure/Decoders/OpCode32SimdLong.cs30
1 files changed, 0 insertions, 30 deletions
diff --git a/ARMeilleure/Decoders/OpCode32SimdLong.cs b/ARMeilleure/Decoders/OpCode32SimdLong.cs
deleted file mode 100644
index 8d64d673..00000000
--- a/ARMeilleure/Decoders/OpCode32SimdLong.cs
+++ /dev/null
@@ -1,30 +0,0 @@
-namespace ARMeilleure.Decoders
-{
- class OpCode32SimdLong : OpCode32SimdBase
- {
- public bool U { get; }
-
- public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdLong(inst, address, opCode, false);
- public static OpCode CreateT32(InstDescriptor inst, ulong address, int opCode) => new OpCode32SimdLong(inst, address, opCode, true);
-
- public OpCode32SimdLong(InstDescriptor inst, ulong address, int opCode, bool isThumb) : base(inst, address, opCode, isThumb)
- {
- int imm3h = (opCode >> 19) & 0x7;
-
- // The value must be a power of 2, otherwise it is the encoding of another instruction.
- switch (imm3h)
- {
- case 1: Size = 0; break;
- case 2: Size = 1; break;
- case 4: Size = 2; break;
- }
-
- U = ((opCode >> (isThumb ? 28 : 24)) & 0x1) != 0;
-
- RegisterSize = RegisterSize.Simd64;
-
- Vd = ((opCode >> 18) & 0x10) | ((opCode >> 12) & 0xf);
- Vm = ((opCode >> 1) & 0x10) | ((opCode >> 0) & 0xf);
- }
- }
-}