diff options
| author | Merry <MerryMage@users.noreply.github.com> | 2018-02-14 22:01:36 +0000 |
|---|---|---|
| committer | gdkchan <gab.dark.100@gmail.com> | 2018-02-14 19:01:36 -0300 |
| commit | 7c4346685cc1bb66f91b584af706c0cb7d372f00 (patch) | |
| tree | 9fbb560031997fa7e507ce0e1a2b820e960de6e2 | |
| parent | 7791e1fe369d9dbcb43ec5c6d406df664219057c (diff) | |
AInstEmitAluHelper: Simplify EmitAddsVCheck (#14)
| -rw-r--r-- | Ryujinx/Cpu/Instruction/AInstEmitAluHelper.cs | 13 |
1 files changed, 2 insertions, 11 deletions
diff --git a/Ryujinx/Cpu/Instruction/AInstEmitAluHelper.cs b/Ryujinx/Cpu/Instruction/AInstEmitAluHelper.cs index 367c3b75..b526c553 100644 --- a/Ryujinx/Cpu/Instruction/AInstEmitAluHelper.cs +++ b/Ryujinx/Cpu/Instruction/AInstEmitAluHelper.cs @@ -21,22 +21,13 @@ namespace ChocolArm64.Instruction public static void EmitAddsVCheck(AILEmitterCtx Context) { - //V = (Rd ^ Rn) & (Rd ^ Rm) & ~(Rn ^ Rm) < 0 - Context.EmitSttmp(); - Context.EmitLdtmp(); - Context.EmitLdtmp(); + //V = (Rd ^ Rn) & ~(Rn ^ Rm) < 0 + Context.Emit(OpCodes.Dup); EmitDataLoadRn(Context); Context.Emit(OpCodes.Xor); - Context.EmitLdtmp(); - - EmitDataLoadOper2(Context); - - Context.Emit(OpCodes.Xor); - Context.Emit(OpCodes.And); - EmitDataLoadOpers(Context); Context.Emit(OpCodes.Xor); |
