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| author | ReinUsesLisp <reinuseslisp@airmail.cc> | 2018-12-20 22:41:31 -0300 |
|---|---|---|
| committer | ReinUsesLisp <reinuseslisp@airmail.cc> | 2019-01-15 17:54:49 -0300 |
| commit | 5e639bfcf6d764714cc9814fc47142ca85f889cf (patch) | |
| tree | 29f4a84ea1beb8636352f10b0e6513977b3ed50d /src/video_core/shader/shader_ir.h | |
| parent | 4aaa2192b993411f63d46a57b93e9e787b6a836d (diff) | |
shader_ir: Add register getter
Diffstat (limited to 'src/video_core/shader/shader_ir.h')
| -rw-r--r-- | src/video_core/shader/shader_ir.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/video_core/shader/shader_ir.h b/src/video_core/shader/shader_ir.h index db06d51ca..30b75c3ed 100644 --- a/src/video_core/shader/shader_ir.h +++ b/src/video_core/shader/shader_ir.h @@ -610,6 +610,8 @@ private: return Immediate(*reinterpret_cast<const u32*>(&value)); } + /// Generates a node for a passed register. + Node GetRegister(Tegra::Shader::Register reg); /// Generates a node representing a 19-bit immediate value Node GetImmediate19(Tegra::Shader::Instruction instr); /// Generates a node representing a 32-bit immediate value |