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authorbunnei <bunneidev@gmail.com>2018-08-30 10:31:26 -0400
committerGitHub <noreply@github.com>2018-08-30 10:31:26 -0400
commitd6accf96ff08450f17c9ec71425037aa2dbddd7f (patch)
treee9110ef0cd78b866ced55aac4aeeefa458c66bc9 /src/video_core/renderer_opengl
parent5094dfa081c7275e35496374a42996b11f0f6005 (diff)
parentb1ccd8843467e43838e19c50dcfcbc2ff0b3bc0b (diff)
Merge pull request #1200 from bunnei/improve-ipa
gl_shader_decompiler: Improve IPA for Pass mode with Position attribute.
Diffstat (limited to 'src/video_core/renderer_opengl')
-rw-r--r--src/video_core/renderer_opengl/gl_shader_decompiler.cpp34
1 files changed, 33 insertions, 1 deletions
diff --git a/src/video_core/renderer_opengl/gl_shader_decompiler.cpp b/src/video_core/renderer_opengl/gl_shader_decompiler.cpp
index 7e5ebfe24..7b6eb25a4 100644
--- a/src/video_core/renderer_opengl/gl_shader_decompiler.cpp
+++ b/src/video_core/renderer_opengl/gl_shader_decompiler.cpp
@@ -2100,7 +2100,39 @@ private:
}
case OpCode::Id::IPA: {
const auto& attribute = instr.attribute.fmt28;
- regs.SetRegisterToInputAttibute(instr.gpr0, attribute.element, attribute.index);
+ const auto& reg = instr.gpr0;
+ switch (instr.ipa.mode) {
+ case Tegra::Shader::IpaMode::Pass:
+ if (stage == Maxwell3D::Regs::ShaderStage::Fragment &&
+ attribute.index == Attribute::Index::Position) {
+ switch (attribute.element) {
+ case 0:
+ shader.AddLine(regs.GetRegisterAsFloat(reg) + " = gl_FragCoord.x;");
+ break;
+ case 1:
+ shader.AddLine(regs.GetRegisterAsFloat(reg) + " = gl_FragCoord.y;");
+ break;
+ case 2:
+ shader.AddLine(regs.GetRegisterAsFloat(reg) + " = gl_FragCoord.z;");
+ break;
+ case 3:
+ shader.AddLine(regs.GetRegisterAsFloat(reg) + " = 1.0;");
+ break;
+ }
+ } else {
+ regs.SetRegisterToInputAttibute(reg, attribute.element, attribute.index);
+ }
+ break;
+ case Tegra::Shader::IpaMode::None:
+ regs.SetRegisterToInputAttibute(reg, attribute.element, attribute.index);
+ break;
+ default:
+ LOG_CRITICAL(HW_GPU, "Unhandled IPA mode: {}",
+ static_cast<u32>(instr.ipa.mode.Value()));
+ UNREACHABLE();
+ regs.SetRegisterToInputAttibute(reg, attribute.element, attribute.index);
+ }
+
break;
}
case OpCode::Id::SSY: {