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authorFernandoS27 <fsahmkow27@gmail.com>2018-10-19 12:17:02 -0400
committerFernandoS27 <fsahmkow27@gmail.com>2018-10-28 19:16:41 -0400
commit3aa8b644a921020beb91109f284ae86dc2f7e189 (patch)
treefb5430bbc80ebae720492760b82d2f4986298ce8 /src/video_core/engines
parentb5f8a5f0a3558cfffea1c91291ecb857ccb3e862 (diff)
Assert Control Flow Instructions using Control Codes
Diffstat (limited to 'src/video_core/engines')
-rw-r--r--src/video_core/engines/shader_bytecode.h3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/video_core/engines/shader_bytecode.h b/src/video_core/engines/shader_bytecode.h
index 141b9159b..55763332e 100644
--- a/src/video_core/engines/shader_bytecode.h
+++ b/src/video_core/engines/shader_bytecode.h
@@ -1232,6 +1232,7 @@ union Instruction {
BitField<60, 1, u64> is_b_gpr;
BitField<59, 1, u64> is_c_gpr;
BitField<20, 24, s64> smem_imm;
+ BitField<0, 5, ControlCode> flow_control_code;
Attribute attribute;
Sampler sampler;
@@ -1658,4 +1659,4 @@ private:
}
};
-} // namespace Tegra::Shader \ No newline at end of file
+} // namespace Tegra::Shader