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authorReinUsesLisp <reinuseslisp@airmail.cc>2018-09-25 19:41:21 -0300
committerReinUsesLisp <reinuseslisp@airmail.cc>2018-09-25 21:07:00 -0300
commitab65fde9f489ca32aa7bd3a7e7bcd1f92a61c0d1 (patch)
treeae8fd84ba5c5c3beeed1b9e3f6c4ff425f1a3d46 /src/video_core/engines/maxwell_compute.cpp
parent7b81e1e52565ee867c285e2b0c2526f8d4b82581 (diff)
video_core: Add asserts for CS, TFB and alpha testing
Add asserts for compute shader dispatching, transform feedback being enabled and alpha testing. These have in common that they'll probably break rendering without logging.
Diffstat (limited to 'src/video_core/engines/maxwell_compute.cpp')
-rw-r--r--src/video_core/engines/maxwell_compute.cpp19
1 files changed, 18 insertions, 1 deletions
diff --git a/src/video_core/engines/maxwell_compute.cpp b/src/video_core/engines/maxwell_compute.cpp
index e4e5f9e5e..59e28b22d 100644
--- a/src/video_core/engines/maxwell_compute.cpp
+++ b/src/video_core/engines/maxwell_compute.cpp
@@ -2,12 +2,29 @@
// Licensed under GPLv2 or any later version
// Refer to the license.txt file included.
+#include "common/logging/log.h"
+#include "core/core.h"
#include "video_core/engines/maxwell_compute.h"
namespace Tegra {
namespace Engines {
-void MaxwellCompute::WriteReg(u32 method, u32 value) {}
+void MaxwellCompute::WriteReg(u32 method, u32 value) {
+ ASSERT_MSG(method < Regs::NUM_REGS,
+ "Invalid MaxwellCompute register, increase the size of the Regs structure");
+
+ regs.reg_array[method] = value;
+
+ switch (method) {
+ case MAXWELL_COMPUTE_REG_INDEX(compute): {
+ LOG_CRITICAL(HW_GPU, "Compute shaders are not implemented");
+ UNREACHABLE();
+ break;
+ }
+ default:
+ break;
+ }
+}
} // namespace Engines
} // namespace Tegra