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authorbunnei <bunneidev@gmail.com>2020-05-03 02:43:18 -0400
committerGitHub <noreply@github.com>2020-05-03 02:43:18 -0400
commit2aff0b473338655fba08f83c6a4c0af808b6d4a9 (patch)
treeaae207eac2560d76f835a0eba3511b36fcf4a571 /src/video_core/buffer_cache
parenta925ae79ff848b1f6f784e660ce59744667b50b7 (diff)
parentfe931ac9761a813c8e7d195cf99bf68ff324839c (diff)
Merge pull request #3808 from ReinUsesLisp/wait-for-idle
{maxwell_3d,buffer_cache}: Implement memory barriers using 3D registers
Diffstat (limited to 'src/video_core/buffer_cache')
-rw-r--r--src/video_core/buffer_cache/buffer_cache.h6
1 files changed, 0 insertions, 6 deletions
diff --git a/src/video_core/buffer_cache/buffer_cache.h b/src/video_core/buffer_cache/buffer_cache.h
index 398f16181..56e570994 100644
--- a/src/video_core/buffer_cache/buffer_cache.h
+++ b/src/video_core/buffer_cache/buffer_cache.h
@@ -88,10 +88,6 @@ public:
map->MarkAsWritten(true);
MarkRegionAsWritten(map->GetStart(), map->GetEnd() - 1);
}
- } else {
- if (map->IsWritten()) {
- WriteBarrier();
- }
}
return {ToHandle(block), static_cast<u64>(block->GetOffset(cpu_addr))};
@@ -253,8 +249,6 @@ protected:
virtual BufferType ToHandle(const OwnerBuffer& storage) = 0;
- virtual void WriteBarrier() = 0;
-
virtual OwnerBuffer CreateBlock(VAddr cpu_addr, std::size_t size) = 0;
virtual void UploadBlockData(const OwnerBuffer& buffer, std::size_t offset, std::size_t size,