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| author | Feng Chen <VonChenPlus@gmail.com> | 2021-12-18 13:57:14 +0800 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2021-12-18 13:57:14 +0800 |
| commit | e49184e6069a9d791d2df3c1958f5c4b1187e124 (patch) | |
| tree | b776caf722e0be0e680f67b0ad0842628162ef1c /src/core/arm/dynarmic/arm_dynarmic_64.cpp | |
| parent | 4dd85f86a89338ff84d05a3981c14f6de1be4606 (diff) | |
| parent | 77d06d5df02d18da381bcd572ce11fee790d9edf (diff) | |
Merge branch 'yuzu-emu:master' into convert_legacy
Diffstat (limited to 'src/core/arm/dynarmic/arm_dynarmic_64.cpp')
| -rw-r--r-- | src/core/arm/dynarmic/arm_dynarmic_64.cpp | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/src/core/arm/dynarmic/arm_dynarmic_64.cpp b/src/core/arm/dynarmic/arm_dynarmic_64.cpp index 4e73cc03a..56836bd05 100644 --- a/src/core/arm/dynarmic/arm_dynarmic_64.cpp +++ b/src/core/arm/dynarmic/arm_dynarmic_64.cpp @@ -86,6 +86,26 @@ public: num_instructions, MemoryReadCode(pc)); } + void InstructionCacheOperationRaised(Dynarmic::A64::InstructionCacheOperation op, + VAddr value) override { + switch (op) { + case Dynarmic::A64::InstructionCacheOperation::InvalidateByVAToPoU: { + static constexpr u64 ICACHE_LINE_SIZE = 64; + + const u64 cache_line_start = value & ~(ICACHE_LINE_SIZE - 1); + parent.InvalidateCacheRange(cache_line_start, ICACHE_LINE_SIZE); + break; + } + case Dynarmic::A64::InstructionCacheOperation::InvalidateAllToPoU: + parent.ClearInstructionCache(); + break; + case Dynarmic::A64::InstructionCacheOperation::InvalidateAllToPoUInnerSharable: + default: + LOG_DEBUG(Core_ARM, "Unprocesseed instruction cache operation: {}", op); + break; + } + } + void ExceptionRaised(u64 pc, Dynarmic::A64::Exception exception) override { switch (exception) { case Dynarmic::A64::Exception::WaitForInterrupt: |
