aboutsummaryrefslogtreecommitdiff
path: root/src/core/arm/dynarmic/arm_dynarmic_64.cpp
diff options
context:
space:
mode:
authorbunnei <bunneidev@gmail.com>2020-11-13 23:20:32 -0800
committerbunnei <bunneidev@gmail.com>2020-11-29 01:31:52 -0800
commit63fd1bb50302867b233325f253b1e2abbc379875 (patch)
tree65204a55cc87b2b4ef7260744ff96fabc813c9f6 /src/core/arm/dynarmic/arm_dynarmic_64.cpp
parentc0870315fd89dfeabdbe5833d52e753a5d8417ea (diff)
core: arm: Implement InvalidateCacheRange for CPU cache invalidation.
Diffstat (limited to 'src/core/arm/dynarmic/arm_dynarmic_64.cpp')
-rw-r--r--src/core/arm/dynarmic/arm_dynarmic_64.cpp7
1 files changed, 7 insertions, 0 deletions
diff --git a/src/core/arm/dynarmic/arm_dynarmic_64.cpp b/src/core/arm/dynarmic/arm_dynarmic_64.cpp
index 1c9fd18b5..0f0585d0f 100644
--- a/src/core/arm/dynarmic/arm_dynarmic_64.cpp
+++ b/src/core/arm/dynarmic/arm_dynarmic_64.cpp
@@ -322,6 +322,13 @@ void ARM_Dynarmic_64::ClearInstructionCache() {
jit->ClearCache();
}
+void ARM_Dynarmic_64::InvalidateCacheRange(VAddr addr, std::size_t size) {
+ if (!jit) {
+ return;
+ }
+ jit->InvalidateCacheRange(addr, size);
+}
+
void ARM_Dynarmic_64::ClearExclusiveState() {
jit->ClearExclusiveState();
}