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authorSubv <subv2112@gmail.com>2018-07-20 19:57:45 -0500
committerSubv <subv2112@gmail.com>2018-07-20 19:57:45 -0500
commitd84eb9dac64f314adcef2c374de245012f658b1d (patch)
tree56720a5bce5d1a285dda01c16bfcb1dd57e53054 /src/core/arm/dynarmic/arm_dynarmic.cpp
parentf36affdbe3727e21b6b0bdc3bef562ada6abe2c8 (diff)
CPU: Save and restore the TPIDR_EL0 system register on every context switch.
Note that there's currently a dynarmic bug preventing this register from being written.
Diffstat (limited to 'src/core/arm/dynarmic/arm_dynarmic.cpp')
-rw-r--r--src/core/arm/dynarmic/arm_dynarmic.cpp8
1 files changed, 8 insertions, 0 deletions
diff --git a/src/core/arm/dynarmic/arm_dynarmic.cpp b/src/core/arm/dynarmic/arm_dynarmic.cpp
index 3572ee7b9..df47d5ee8 100644
--- a/src/core/arm/dynarmic/arm_dynarmic.cpp
+++ b/src/core/arm/dynarmic/arm_dynarmic.cpp
@@ -196,6 +196,14 @@ void ARM_Dynarmic::SetTlsAddress(u64 address) {
cb->tpidrro_el0 = address;
}
+u64 ARM_Dynarmic::GetTPIDR_EL0() const {
+ return cb->tpidr_el0;
+}
+
+void ARM_Dynarmic::SetTPIDR_EL0(u64 value) {
+ cb->tpidr_el0 = value;
+}
+
void ARM_Dynarmic::SaveContext(ARM_Interface::ThreadContext& ctx) {
ctx.cpu_registers = jit->GetRegisters();
ctx.sp = jit->GetSP();