1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
|
using ChocolArm64.Decoder;
using ChocolArm64.Decoder32;
using ChocolArm64.Memory;
using ChocolArm64.State;
using static ChocolArm64.Instruction32.A32InstInterpretHelper;
namespace ChocolArm64.Instruction32
{
static partial class A32InstInterpret
{
public static void B(AThreadState State, AMemory Memory, AOpCode OpCode)
{
A32OpCodeBImmAl Op = (A32OpCodeBImmAl)OpCode;
if (IsConditionTrue(State, Op.Cond))
{
BranchWritePc(State, GetPc(State) + (uint)Op.Imm);
}
}
public static void Bl(AThreadState State, AMemory Memory, AOpCode OpCode)
{
Blx(State, Memory, OpCode, false);
}
public static void Blx(AThreadState State, AMemory Memory, AOpCode OpCode)
{
Blx(State, Memory, OpCode, true);
}
public static void Blx(AThreadState State, AMemory Memory, AOpCode OpCode, bool X)
{
A32OpCodeBImmAl Op = (A32OpCodeBImmAl)OpCode;
if (IsConditionTrue(State, Op.Cond))
{
uint Pc = GetPc(State);
if (State.Thumb)
{
State.R14 = Pc | 1;
}
else
{
State.R14 = Pc - 4U;
}
if (X)
{
State.Thumb = !State.Thumb;
}
if (!State.Thumb)
{
Pc &= ~3U;
}
BranchWritePc(State, Pc + (uint)Op.Imm);
}
}
private static void BranchWritePc(AThreadState State, uint Pc)
{
State.R15 = State.Thumb
? Pc & ~1U
: Pc & ~3U;
}
}
}
|
