aboutsummaryrefslogtreecommitdiff
path: root/ARMeilleure
AgeCommit message (Collapse)Author
2021-04-18Add inlined on translation call counting (#2190)FICTURE7
* Add EntryTable<TEntry> * Add on translation call counting * Add Counter * Add PPTC support * Make Counter a generic & use a 32-bit counter instead * Return false on overflow * Set PPTC version * Print more information about the rejit queue * Make Counter<T> disposable * Remove Block.TailCall since it is not used anymore * Apply suggestions from code review Address gdkchan's feedback Co-authored-by: gdkchan <gab.dark.100@gmail.com> * Fix more stale docs * Remove rejit requests queue logging * Make Counter<T> finalizable Most certainly quite an odd use case. * Make EntryTable<T>.TryAllocate set entry to default * Re-trigger CI * Dispose Counters before they hit the finalizer queue * Re-trigger CI Just for good measure... * Make EntryTable<T> expandable * EntryTable is now expandable instead of being a fixed slab. * Remove EntryTable<T>.TryAllocate * Remove Counter<T>.TryCreate Address LDj3SNuD's feedback * Apply suggestions from code review Address LDj3SNuD's feedback Co-authored-by: LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com> * Remove useless return * POH approach, but the sequel * Revert "POH approach, but the sequel" This reverts commit 5f5abaa24735726ff2db367dc74f98055d4f4cba. The sequel got shelved * Add extra documentation Co-authored-by: gdkchan <gab.dark.100@gmail.com> Co-authored-by: LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com>
2021-04-13PPTC vs. giant ExeFS. (#2168)LDj3SNuD
* PPTC vs. giant ExeFS. * InternalVersion = 2168 * Add new heuristic algorithm for calculating the number of threads for parallel translations that also takes into account the user's free physical memory and not just the number of CPU cores. * Nit. * Add an outer Header structure and add the hashes for both this new structure and the existing "inner" Header structure. * InternalVersion = 2169
2021-04-07(CPU) Fix CRC32 instruction when constant values are used as input (#2183)gdkchan
2021-04-02Improve `StoreToContext` emission (#2155)FICTURE7
* Improve StoreToContext emission Hoist StoreToContext in dynamic branch fast & slow paths out into their predecessor. Reduces register pressure, code size and compile time because we're throwing less stuff down the pipeline. * Set PTC internal version * Turn EmitDynamicTableCall private * Re-trigger CI
2021-04-02Reduce allocation during SSA construction (#2162)FICTURE7
* Reduce allocation during SSA construction * Re-trigger CI
2021-03-25Add Sqdmulh_Ve & Sqrdmulh_Ve Inst.s with Tests. (#2139)LDj3SNuD
2021-03-22Fix inconsistencies in progress reporting (#2129)mageven
Signal and setup events correctly Eliminate possible races Use a single event Mark volatiles and reduce scope of waithandles Common handler 100ms -> 50ms
2021-03-03Add progress reporting to PTC and Shader Cache (#2057)mageven
* UI changes * Add progress reporting to PTC & ShaderCache * Account for null events and expand docs Co-authored-by: Joshi234 <46032261+Joshi234@users.noreply.github.com>
2021-02-23PPTC: Fix unwanted propagation of a relocatable constant in a specific case. ↵LDj3SNuD
(#1990) * Fix unwanted propagation of a relocatable constant in a specific case. * Ptc.InternalVersion = 1990 * Nit to retrigger the Checks.
2021-02-22Implement VCNT instruction (#1963)mageven
* Implement VCNT based on AArch64 CNT Add tests * Update PTC version * Address LDj's comments * Explicit size in encoding * Tighter tests * Replace SoftFallback with IR helper Co-authored-by: LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com> * Reduce one BitwiseAnd from IR fallback Based on popcount64b from https://en.wikipedia.org/wiki/Hamming_weight#Efficient_implementation * Rename parameter and add assert Co-authored-by: LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com> Co-authored-by: LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com>
2021-02-22PPTC & Pool Enhancements. (#1968)LDj3SNuD
* PPTC & Pool Enhancements. * Avoid buffer allocations in CodeGenContext.GetCode(). Avoid stream allocations in PTC.PtcInfo. Refactoring/nits. * Use XXHash128, for Ptc.Load & Ptc.Save, x10 faster than Md5. * Why not a nice Span. * Added a simple PtcFormatter library for deserialization/serialization, which does not require reflection, in use at PtcJumpTable and PtcProfiler; improves maintainability and simplicity/readability of affected code. * Nits. * Revert #1987. * Revert "Revert #1987." This reverts commit 998be765cf7f7da5ff0c1c08de704c9012b0f49c.
2021-02-21Turn Copy into Fill in HybridAllocator (#2010)FICTURE7
* Turn Copy into Fill in HybridAllocator * Set PTC internal verison
2021-02-17Fix memory tracking performance regression (#2026)gdkchan
* Fix memory tracking performance regression * Set PTC version
2021-02-16Validate CPU virtual addresses on access (#1987)gdkchan
* Enable PTE null checks again * Do address validation on EmitPtPointerLoad, and make it branchless * PTC version increment * Mask of pointer tag for exclusive access * Move mask to the correct place Co-authored-by: LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com>
2021-02-08Optimization | Modify Add (Integer) Instruction to use LEA instead. (#1971)sharmander
* Optimization | Modify Add Instruction to use LEA instead. Currently, the add instruction requires 4 registers to take place. By using LEA, we can effectively perform the same working using 3 registers, reducing memory spills and improving translation efficiency. * Fix IsSameOperandDestSrc1 Check for Add * Use LEA if Dest != SRC1 * Update IsSameOperandDestSrc1 to account for Cases where Dest and Src1 can be same for add * Fix error in logic * Typo * Add paranthesis for clarity * Compare registers as requested. * Cleanup if statement, use same comparison method as generateCopy * Make change as recommended by gdk * Perform check only when Add calls are made * use ensure sametype for lea, fix else * Update comment * Update version #
2021-02-08Disable partial JIT invalidation on unmap (#1991)gdkchan
2021-01-28Lower precision of estimate instruction results to match Arm behavior (#1943)gdkchan
* Lower precision of estimate instruction results to match Arm behavior * PTC version update * Nits
2021-01-26Implement PRFM (register variant) as NOP (#1956)mageven
* Implement PRFM (register variant) as NOP Fix typo pfrm -> prfm Add comments to distinguish variants * Increment PTC version
2021-01-25Add VCLZ.* fast path (#1917)FICTURE7
* Add VCLZ fast path * Add VCLZ.8B/16B SSSE3 fast path * Add VCLZ.4H/8H SSSE3 fast path * Add VCLZ.2S/4S SSE2 fast path * Improve CLZ.4H/8H fast path * Improve CLZ.2S/4S fast path * Set PPTC version
2021-01-20CPU (A64): Add Fmaxnmp & Fminnmp Scalar Inst.s, Fast & Slow Paths; with ↵LDj3SNuD
Tests. (#1894)
2021-01-12Add a simple Pools Limiter. (#1830)LDj3SNuD
* Added support for offline invalidation, via PPTC, of low cq translations replaced by high cq translations; both on a single run and between runs. Added invalidation of .cache files in the event of reuse on a different user operating system. Added .info and .cache files invalidation in case of a failed stream decompression. Nits. * InternalVersion = 1712; * Nits. * Address comment. * Get rid of BinaryFormatter. Nits. * Move Ptc.LoadTranslations(). Nits. * Nits. * Fixed corner cases (in case backup copies have to be used). Added save logs. * Not core fixes. * Complement to the previous commit. Added load logs. Removed BinaryFormatter leftovers. * Add LoadTranslations log. * Nits. * Removed the search and management of LowCq overlapping functions. * Final increment of .info and .cache flags. * Nit. * Free up memory allocated by Pools during any PPTC translations at boot time. * Nit due to rebase. * Add a simple Pools Limiter. * Nits. * Fix missing JumpTable.RegisterFunction() due to rebase. Clear MemoryStreams as soon as possible, when they are no longer needed. * Code cleaning. * Nit for retrigger Checks. * Update Ptc.cs * Contextual refactoring of Translator. Ignore resetting of pools for DirectCallStubs. * Nit for retrigger Checks.
2021-01-04CPU (A64): Add Pmull_V Inst. with Clmul fast path for the "1/2D -> 1Q" ↵LDj3SNuD
variant & Sse fast path and slow path for both the "8/16B -> 8H" and "1/2D -> 1Q" variants; with Test. (#1817) * Add Pmull_V Sse fast path only, both "8/16B -> 8H" and "1/2D -> 1Q" variants; with Test. * Add Clmul fast path for the 128 bits variant. * Small optimisation (save 60 instructions) for the Sse fast path about the 128 bits variant. * Add slow path, both variants. Fix V128 Shl/Shr when shift = 0. * A32: Add Vmull_I P64 variant (slow path); not tested. * A32: Add Vmull_I_P8_P64 Test and fix P64 variant.
2020-12-24Hotfix for #1814Ac_K
2020-12-24Free up memory allocated by Pools during any PPTC translations at boot time. ↵LDj3SNuD
(#1814) * Added support for offline invalidation, via PPTC, of low cq translations replaced by high cq translations; both on a single run and between runs. Added invalidation of .cache files in the event of reuse on a different user operating system. Added .info and .cache files invalidation in case of a failed stream decompression. Nits. * InternalVersion = 1712; * Nits. * Address comment. * Get rid of BinaryFormatter. Nits. * Move Ptc.LoadTranslations(). Nits. * Nits. * Fixed corner cases (in case backup copies have to be used). Added save logs. * Not core fixes. * Complement to the previous commit. Added load logs. Removed BinaryFormatter leftovers. * Add LoadTranslations log. * Nits. * Removed the search and management of LowCq overlapping functions. * Final increment of .info and .cache flags. * Nit. * Free up memory allocated by Pools during any PPTC translations at boot time. * Nit due to rebase.
2020-12-17Fix Vnmls_S fast path (F64: losing input d value). Fix Vnmla_S & Vnmls_S ↵LDj3SNuD
slow paths (using fused inst.s). Fix Vfma_V slow path not using StandardFPSCRValue(). (#1775) * Fix Vnmls_S fast path (F64: losing input d value). Fix Vnmla_S & Vnmls_S slow paths (using fused inst.s). Add Vfma_S & Vfms_S Fma fast paths. Add Vfnma_S inst. with Fma/Sse fast paths and slow path. Add Vfnms_S Sse fast path. Add Tests for affected inst.s. Nits. * InternalVersion = 1775 * Nits. * Fix Vfma_V slow path not using StandardFPSCRValue(). * Nit: Fix Vfma_V order. * Add Vfms_V Sse fast path and slow path. * Add Vfma_V and Vfms_V Test.
2020-12-17PPTC Follow-up. (#1712)LDj3SNuD
* Added support for offline invalidation, via PPTC, of low cq translations replaced by high cq translations; both on a single run and between runs. Added invalidation of .cache files in the event of reuse on a different user operating system. Added .info and .cache files invalidation in case of a failed stream decompression. Nits. * InternalVersion = 1712; * Nits. * Address comment. * Get rid of BinaryFormatter. Nits. * Move Ptc.LoadTranslations(). Nits. * Nits. * Fixed corner cases (in case backup copies have to be used). Added save logs. * Not core fixes. * Complement to the previous commit. Added load logs. Removed BinaryFormatter leftovers. * Add LoadTranslations log. * Nits. * Removed the search and management of LowCq overlapping functions. * Final increment of .info and .cache flags. * Nit. * GetIndirectFunctionAddress(): Validate that writing actually takes place in dynamic table memory range (and not elsewhere). * Fix Ptc.UpdateInfo() due to rebase. * Nit for retrigger Checks. * Nit for retrigger Checks.
2020-12-16CPU: Implement VRINTX.F32 | VRINTX.F64 (#1776)sharmander
* Start implementation * Draft * Updated opcode. Needs verification. * Clean up code. * Update implementation and tests. * Update implemenation + tests * Get RM from FPSCR + Do not use emit/addintrinsic * Remove "fast" path, as recommended by gdk. * Variable DELETED. * Update ARMeilleure/Decoders/OpCodeTable.cs Co-authored-by: LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com> * Update ARMeilleure/Instructions/InstEmitSimdCvt32.cs Co-authored-by: LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com> * Update ARMeilleure/Instructions/InstEmitSimdCvt32.cs Co-authored-by: LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com> * Update ARMeilleure/Instructions/InstEmitSimdCvt32.cs Co-authored-by: LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com> * Move method * stringing things together :) Co-authored-by: LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com>
2020-12-16Clear JIT cache on exit (#1518)gdkchan
* Initial cache memory allocator implementation * Get rid of CallFlag * Perform cache cleanup on exit * Basic cache invalidation * Thats not how conditionals works in C# it seems * Set PTC version to PR number * Address PR feedback * Update InstEmitFlowHelper.cs * Flag clear on address is no longer needed * Do not include exit block in function size calculation * Dispose jump table * For future use * InternalVersion = 1519 (force retest). Co-authored-by: LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com>
2020-12-15CPU: Implement VFMA (Vector) (#1762)sharmander
* Implement VFMA.F64 * Simplify switch * Simplify FMA Instructions into their own IntrinsicType. * Remove whitespace * Fix indentation * Change tests for Vfnms -- disable inf / nan * Move args up, not description ;) * Implementation Complete. All Tests Pass (Slow / Fast Path) * Move location of function in assembler + test updates. * Shift params upwards * Remove unused function * Update PTC version. * Add comments / re-oreder opcode table. * Remove whitespace * Fix nit * Fix nit. * Fix whitespace * Wrong opcode was used by a bad merge. * Addressed rip's comments.
2020-12-14Fix pre-allocator shift instruction copy on a specific case (#1752)gdkchan
* Fix pre-allocator shift instruction copy on a specific case * Fix to make shift use int rather than long for constants
2020-12-13Fix register read after write on STREX implementation (#1801)gdkchan
* Fix register read after write on STREX implementation * PTC version update
2020-12-07CPU: Implement VFNMA.F32 | F.64 (#1783)sharmander
* Implement VFNMA.F<32/64> * Update PTC Version * Update Implementation & Renames & Correct Order * Fix alignment * Update implementation to not trigger assert * Actually use the intrinsic that makes sense :)
2020-12-07Add support for guest Fz (Fpcr) mode through host Ftz and Daz (Mxcsr) modes ↵LDj3SNuD
(fast paths). (#1630) * Add support for guest Fz (Fpcr) mode through host Ftz and Daz (Mxcsr) modes (fast paths). * Ptc.InternalVersion = 1630 * Nits. * Address comments. * Update Ptc.cs * Address comment.
2020-12-03CPU: Implement VFNMS.F32/64 (#1758)sharmander
* Add necessary methods / op-code * Enable Support for FMA Instruction Set * Add Intrinsics / Assembly Opcodes for VFMSUB231XX. * Add X86 Instructions for VFMSUB231XX * Implement VFNMS * Implement VFNMS Tests * Add special cases for FMA instructions. * Update PPTC Version * Remove unused Op * Move Check into Assert / Cleanup * Rename and cleanup * Whitespace * Whitespace / Rename * Re-sort * Address final requests * Implement VFMA.F64 * Simplify switch * Simplify FMA Instructions into their own IntrinsicType. * Remove whitespace * Fix indentation * Change tests for Vfnms -- disable inf / nan * Move args up, not description ;) * Undo vfma * Completely remove vfms code., * Fix order of instruction in assembler
2020-12-02IPC refactor part 2: Use ReplyAndReceive on HLE services and remove special ↵gdkchan
handling from kernel (#1458) * IPC refactor part 2: Use ReplyAndReceive on HLE services and remove special handling from kernel * Fix for applet transfer memory + some nits * Keep handles if possible to avoid server handle table exhaustion * Fix IPC ZeroFill bug * am: Correctly implement CreateManagedDisplayLayer and implement CreateManagedDisplaySeparableLayer CreateManagedDisplaySeparableLayer is requires since 10.x+ when appletResourceUserId != 0 * Make it exit properly * Make ServiceNotImplementedException show the full message again * Allow yielding execution to avoid starving other threads * Only wait if active * Merge IVirtualMemoryManager and IAddressSpaceManager * Fix Ro loading data from the wrong process Co-authored-by: Thog <me@thog.eu>
2020-11-20Use backup when PTC compression is corrupt (#1704)riperiperi
* Use backup when PTC compression is corrupt * Apply suggestions from code review Co-authored-by: LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com> Co-authored-by: LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com>
2020-11-18CPU (A64): Add FP16/FP32 fast paths (F16C Intrinsics) for Fcvt_S, Fcvtl_V & ↵LDj3SNuD
Fcvtn_V Instructions. Now HardwareCapabilities uses CpuId. (#1650) * net5.0 * CPU (A64): Add FP16/FP32 fast paths (F16C Intrinsics) for Fcvt_S, Fcvtl_V & Fcvtn_V Instructions. Switch to .NET 5.0. Nits. Tests performed successfully in both debug and release mode (for all instructions involved). * Address comment. * Update appveyor.yml * Revert "Update appveyor.yml" This reverts commit 27cdd59e8b90e227e6924d9c162af26c00a89013. * Remove Assembler CpuId. * Update appveyor.yml * Address comment.
2020-11-17shader cache: Fix Linux boot issues (#1709)Mary
* shader cache: Fix Linux boot issues This rollback the init logic back to previous state, and replicate the way PTC handle initialization. * shader cache: set default state of ready for translation event to false * Fix cpu unit tests
2020-11-15infra: Migrate to .NET 5 (#1694)Mary
* infra: Migrate to .NET 5 This migrate projects and CI to .NET 5 * Remove language version restrictions (now on 9.0 by default) * infra: pin .NET 5 to avoid later issues * infra: Cleanup csproj files * infra: update dependencies * infra: Add temporary workaround for a bug in Vector128.Create see https://github.com/dotnet/runtime/issues/44704 for more informations
2020-11-04Fix LiveInterval.Split (#1660)FICTURE7
Before when splitting intervals, the end of the range would be included in the split check, this can produce empty ranges in the child split. This in turn can affect spilling decisions since the child split will have a different start position and this empty range will get a register and move to the active set for a brief moment. For example: A = [153, 172[; [1899, 1916[; [1991, 2010[; [2397, 2414[; ... Split(A, 1916) A0 = [153, 172[; [1899, 1916[ A1 = [1916, 1916[; [1991, 2010[; [2397, 2414[; ...
2020-10-21Get rid of Reflection.Emit dependency on CPU and Shader projects (#1626)gdkchan
* Get rid of Reflection.Emit dependency on CPU and Shader projects * Remove useless private sets * Missed those due to the alignment
2020-10-16Memory Read/Write Tracking using Region Handles (#1272)riperiperi
* WIP Range Tracking - Texture invalidation seems to have large problems - Buffer/Pool invalidation may have problems - Mirror memory tracking puts an additional `add` in compiled code, we likely just want to make HLE access slower if this is the final solution. - Native project is in the messiest possible location. - [HACK] JIT memory access always uses native "fast" path - [HACK] Trying some things with texture invalidation and views. It works :) Still a few hacks, messy things, slow things More work in progress stuff (also move to memory project) Quite a bit faster now. - Unmapping GPU VA and CPU VA will now correctly update write tracking regions, and invalidate textures for the former. - The Virtual range list is now non-overlapping like the physical one. - Fixed some bugs where regions could leak. - Introduced a weird bug that I still need to track down (consistent invalid buffer in MK8 ribbon road) Move some stuff. I think we'll eventually just put the dll and so for this in a nuget package. Fix rebase. [WIP] MultiRegionHandle variable size ranges - Avoid reprotecting regions that change often (needs some tweaking) - There's still a bug in buffers, somehow. - Might want different api for minimum granularity Fix rebase issue Commit everything needed for software only tracking. Remove native components. Remove more native stuff. Cleanup Use a separate window for the background context, update opentk. (fixes linux) Some experimental changes Should get things working up to scratch - still need to try some things with flush/modification and res scale. Include address with the region action. Initial work to make range tracking work Still a ton of bugs Fix some issues with the new stuff. * Fix texture flush instability There's still some weird behaviour, but it's much improved without this. (textures with cpu modified data were flushing over it) * Find the destination texture for Buffer->Texture full copy Greatly improves performance for nvdec videos (with range tracking) * Further improve texture tracking * Disable Memory Tracking for view parents This is a temporary approach to better match behaviour on master (where invalidations would be soaked up by views, rather than trigger twice) The assumption is that when views are created to a texture, they will cover all of its data anyways. Of course, this can easily be improved in future. * Introduce some tracking tests. WIP * Complete base tests. * Add more tests for multiregion, fix existing test. * Cleanup Part 1 * Remove unnecessary code from memory tracking * Fix some inconsistencies with 3D texture rule. * Add dispose tests. * Use a background thread for the background context. Rather than setting and unsetting a context as current, doing the work on a dedicated thread with signals seems to be a bit faster. Also nerf the multithreading test a bit. * Copy to texture with matching alignment This extends the copy to work for some videos with unusual size, such as tutorial videos in SMO. It will only occur if the destination texture already exists at XCount size. * Track reads for buffer copies. Synchronize new buffers before copying overlaps. * Remove old texture flushing mechanisms. Range tracking all the way, baby. * Wake the background thread when disposing. Avoids a deadlock when games are closed. * Address Feedback 1 * Separate TextureCopy instance for background thread Also `BackgroundContextWorker.InBackground` for a more sensible idenfifier for if we're in a background thread. * Add missing XML docs. * Address Feedback * Maybe I should start drinking coffee. * Some more feedback. * Remove flush warning, Refocus window after making background context
2020-10-13Add Umaal & Vabd_I, Vabdl_I, Vaddl_I, Vhadd, Vqshrn, Vshll inst.s (slow ↵LDj3SNuD
paths). (#1577) * Add Umaal & Vabd_I, Vabdl_I, Vaddl_I, Vhadd, Vqshrn, Vshll inst.s (slow paths). No test provided (i.e. draft). * Ptc InternalVersion = 1577
2020-09-30Remove old, unused CPU optimization (#1586)gdkchan
2020-09-22IPC refactor part 1: Use explicit separate threads to process requests (#1447)gdkchan
* Changes to allow explicit management of service threads * Remove now unused code * Remove ThreadCounter, its no longer needed * Allow and use separate server per service, also fix exit issues * New policy change: PTC version now uses PR number
2020-09-19Fix host stack overflow caused by some recursive guest methods. (#1528)LDj3SNuD
* Fix host stack overflow caused by some recursive guest methods. * PPTC flag up. * Address comments. Co-authored-by: gdkchan <gab.dark.100@gmail.com>
2020-09-19Implement block placement (#1549)FICTURE7
* Implement block placement Implement a simple pass which re-orders cold blocks at the end of the list of blocks in the CFG. * Set PPTC version * Use Array.Resize Address gdkchan's feedback
2020-09-12Relax block ordering constraints (#1535)FICTURE7
* Relax block ordering constraints Before `block.Next` had to follow `block.ListNext`, now it does not. Instead `CodeGenerator` will now emit the necessary jump instructions to ensure control flow. This makes control flow and block order modifications easier. It also eliminates some simple cases of redundant branches. * Set PPTC version
2020-09-07Do not emit StoreToContext before Return (#1537)FICTURE7
* Do not emit StoreToContext before Return * Set PPTC version
2020-09-01SIMD&FP load/store with scale > 4 should be undefined (#1522)gdkchan
* SIMD&FP load/store with scale > 4 should be undefined * Catch more invalid encodings for FP&SIMD LDR/STR (reg variant) * Set PTC version to PR number
generated by cgit v1.2.3 (git 2.39.1) at 2026-06-11 03:24:06 +0000