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ARMeilleure
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Translation
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Delegates.cs
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Author
2023-04-27
Move solution and projects to src
TSR Berry
2023-04-11
ARMeilleure: Move TPIDR_EL0 and TPIDRRO_EL0 to NativeContext (#4661)
riperiperi
2022-12-27
Use new ArgumentNullException and ObjectDisposedException throw-helper API (#...
Berkan Diler
2022-09-20
Fpsr and Fpcr freed. (#3701)
LDj3SNuD
2022-09-19
Implemented in IR the managed methods of the ShlReg region of the SoftFallbac...
LDj3SNuD
2022-09-08
Implemented in IR the managed methods of the Saturating region ... (#3665)
LDj3SNuD
2022-07-06
Implement CPU FCVT Half <-> Double conversion variants (#3439)
gdkchan
2022-05-31
Refactor CPU interface to allow the implementation of other CPU emulators (#3...
gdkchan
2022-02-18
Enable CPU JIT cache invalidation (#2965)
gdkchan
2021-05-29
Add multi-level function table (#2228)
FICTURE7
2021-04-18
Add inlined on translation call counting (#2190)
FICTURE7
2021-02-22
Implement VCNT instruction (#1963)
mageven
2021-01-04
CPU (A64): Add Pmull_V Inst. with Clmul fast path for the "1/2D -> 1Q" varian...
LDj3SNuD
2020-12-16
Clear JIT cache on exit (#1518)
gdkchan
2020-12-07
Add support for guest Fz (Fpcr) mode through host Ftz and Daz (Mxcsr) modes (...
LDj3SNuD
2020-10-16
Memory Read/Write Tracking using Region Handles (#1272)
riperiperi
2020-08-08
CPU: This PR fixes Fpscr, among other things. (#1433)
LDj3SNuD
2020-07-30
Implement inline memory load/store exclusive and ordered (#1413)
gdkchan
2020-06-16
Add Profiled Persistent Translation Cache. (#769)
LDj3SNuD