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AgeCommit message (Expand)Author
2023-03-20ARMeilleure: Add initial support for AVX512 (EVEX encoding) (cont) (#4147)Wunk
2023-03-04Minor code formatting (#4498)gdkchan
2023-01-23Remove use of GetFunctionPointerForDelegate to get JIT cache function pointer...gdkchan
2023-01-12Arm64: Cpu feature detection (#4264)merry
2023-01-10Implement JIT Arm64 backend (#4114)gdkchan
2022-12-21Fix CPU FCVTN instruction implementation (slow path) (#4159)gdkchan
2022-12-18Revert "ARMeilleure: Add initial support for AVX512(EVEX encoding) (#3663)" (...gdkchan
2022-12-18ARMeilleure: Add initial support for AVX512(EVEX encoding) (#3663)Wunk
2022-10-19Do not clear the rejit queue when overlaps count is equal to 0. (#3721)LDj3SNuD
2022-10-19A32: Implement VCVTT, VCVTB (#3710)merry
2022-10-19A64: Add fast path for Fcvtas_Gp/S/V, Fcvtau_Gp/S/V and Frinta_S/V in… (#3712)LDj3SNuD
2022-10-02ARMeilleure: Add `gfni` acceleration (#3669)Wunk
2022-09-20Fpsr and Fpcr freed. (#3701)LDj3SNuD
2022-09-19Implemented in IR the managed methods of the ShlReg region of the SoftFallbac...LDj3SNuD
2022-09-14A32/T32/A64: Implement Hint instructions (CSDB, SEV, SEVL, WFE, WFI, YIELD) (...merry
2022-09-13Implement PLD and SUB (imm16) on T32, plus UADD8, SADD8, USUB8 and SSUB8 on b...gdkchan
2022-09-13Fix increment on Arm32 NEON VLDn/VSTn instructions with regs > 1 (#3695)gdkchan
2022-09-11Implement VRINT (vector) Arm32 NEON instructions (#3691)gdkchan
2022-09-10T32: Add Vfp instructions (#3690)merry
2022-09-10Implement Thumb (32-bit) memory (ordered), multiply, extension and bitfield i...gdkchan
2022-09-09Add ADD (zx imm12), NOP, MOV (rs), LDA, TBB, TBH, MOV (zx imm16) and CLZ thum...gdkchan
2022-09-09Implement VRSRA, VRSHRN, VQSHRUN, VQMOVN, VQMOVUN, VQADD, VQSUB, VRHADD, VPAD...gdkchan
2022-09-08Implemented in IR the managed methods of the Saturating region ... (#3665)LDj3SNuD
2022-08-25ARMeilleure: Hardware accelerate SHA256 (#3585)merry
2022-08-25Implement some 32-bit Thumb instructions (#3614)gdkchan
2022-08-18Removed unused usings. (#3593)Nicholas Rodine
2022-08-05Implement Arm32 Sha256 and MRS Rd, CPSR instructions (#3544)gdkchan
2022-07-06Implement CPU FCVT Half <-> Double conversion variants (#3439)gdkchan
2022-05-31Refactor CPU interface to allow the implementation of other CPU emulators (#3...gdkchan
2022-03-19InstEmitMemoryEx: Barrier after write on ordered store (#3193)merry
2022-03-05A32: Fix ALU immediate instructions (#3179)merry
2022-03-04Decoder: Exit on trapping instructions, and resume execution at trapping inst...merry
2022-03-04T32: Implement B, B.cond, BL, BLX (#3155)merry
2022-02-22T32: Implement ALU (shifted register) instructions (#3135)merry
2022-02-22A32: Fix BLX and BXWritePC (#3151)merry
2022-02-18Enable CPU JIT cache invalidation (#2965)gdkchan
2022-02-18Decoders: Add IOpCode32HasSetFlags (#3136)merry
2022-02-17ARMeilleure: Thumb support (All T16 instructions) (#3105)merry
2022-02-17Use ReadOnlySpan<byte> compiler optimization for static data (#3130)Berkan Diler
2022-02-11InstEmitMemory32: Literal loads always have word-aligned PC (#3104)merry
2022-02-08ARMeilleure: A32: Implement SHSUB8 and UHSUB8 (#3089)merry
2022-02-06ARMeilleure: A32: Implement SHADD8 (#3086)merry
2022-01-29Fix small precision error on CPU reciprocal estimate instructions (#3061)gdkchan
2022-01-21Add host CPU memory barriers for DMB/DSB and ordered load/store (#3015)gdkchan
2022-01-19Implement FCVTNS (Scalar GP) (#2953)sharmander
2022-01-16Fix return type mismatch on 32-bit titles (#3000)gdkchan
2022-01-04CPU - Implement FCVTMS (Vector) (#2937)sharmander
2021-12-19Implement CSDB instruction (#2927)gdkchan
2021-12-08Implement UHADD8 instruction (#2908)Piyachet Kanda
2021-09-29Use normal memory store path for DC ZVA (#2693)riperiperi