| Age | Commit message (Expand) | Author |
|---|---|---|
| 2023-04-27 | Move solution and projects to src | TSR Berry |
| 2023-04-11 | ARMeilleure: Move TPIDR_EL0 and TPIDRRO_EL0 to NativeContext (#4661) | riperiperi |
| 2023-04-10 | ARMeilleure: Respect FZ/RM flags for all floating point operations (#4618) | riperiperi |
| 2023-01-10 | Implement JIT Arm64 backend (#4114) | gdkchan |
| 2022-09-20 | Fpsr and Fpcr freed. (#3701) | LDj3SNuD |
| 2022-09-14 | A32/T32/A64: Implement Hint instructions (CSDB, SEV, SEVL, WFE, WFI, YIELD) (... | merry |
| 2022-05-31 | Refactor CPU interface to allow the implementation of other CPU emulators (#3... | gdkchan |
| 2022-02-18 | Enable CPU JIT cache invalidation (#2965) | gdkchan |
| 2021-09-29 | Use normal memory store path for DC ZVA (#2693) | riperiperi |
| 2021-08-17 | Reduce JIT GC allocations (#2515) | FICTURE7 |
| 2020-06-16 | Add Profiled Persistent Translation Cache. (#769) | LDj3SNuD |
| 2020-05-23 | Implement CNTVCT_EL0 (#1268) | mageven |
| 2019-11-14 | Add Mrs & Msr (Nzcv) Inst., with Tests. (#819) | LDj3SNuD |
| 2019-08-08 | Add a new JIT compiler for CPU code (#693) | gdkchan |
 |
index : Ryujinx | |
| A backup of the Ryujinx master git branch. |
| aboutsummaryrefslogtreecommitdiff |