| Age | Commit message (Expand) | Author |
|---|---|---|
| 2023-04-27 | Move solution and projects to src | TSR Berry |
| 2022-09-14 | A32/T32/A64: Implement Hint instructions (CSDB, SEV, SEVL, WFE, WFI, YIELD) (... | merry |
| 2022-03-19 | InstEmitMemoryEx: Barrier after write on ordered store (#3193) | merry |
| 2022-01-21 | Add host CPU memory barriers for DMB/DSB and ordered load/store (#3015) | gdkchan |
| 2021-08-17 | Reduce JIT GC allocations (#2515) | FICTURE7 |
| 2021-01-26 | Implement PRFM (register variant) as NOP (#1956) | mageven |
| 2020-07-30 | Implement inline memory load/store exclusive and ordered (#1413) | gdkchan |
| 2020-06-16 | Add Profiled Persistent Translation Cache. (#769) | LDj3SNuD |
| 2020-02-24 | Add most of the A32 instruction set to ARMeilleure (#897) | riperiperi |
| 2019-08-08 | Add a new JIT compiler for CPU code (#693) | gdkchan |
 |
index : Ryujinx | |
| A backup of the Ryujinx master git branch. |
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