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2022-08-25Implement some 32-bit Thumb instructions (#3614)gdkchan
* Implement some 32-bit Thumb instructions * Optimize OpCode32MemMult using PopCount
2022-08-18Removed unused usings. (#3593)Nicholas Rodine
* Removed unused usings. * Added back using, now that it's used. * Removed extra whitespace.
2022-08-05Implement Arm32 Sha256 and MRS Rd, CPSR instructions (#3544)gdkchan
* Implement Arm32 Sha256 and MRS Rd, CPSR instructions * Add tests using Arm64 outputs
2022-04-21T32: Implement load/store single (immediate) (#3186)merry
* T32: Implement load/store single (immediate) * tests * tidy formatting * address comments
2022-03-06T32: Implement Data Processing (Modified Immediate) instructions (#3178)merry
* T32: Implement Data Processing (Modified Immediate) instructions * Update tests * switch -> lookup table
2022-03-05Decoders: Fix instruction lengths for 16-bit B instructions (#3177)merry
2022-03-04Decoder: Exit on trapping instructions, and resume execution at trapping ↵merry
instruction (#3153) * Decoder: Exit on trapping instructions, and resume execution at trapping instruction * Resume at trapping address * remove mustExit
2022-03-04T32: Implement B, B.cond, BL, BLX (#3155)merry
* Decoders: Make IsThumb a function of OpCode32 * OpCode32: Fix GetPc * T32: Implement B, B.cond, BL, BLX * rm usings
2022-02-22T32: Implement ALU (shifted register) instructions (#3135)merry
* T32: Implement ADC, ADD, AND, BIC, CMN, CMP, EOR, MOV, MVN, ORN, ORR, RSB, SBC, SUB, TEQ, TST (shifted register) * OpCodeTable: Sort T32 list * Tests: Rename RandomTestCase to PrecomputedThumbTestCase * T32: Tests for AluRsImm instructions * fix nit * fix nit 2
2022-02-22ARMeilleure: Implement single stepping (#3133)merry
* Decoder: Implement SingleInstruction decoder mode * Translator: Implement Step * DecoderMode: Rename Normal to MultipleBlocks
2022-02-18Decoders: Add IOpCode32HasSetFlags (#3136)merry
2022-02-17ARMeilleure: Thumb support (All T16 instructions) (#3105)merry
* Decoders: Add InITBlock argument * OpCodeTable: Minor cleanup * OpCodeTable: Remove existing thumb instruction implementations * OpCodeTable: Prepare for thumb instructions * OpCodeTables: Improve thumb fast lookup * Tests: Prepare for thumb tests * T16: Implement BX * T16: Implement LSL/LSR/ASR (imm) * T16: Implement ADDS, SUBS (reg) * T16: Implement ADDS, SUBS (3-bit immediate) * T16: Implement MOVS, CMP, ADDS, SUBS (8-bit immediate) * T16: Implement ANDS, EORS, LSLS, LSRS, ASRS, ADCS, SBCS, RORS, TST, NEGS, CMP, CMN, ORRS, MULS, BICS, MVNS (low registers) * T16: Implement ADD, CMP, MOV (high reg) * T16: Implement BLX (reg) * T16: Implement LDR (literal) * T16: Implement {LDR,STR}{,H,B,SB,SH} (register) * T16: Implement {LDR,STR}{,B,H} (immediate) * T16: Implement LDR/STR (SP) * T16: Implement ADR * T16: Implement Add to SP (immediate) * T16: Implement ADD/SUB (SP) * T16: Implement SXTH, SXTB, UXTH, UTXB * T16: Implement CBZ, CBNZ * T16: Implement PUSH, POP * T16: Implement REV, REV16, REVSH * T16: Implement NOP * T16: Implement LDM, STM * T16: Implement SVC * T16: Implement B (conditional) * T16: Implement B (unconditional) * T16: Implement IT * fixup! T16: Implement ADD/SUB (SP) * fixup! T16: Implement Add to SP (immediate) * fixup! T16: Implement IT * CpuTestThumb: Add randomized tests * Remove inITBlock argument * Address nits * Use index to handle IfThenBlockState * Reduce line noise * fixup * nit
2022-02-08ARMeilleure: A32: Implement SHSUB8 and UHSUB8 (#3089)merry
* ARMeilleure: A32: Implement UHSUB8 * ARMeilleure: A32: Implement SHSUB8
2022-02-06ARMeilleure: A32: Implement SHADD8 (#3086)merry
2022-02-06ARMeilleure: OpCodeTable: Add CMN (RsReg) (#3087)merry
2022-01-19Implement FCVTNS (Scalar GP) (#2953)sharmander
* Implement FCVTNS (Scalar GP) * Update Ptc Version
2022-01-04CPU - Implement FCVTMS (Vector) (#2937)sharmander
* Add FCVTMS_V Implementation to Armeilleure * Fix opcode designation * Add tests * Amend Ptc version * Fix OpCode / Tests * Create Math.Floor helper method + Update implementation * Address gdk comments * Re-address gdk comments * Update ARMeilleure/Decoders/OpCodeTable.cs Co-authored-by: gdkchan <gab.dark.100@gmail.com> * Update Tests to use 2S (4S) and 2D Co-authored-by: gdkchan <gab.dark.100@gmail.com>
2021-12-19Implement CSDB instruction (#2927)gdkchan
2021-12-08Implement UHADD8 instruction (#2908)Piyachet Kanda
* Implement UHADD8 instruction along with a test unit * Update PTC revision number
2021-08-27Implement MSR instruction for A32 (#2585)Mary
* Implement MSR instruction Fix #1342. Now Pocket Rumble is playable. * Address gdkchan's comments * Address gdkchan's comments * Address gdkchan's comment
2021-06-23Implement VORN (register) Arm32 instruction (#2396)gdkchan
2021-04-18Add inlined on translation call counting (#2190)FICTURE7
* Add EntryTable<TEntry> * Add on translation call counting * Add Counter * Add PPTC support * Make Counter a generic & use a 32-bit counter instead * Return false on overflow * Set PPTC version * Print more information about the rejit queue * Make Counter<T> disposable * Remove Block.TailCall since it is not used anymore * Apply suggestions from code review Address gdkchan's feedback Co-authored-by: gdkchan <gab.dark.100@gmail.com> * Fix more stale docs * Remove rejit requests queue logging * Make Counter<T> finalizable Most certainly quite an odd use case. * Make EntryTable<T>.TryAllocate set entry to default * Re-trigger CI * Dispose Counters before they hit the finalizer queue * Re-trigger CI Just for good measure... * Make EntryTable<T> expandable * EntryTable is now expandable instead of being a fixed slab. * Remove EntryTable<T>.TryAllocate * Remove Counter<T>.TryCreate Address LDj3SNuD's feedback * Apply suggestions from code review Address LDj3SNuD's feedback Co-authored-by: LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com> * Remove useless return * POH approach, but the sequel * Revert "POH approach, but the sequel" This reverts commit 5f5abaa24735726ff2db367dc74f98055d4f4cba. The sequel got shelved * Add extra documentation Co-authored-by: gdkchan <gab.dark.100@gmail.com> Co-authored-by: LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com>
2021-03-25Add Sqdmulh_Ve & Sqrdmulh_Ve Inst.s with Tests. (#2139)LDj3SNuD
2021-02-22Implement VCNT instruction (#1963)mageven
* Implement VCNT based on AArch64 CNT Add tests * Update PTC version * Address LDj's comments * Explicit size in encoding * Tighter tests * Replace SoftFallback with IR helper Co-authored-by: LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com> * Reduce one BitwiseAnd from IR fallback Based on popcount64b from https://en.wikipedia.org/wiki/Hamming_weight#Efficient_implementation * Rename parameter and add assert Co-authored-by: LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com> Co-authored-by: LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com>
2021-01-26Implement PRFM (register variant) as NOP (#1956)mageven
* Implement PRFM (register variant) as NOP Fix typo pfrm -> prfm Add comments to distinguish variants * Increment PTC version
2021-01-20CPU (A64): Add Fmaxnmp & Fminnmp Scalar Inst.s, Fast & Slow Paths; with ↵LDj3SNuD
Tests. (#1894)
2021-01-04CPU (A64): Add Pmull_V Inst. with Clmul fast path for the "1/2D -> 1Q" ↵LDj3SNuD
variant & Sse fast path and slow path for both the "8/16B -> 8H" and "1/2D -> 1Q" variants; with Test. (#1817) * Add Pmull_V Sse fast path only, both "8/16B -> 8H" and "1/2D -> 1Q" variants; with Test. * Add Clmul fast path for the 128 bits variant. * Small optimisation (save 60 instructions) for the Sse fast path about the 128 bits variant. * Add slow path, both variants. Fix V128 Shl/Shr when shift = 0. * A32: Add Vmull_I P64 variant (slow path); not tested. * A32: Add Vmull_I_P8_P64 Test and fix P64 variant.
2020-12-17Fix Vnmls_S fast path (F64: losing input d value). Fix Vnmla_S & Vnmls_S ↵LDj3SNuD
slow paths (using fused inst.s). Fix Vfma_V slow path not using StandardFPSCRValue(). (#1775) * Fix Vnmls_S fast path (F64: losing input d value). Fix Vnmla_S & Vnmls_S slow paths (using fused inst.s). Add Vfma_S & Vfms_S Fma fast paths. Add Vfnma_S inst. with Fma/Sse fast paths and slow path. Add Vfnms_S Sse fast path. Add Tests for affected inst.s. Nits. * InternalVersion = 1775 * Nits. * Fix Vfma_V slow path not using StandardFPSCRValue(). * Nit: Fix Vfma_V order. * Add Vfms_V Sse fast path and slow path. * Add Vfma_V and Vfms_V Test.
2020-12-17PPTC Follow-up. (#1712)LDj3SNuD
* Added support for offline invalidation, via PPTC, of low cq translations replaced by high cq translations; both on a single run and between runs. Added invalidation of .cache files in the event of reuse on a different user operating system. Added .info and .cache files invalidation in case of a failed stream decompression. Nits. * InternalVersion = 1712; * Nits. * Address comment. * Get rid of BinaryFormatter. Nits. * Move Ptc.LoadTranslations(). Nits. * Nits. * Fixed corner cases (in case backup copies have to be used). Added save logs. * Not core fixes. * Complement to the previous commit. Added load logs. Removed BinaryFormatter leftovers. * Add LoadTranslations log. * Nits. * Removed the search and management of LowCq overlapping functions. * Final increment of .info and .cache flags. * Nit. * GetIndirectFunctionAddress(): Validate that writing actually takes place in dynamic table memory range (and not elsewhere). * Fix Ptc.UpdateInfo() due to rebase. * Nit for retrigger Checks. * Nit for retrigger Checks.
2020-12-16CPU: Implement VRINTX.F32 | VRINTX.F64 (#1776)sharmander
* Start implementation * Draft * Updated opcode. Needs verification. * Clean up code. * Update implementation and tests. * Update implemenation + tests * Get RM from FPSCR + Do not use emit/addintrinsic * Remove "fast" path, as recommended by gdk. * Variable DELETED. * Update ARMeilleure/Decoders/OpCodeTable.cs Co-authored-by: LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com> * Update ARMeilleure/Instructions/InstEmitSimdCvt32.cs Co-authored-by: LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com> * Update ARMeilleure/Instructions/InstEmitSimdCvt32.cs Co-authored-by: LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com> * Update ARMeilleure/Instructions/InstEmitSimdCvt32.cs Co-authored-by: LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com> * Move method * stringing things together :) Co-authored-by: LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com>
2020-12-15CPU: Implement VFMA (Vector) (#1762)sharmander
* Implement VFMA.F64 * Simplify switch * Simplify FMA Instructions into their own IntrinsicType. * Remove whitespace * Fix indentation * Change tests for Vfnms -- disable inf / nan * Move args up, not description ;) * Implementation Complete. All Tests Pass (Slow / Fast Path) * Move location of function in assembler + test updates. * Shift params upwards * Remove unused function * Update PTC version. * Add comments / re-oreder opcode table. * Remove whitespace * Fix nit * Fix nit. * Fix whitespace * Wrong opcode was used by a bad merge. * Addressed rip's comments.
2020-12-07CPU: Implement VFNMA.F32 | F.64 (#1783)sharmander
* Implement VFNMA.F<32/64> * Update PTC Version * Update Implementation & Renames & Correct Order * Fix alignment * Update implementation to not trigger assert * Actually use the intrinsic that makes sense :)
2020-12-03CPU: Implement VFNMS.F32/64 (#1758)sharmander
* Add necessary methods / op-code * Enable Support for FMA Instruction Set * Add Intrinsics / Assembly Opcodes for VFMSUB231XX. * Add X86 Instructions for VFMSUB231XX * Implement VFNMS * Implement VFNMS Tests * Add special cases for FMA instructions. * Update PPTC Version * Remove unused Op * Move Check into Assert / Cleanup * Rename and cleanup * Whitespace * Whitespace / Rename * Re-sort * Address final requests * Implement VFMA.F64 * Simplify switch * Simplify FMA Instructions into their own IntrinsicType. * Remove whitespace * Fix indentation * Change tests for Vfnms -- disable inf / nan * Move args up, not description ;) * Undo vfma * Completely remove vfms code., * Fix order of instruction in assembler
2020-10-21Get rid of Reflection.Emit dependency on CPU and Shader projects (#1626)gdkchan
* Get rid of Reflection.Emit dependency on CPU and Shader projects * Remove useless private sets * Missed those due to the alignment
2020-10-13Add Umaal & Vabd_I, Vabdl_I, Vaddl_I, Vhadd, Vqshrn, Vshll inst.s (slow ↵LDj3SNuD
paths). (#1577) * Add Umaal & Vabd_I, Vabdl_I, Vaddl_I, Vhadd, Vqshrn, Vshll inst.s (slow paths). No test provided (i.e. draft). * Ptc InternalVersion = 1577
2020-09-01SIMD&FP load/store with scale > 4 should be undefined (#1522)gdkchan
* SIMD&FP load/store with scale > 4 should be undefined * Catch more invalid encodings for FP&SIMD LDR/STR (reg variant) * Set PTC version to PR number
2020-08-31CPU (A64): Add Scvtf_S_Fixed & Ucvtf_S_Fixed with Tests. (#1492)LDj3SNuD
2020-08-13Fix Vcvt_FI & Vcvt_RM; Add Vfma_S & Vfms_S. Add Tests. (#1471)LDj3SNuD
* Fix Vcvt_FI & Vcvt_RM; Add Vfma_S & Vfms_S. Add Tests. * Address PR feedback & Nit.
2020-07-19Implements some 32-bit instructions (VBIC, VTST, VSRA) (#1192)Valentin PONS
* Added some 32 bits instructions: * VBIC * VTST * VSRA * Incremented the PTC * Add tests and fix implementation * Fixed VBIC immediate opcode mapping * Hey hey! * Nit. Co-authored-by: gdkchan <gab.dark.100@gmail.com> Co-authored-by: LDj3SNuD <dvitiello@gmail.com> Co-authored-by: LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com>
2020-07-17CPU: A32: Fix Vabs_V & Vneg_V (S8, S16, S32 & F32); add Tests. (#1394)LDj3SNuD
* Fix Vabs_V & Vneg_V (S8, S16, S32 & F32); add Tests. * Update Ptc.cs
2020-07-17CPU: A32: Add Vadd & Vsub Wide (S/U_8/16/32) Inst.s with Test. (#1390)LDj3SNuD
2020-07-15Fix Decode exception condition (#1377)Ficture Seven
2020-07-13Add Fmax/minv_V & S/Ushl_S Inst.s with Tests. Fix Maxps/d & Minps/d d… (#1335)LDj3SNuD
* Add Fmax/minv_V & S/Ushl_S Inst.s with Tests. Fix Maxps/d & Minps/d double zero sign handling. Allows better handling of NaNs. * Optimized EmitSse2VectorIsNaNOpF() for multiple uses per opF.
2020-07-13Add SSE4.2 Path for CRC32, add A32 variant, add tests for non-castagnoli ↵riperiperi
variants. (#1328) * Add CRC32 A32 instructions. * Fix CRC32 instructions. * Add CRC intrinsic and fast path. Loop is currently unrolled, will look into adding temp vars after tests are added. * Begin work on Crc tests * Fix SSE4.2 path for CRC32C, finialize tests. * Remove unused IR path. * Fix spacing between prefix checks. * This should be Src. * PTC Version * OpCodeTable Order * Integer check improvement. Value and Crc can be either 32 or 64 size. * This wasn't necessary... * If size is 3, value type must be I64. * Fix same src+dest handling for non crc intrinsics. * Pre-fix (ha) issue with vex encodings
2020-06-24Fix VMVN (immediate), Add VPMIN, VPMAX, VMVN (register) (#1303)riperiperi
* Add Vmvn (register), tests for both Vmvn variants. * Add Vpmin, Vpmax, improve Non-FastFp accuracy for Vpadd * Rebase on top of PTC. * Add Nopcode * Increment PTC version. * Fix nits.
2020-06-18Generalize tail continues (#1298)Ficture Seven
* Generalize tail continues * Fix DecodeBasicBlock `Next` and `Branch` would be null, which is not the state expected by the branch instructions. They end up branching or falling into a block which is never populated by the `Translator`. This causes an assert to be fired when building the CFG. * Clean up Decode overloads * Do not synchronize when branching into exit block If we're branching into an exit block, that exit block will tail continue into another translation which already has a synchronization. * Remove A32 predicate tail continue If `block` is not an exit block then the `block.Next` must exist (as per the last instruction of `block`). * Throw if decoded 0 blocks Address gdkchan's feedback * Rebuild block list instead of setting to null Address gdkchan's feedback
2020-06-16Add Profiled Persistent Translation Cache. (#769)LDj3SNuD
* Delete DelegateTypes.cs * Delete DelegateCache.cs * Add files via upload * Update Horizon.cs * Update Program.cs * Update MainWindow.cs * Update Aot.cs * Update RelocEntry.cs * Update Translator.cs * Update MemoryManager.cs * Update InstEmitMemoryHelper.cs * Update Delegates.cs * Nit. * Nit. * Nit. * 10 fewer MSIL bytes for us * Add comment. Nits. * Update Translator.cs * Update Aot.cs * Nits. * Opt.. * Opt.. * Opt.. * Opt.. * Allow to change compression level. * Update MemoryManager.cs * Update Translator.cs * Manage corner cases during the save phase. Nits. * Update Aot.cs * Translator response tweak for Aot disabled. Nit. * Nit. * Nits. * Create DelegateHelpers.cs * Update Delegates.cs * Nit. * Nit. * Nits. * Fix due to #784. * Fixes due to #757 & #841. * Fix due to #846. * Fix due to #847. * Use MethodInfo for managed method calls. Use IR methods instead of managed methods about Max/Min (S/U). Follow-ups & Nits. * Add missing exception messages. Reintroduce slow path for Fmov_Vi. Implement slow path for Fmov_Si. * Switch to the new folder structure. Nits. * Impl. index-based relocation information. Impl. cache file version field. * Nit. * Address gdkchan comments. Mainly: - fixed cache file corruption issue on exit; - exposed a way to disable AOT on the GUI. * Address AcK77 comment. * Address Thealexbarney, jduncanator & emmauss comments. Header magic, CpuId (FI) & Aot -> Ptc. * Adaptation to the new application reloading system. Improvements to the call system of managed methods. Follow-ups. Nits. * Get the same boot times as on master when PTC is disabled. * Profiled Aot. * A32 support (#897). * #975 support (1 of 2). * #975 support (2 of 2). * Rebase fix & nits. * Some fixes and nits (still one bug left). * One fix & nits. * Tests fix (by gdk) & nits. * Support translations not only in high quality and rejit. Nits. * Added possibility to skip translations and continue execution, using `ESC` key. * Update SettingsWindow.cs * Update GLRenderer.cs * Update Ptc.cs * Disabled Profiled PTC by default as requested in the past by gdk. * Fix rejit bug. Increased number of parallel translations. Add stack unwinding stuffs support (1 of 2). Nits. * Add stack unwinding stuffs support (2 of 2). Tuned number of parallel translations. * Restored the ability to assemble jumps with 8-bit offset when Profiled PTC is disabled or during profiling. Modifications due to rebase. Nits. * Limited profiling of the functions to be translated to the addresses belonging to the range of static objects only. * Nits. * Nits. * Update Delegates.cs * Nit. * Update InstEmitSimdArithmetic.cs * Address riperiperi comments. * Fixed the issue of unjustifiably longer boot times at the second boot than at the first boot, measured at the same time or reference point and with the same number of translated functions. * Implemented a simple redundant load/save mechanism. Halved the value of Decoder.MaxInstsPerFunction more appropriate for the current performance of the Translator. Replaced by Logger.PrintError to Logger.PrintDebug in TexturePool.cs about the supposed invalid texture format to avoid the spawn of the log. Nits. * Nit. Improved Logger.PrintError in TexturePool.cs to avoid log spawn. Added missing code for FZ handling (in output) for fp max/min instructions (slow paths). * Add configuration migration for PTC Co-authored-by: Thog <me@thog.eu>
2020-06-14VABS takes one input register, not two. (#1300)riperiperi
2020-05-27Add FMaxNmV & FMinNmV Inst.s with Test. (#1279)LDj3SNuD
Successful unit testing on Windows (debug and release mode).
2020-05-04Implement a new physical memory manager and replace DeviceMemory (#856)gdkchan
* Implement a new physical memory manager and replace DeviceMemory * Proper generic constraints * Fix debug build * Add memory tests * New CPU memory manager and general code cleanup * Remove host memory management from CPU project, use Ryujinx.Memory instead * Fix tests * Document exceptions on MemoryBlock * Fix leak on unix memory allocation * Proper disposal of some objects on tests * Fix JitCache not being set as initialized * GetRef without checks for 8-bits and 16-bits CAS * Add MemoryBlock destructor * Throw in separate method to improve codegen * Address PR feedback * QueryModified improvements * Fix memory write tracking not marking all pages as modified in some cases * Simplify MarkRegionAsModified * Remove XML doc for ghost param * Add back optimization to avoid useless buffer updates * Add Ryujinx.Cpu project, move MemoryManager there and remove MemoryBlockWrapper * Some nits * Do not perform address translation when size is 0 * Address PR feedback and format NativeInterface class * Remove ghost parameter description * Update Ryujinx.Cpu to .NET Core 3.1 * Address PR feedback * Fix build * Return a well defined value for GetPhysicalAddress with invalid VA, and do not return unmapped ranges as modified * Typo
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