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AgeCommit message (Expand)Author
2022-08-25Implement some 32-bit Thumb instructions (#3614)gdkchan
2022-08-18Removed unused usings. (#3593)Nicholas Rodine
2022-08-05Implement Arm32 Sha256 and MRS Rd, CPSR instructions (#3544)gdkchan
2022-04-21T32: Implement load/store single (immediate) (#3186)merry
2022-03-06T32: Implement Data Processing (Modified Immediate) instructions (#3178)merry
2022-03-05Decoders: Fix instruction lengths for 16-bit B instructions (#3177)merry
2022-03-04Decoder: Exit on trapping instructions, and resume execution at trapping inst...merry
2022-03-04T32: Implement B, B.cond, BL, BLX (#3155)merry
2022-02-22T32: Implement ALU (shifted register) instructions (#3135)merry
2022-02-22ARMeilleure: Implement single stepping (#3133)merry
2022-02-18Decoders: Add IOpCode32HasSetFlags (#3136)merry
2022-02-17ARMeilleure: Thumb support (All T16 instructions) (#3105)merry
2022-02-08ARMeilleure: A32: Implement SHSUB8 and UHSUB8 (#3089)merry
2022-02-06ARMeilleure: A32: Implement SHADD8 (#3086)merry
2022-02-06ARMeilleure: OpCodeTable: Add CMN (RsReg) (#3087)merry
2022-01-19Implement FCVTNS (Scalar GP) (#2953)sharmander
2022-01-04CPU - Implement FCVTMS (Vector) (#2937)sharmander
2021-12-19Implement CSDB instruction (#2927)gdkchan
2021-12-08Implement UHADD8 instruction (#2908)Piyachet Kanda
2021-08-27Implement MSR instruction for A32 (#2585)Mary
2021-06-23Implement VORN (register) Arm32 instruction (#2396)gdkchan
2021-04-18Add inlined on translation call counting (#2190)FICTURE7
2021-03-25Add Sqdmulh_Ve & Sqrdmulh_Ve Inst.s with Tests. (#2139)LDj3SNuD
2021-02-22Implement VCNT instruction (#1963)mageven
2021-01-26Implement PRFM (register variant) as NOP (#1956)mageven
2021-01-20CPU (A64): Add Fmaxnmp & Fminnmp Scalar Inst.s, Fast & Slow Paths; with Tests...LDj3SNuD
2021-01-04CPU (A64): Add Pmull_V Inst. with Clmul fast path for the "1/2D -> 1Q" varian...LDj3SNuD
2020-12-17Fix Vnmls_S fast path (F64: losing input d value). Fix Vnmla_S & Vnmls_S slow...LDj3SNuD
2020-12-17PPTC Follow-up. (#1712)LDj3SNuD
2020-12-16CPU: Implement VRINTX.F32 | VRINTX.F64 (#1776)sharmander
2020-12-15CPU: Implement VFMA (Vector) (#1762)sharmander
2020-12-07CPU: Implement VFNMA.F32 | F.64 (#1783)sharmander
2020-12-03CPU: Implement VFNMS.F32/64 (#1758)sharmander
2020-10-21Get rid of Reflection.Emit dependency on CPU and Shader projects (#1626)gdkchan
2020-10-13Add Umaal & Vabd_I, Vabdl_I, Vaddl_I, Vhadd, Vqshrn, Vshll inst.s (slow paths...LDj3SNuD
2020-09-01SIMD&FP load/store with scale > 4 should be undefined (#1522)gdkchan
2020-08-31CPU (A64): Add Scvtf_S_Fixed & Ucvtf_S_Fixed with Tests. (#1492)LDj3SNuD
2020-08-13Fix Vcvt_FI & Vcvt_RM; Add Vfma_S & Vfms_S. Add Tests. (#1471)LDj3SNuD
2020-07-19Implements some 32-bit instructions (VBIC, VTST, VSRA) (#1192)Valentin PONS
2020-07-17CPU: A32: Fix Vabs_V & Vneg_V (S8, S16, S32 & F32); add Tests. (#1394)LDj3SNuD
2020-07-17CPU: A32: Add Vadd & Vsub Wide (S/U_8/16/32) Inst.s with Test. (#1390)LDj3SNuD
2020-07-15Fix Decode exception condition (#1377)Ficture Seven
2020-07-13Add Fmax/minv_V & S/Ushl_S Inst.s with Tests. Fix Maxps/d & Minps/d d… (#1335)LDj3SNuD
2020-07-13Add SSE4.2 Path for CRC32, add A32 variant, add tests for non-castagnoli vari...riperiperi
2020-06-24Fix VMVN (immediate), Add VPMIN, VPMAX, VMVN (register) (#1303)riperiperi
2020-06-18Generalize tail continues (#1298)Ficture Seven
2020-06-16Add Profiled Persistent Translation Cache. (#769)LDj3SNuD
2020-06-14VABS takes one input register, not two. (#1300)riperiperi
2020-05-27Add FMaxNmV & FMinNmV Inst.s with Test. (#1279)LDj3SNuD
2020-05-04Implement a new physical memory manager and replace DeviceMemory (#856)gdkchan
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