diff options
Diffstat (limited to 'ARMeilleure/Instructions/InstEmitSimdMove32.cs')
| -rw-r--r-- | ARMeilleure/Instructions/InstEmitSimdMove32.cs | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/ARMeilleure/Instructions/InstEmitSimdMove32.cs b/ARMeilleure/Instructions/InstEmitSimdMove32.cs index 52292242..7da180fc 100644 --- a/ARMeilleure/Instructions/InstEmitSimdMove32.cs +++ b/ARMeilleure/Instructions/InstEmitSimdMove32.cs @@ -6,7 +6,7 @@ using System; using static ARMeilleure.Instructions.InstEmitHelper; using static ARMeilleure.Instructions.InstEmitSimdHelper; using static ARMeilleure.Instructions.InstEmitSimdHelper32; -using static ARMeilleure.IntermediateRepresentation.OperandHelper; +using static ARMeilleure.IntermediateRepresentation.Operand.Factory; namespace ARMeilleure.Instructions { @@ -267,7 +267,7 @@ namespace ARMeilleure.Instructions Operand selectedIndex = context.ZeroExtend8(OperandType.I32, context.VectorExtract8(m, index + op.Im)); Operand inRange = context.ICompareLess(selectedIndex, Const(byteLength)); - Operand elemRes = null; // Note: This is I64 for ease of calculation. + Operand elemRes = default; // Note: This is I64 for ease of calculation. // TODO: Branching rather than conditional select. @@ -325,7 +325,7 @@ namespace ARMeilleure.Instructions { EmitVectorShuffleOpSimd32(context, (m, d) => { - Operand mask = null; + Operand mask = default; if (op.Size < 3) { @@ -467,7 +467,7 @@ namespace ARMeilleure.Instructions { if (op.RegisterSize == RegisterSize.Simd128) { - Operand mask = null; + Operand mask = default; if (op.Size < 3) { |