1 files changed, 54 insertions, 15 deletions

diff --git a/ARMeilleure/Instructions/InstEmitSimdLogical32.cs b/ARMeilleure/Instructions/InstEmitSimdLogical32.cs
index e2e9e18e..fef40a17 100644
--- a/ARMeilleure/Instructions/InstEmitSimdLogical32.cs
+++ b/ARMeilleure/Instructions/InstEmitSimdLogical32.cs
@@ -1,4 +1,5 @@
 using ARMeilleure.Decoders;
+using ARMeilleure.IntermediateRepresentation;
 using ARMeilleure.Translation;
 
 using static ARMeilleure.Instructions.InstEmitSimdHelper32;
@@ -9,7 +10,14 @@ namespace ARMeilleure.Instructions
     {
         public static void Vand_I(ArmEmitterContext context)
         {
-            EmitVectorBinaryOpZx32(context, (op1, op2) => context.BitwiseAnd(op1, op2));
+            if (Optimizations.UseSse2)
+            {
+                EmitVectorBinaryOpF32(context, Intrinsic.X86Pand, Intrinsic.X86Pand);
+            }
+            else
+            {
+                EmitVectorBinaryOpZx32(context, (op1, op2) => context.BitwiseAnd(op1, op2));
+            }
         }
 
         public static void Vbif(ArmEmitterContext context)
@@ -24,33 +32,64 @@ namespace ARMeilleure.Instructions
 
         public static void Vbsl(ArmEmitterContext context)
         {
-            EmitVectorTernaryOpZx32(context, (op1, op2, op3) =>
+            if (Optimizations.UseSse2)
             {
-                return context.BitwiseExclusiveOr(
-                    context.BitwiseAnd(op1,
-                    context.BitwiseExclusiveOr(op2, op3)), op3);
-            });
+                EmitVectorTernaryOpSimd32(context, (d, n, m) =>
+                {
+                    Operand res = context.AddIntrinsic(Intrinsic.X86Pxor, n, m);
+                    res = context.AddIntrinsic(Intrinsic.X86Pand, res, d);
+                    return context.AddIntrinsic(Intrinsic.X86Pxor, res, m);
+                });
+            }
+            else
+            {
+                EmitVectorTernaryOpZx32(context, (op1, op2, op3) =>
+                {
+                    return context.BitwiseExclusiveOr(
+                        context.BitwiseAnd(op1,
+                        context.BitwiseExclusiveOr(op2, op3)), op3);
+                });
+            }
         }
 
         public static void Vorr_I(ArmEmitterContext context)
         {
-            EmitVectorBinaryOpZx32(context, (op1, op2) => context.BitwiseOr(op1, op2));
+            if (Optimizations.UseSse2)
+            {
+                EmitVectorBinaryOpF32(context, Intrinsic.X86Por, Intrinsic.X86Por);
+            }
+            else
+            {
+                EmitVectorBinaryOpZx32(context, (op1, op2) => context.BitwiseOr(op1, op2));
+            }
         }
 
         private static void EmitBifBit(ArmEmitterContext context, bool notRm)
         {
             OpCode32SimdReg op = (OpCode32SimdReg)context.CurrOp;
 
-            EmitVectorTernaryOpZx32(context, (d, n, m) =>
+            if (Optimizations.UseSse2)
+            {
+                EmitVectorTernaryOpSimd32(context, (d, n, m) =>
+                {
+                    Operand res = context.AddIntrinsic(Intrinsic.X86Pxor, n, d);
+                    res = context.AddIntrinsic((notRm) ? Intrinsic.X86Pandn : Intrinsic.X86Pand, m, res);
+                    return context.AddIntrinsic(Intrinsic.X86Pxor, d, res);
+                });
+            }
+            else
             {
-                if (notRm)
+                EmitVectorTernaryOpZx32(context, (d, n, m) =>
                 {
-                    m = context.BitwiseNot(m);
-                }
-                return context.BitwiseExclusiveOr(
-                    context.BitwiseAnd(m,
-                    context.BitwiseExclusiveOr(d, n)), d);
-            });
+                    if (notRm)
+                    {
+                        m = context.BitwiseNot(m);
+                    }
+                    return context.BitwiseExclusiveOr(
+                        context.BitwiseAnd(m,
+                        context.BitwiseExclusiveOr(d, n)), d);
+                });
+            }
         }
     }
 }