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| author | gdkchan <gab.dark.100@gmail.com> | 2024-09-12 18:22:30 -0300 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-09-12 18:22:30 -0300 |
| commit | 2f36a6665cc5ad0aeec49d6cce9425830d1cee41 (patch) | |
| tree | 80377c9c0a60bd903a5c6bd9cb9b212b140cc8f4 /src/Ryujinx.Tests/Cpu/CpuTestSimd32.cs | |
| parent | ca59c3f4998e2d1beb3b0d0214611e3332238557 (diff) | |
Implement Arm32 VSHLL and QADD16 instructions (#7301)
Diffstat (limited to 'src/Ryujinx.Tests/Cpu/CpuTestSimd32.cs')
| -rw-r--r-- | src/Ryujinx.Tests/Cpu/CpuTestSimd32.cs | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/src/Ryujinx.Tests/Cpu/CpuTestSimd32.cs b/src/Ryujinx.Tests/Cpu/CpuTestSimd32.cs index f843fd56..08202c9e 100644 --- a/src/Ryujinx.Tests/Cpu/CpuTestSimd32.cs +++ b/src/Ryujinx.Tests/Cpu/CpuTestSimd32.cs @@ -328,6 +328,29 @@ namespace Ryujinx.Tests.Cpu CompareAgainstUnicorn(); } + [Test, Pairwise, Description("VSHLL.<size> {<Vd>}, <Vm>, #<imm>")] + public void Vshll([Values(0u, 2u)] uint rd, + [Values(1u, 0u)] uint rm, + [Values(0u, 1u, 2u)] uint size, + [Random(RndCnt)] ulong z, + [Random(RndCnt)] ulong a, + [Random(RndCnt)] ulong b) + { + uint opcode = 0xf3b20300u; // VSHLL.I8 Q0, D0, #8 + + opcode |= ((rm & 0xf) << 0) | ((rm & 0x10) << 1); + opcode |= ((rd & 0xf) << 12) | ((rd & 0x10) << 18); + opcode |= size << 18; + + V128 v0 = MakeVectorE0E1(z, z); + V128 v1 = MakeVectorE0E1(a, z); + V128 v2 = MakeVectorE0E1(b, z); + + SingleOpcode(opcode, v0: v0, v1: v1, v2: v2); + + CompareAgainstUnicorn(); + } + [Test, Pairwise, Description("VSWP D0, D0")] public void Vswp([Values(0u, 1u)] uint rd, [Values(0u, 1u)] uint rm, |