diff options
| author | gdkchan <gab.dark.100@gmail.com> | 2023-09-14 14:58:11 -0300 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2023-09-14 19:58:11 +0200 |
| commit | 7ccff037e87f82f3461f3e1422235e29800eaa2f (patch) | |
| tree | 280ca9072284926fc24e7c5316b1c92b108888e5 /src/Ryujinx.Graphics.Vulkan/PipelineBase.cs | |
| parent | a745913329c4f4a135b276212f172578f08bc718 (diff) | |
Fix some Vulkan validation errors (mostly related to barriers) (#5603)
* Replace image barriers inside render pass with more generic memory barrier
* Remove forceStorage since it was creating images with storage bit for formats that are not StorageImage compatible
* Add missing flags on subpass dependency
* Don't call vkCmdSetScissor with a scissor count of 0
* One semaphore per swapchain image
* Remove compute stage from read to write barriers
* Try to improve Pipeline.Barrier nonsense
* Set PipelineStateFlags based on supported stages
Diffstat (limited to 'src/Ryujinx.Graphics.Vulkan/PipelineBase.cs')
| -rw-r--r-- | src/Ryujinx.Graphics.Vulkan/PipelineBase.cs | 16 |
1 files changed, 14 insertions, 2 deletions
diff --git a/src/Ryujinx.Graphics.Vulkan/PipelineBase.cs b/src/Ryujinx.Graphics.Vulkan/PipelineBase.cs index 54b67f35..156b3db1 100644 --- a/src/Ryujinx.Graphics.Vulkan/PipelineBase.cs +++ b/src/Ryujinx.Graphics.Vulkan/PipelineBase.cs @@ -149,10 +149,22 @@ namespace Ryujinx.Graphics.Vulkan DstAccessMask = AccessFlags.MemoryReadBit | AccessFlags.MemoryWriteBit, }; + PipelineStageFlags pipelineStageFlags = PipelineStageFlags.VertexShaderBit | PipelineStageFlags.FragmentShaderBit; + + if (Gd.Capabilities.SupportsGeometryShader) + { + pipelineStageFlags |= PipelineStageFlags.GeometryShaderBit; + } + + if (Gd.Capabilities.SupportsTessellationShader) + { + pipelineStageFlags |= PipelineStageFlags.TessellationControlShaderBit | PipelineStageFlags.TessellationEvaluationShaderBit; + } + Gd.Api.CmdPipelineBarrier( CommandBuffer, - PipelineStageFlags.FragmentShaderBit, - PipelineStageFlags.FragmentShaderBit, + pipelineStageFlags, + pipelineStageFlags, 0, 1, memoryBarrier, |