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authormakigumo <makigumo@users.noreply.github.com>2023-05-22 22:32:15 +0200
committerGitHub <noreply@github.com>2023-05-22 17:32:15 -0300
commit6cb6b15612a20717c0e98045914b535f582cdc33 (patch)
treefd6e03f2db0e09d8297b69ffb25cdae1857ae3cd /src/Ryujinx.Graphics.Shader/Instructions/InstEmitPredicate.cs
parent2725e40838070f34e2d10938f3a4223ee0629186 (diff)
Implement p2rc, p2ri, p2rr and r2p.cc shaders (#5031)
* implement P2rC, P2rI, P2rR shaders * implement R2p.CC shader * bump CodeGenVersion * address feedback
Diffstat (limited to 'src/Ryujinx.Graphics.Shader/Instructions/InstEmitPredicate.cs')
-rw-r--r--src/Ryujinx.Graphics.Shader/Instructions/InstEmitPredicate.cs64
1 files changed, 63 insertions, 1 deletions
diff --git a/src/Ryujinx.Graphics.Shader/Instructions/InstEmitPredicate.cs b/src/Ryujinx.Graphics.Shader/Instructions/InstEmitPredicate.cs
index d605661f..79919624 100644
--- a/src/Ryujinx.Graphics.Shader/Instructions/InstEmitPredicate.cs
+++ b/src/Ryujinx.Graphics.Shader/Instructions/InstEmitPredicate.cs
@@ -1,7 +1,6 @@
using Ryujinx.Graphics.Shader.Decoders;
using Ryujinx.Graphics.Shader.IntermediateRepresentation;
using Ryujinx.Graphics.Shader.Translation;
-
using static Ryujinx.Graphics.Shader.Instructions.InstEmitAluHelper;
using static Ryujinx.Graphics.Shader.Instructions.InstEmitHelper;
using static Ryujinx.Graphics.Shader.IntermediateRepresentation.OperandHelper;
@@ -50,5 +49,68 @@ namespace Ryujinx.Graphics.Shader.Instructions
context.Copy(Register(op.DestPred, RegisterType.Predicate), p0Res);
context.Copy(Register(op.DestPredInv, RegisterType.Predicate), p1Res);
}
+
+ public static void P2rC(EmitterContext context)
+ {
+ InstP2rC op = context.GetOp<InstP2rC>();
+
+ Operand srcA = GetSrcReg(context, op.SrcA);
+ Operand dest = GetSrcReg(context, op.Dest);
+ Operand mask = GetSrcCbuf(context, op.CbufSlot, op.CbufOffset);
+
+ EmitP2r(context, srcA, dest, mask, op.ByteSel, op.Ccpr);
+ }
+
+ public static void P2rI(EmitterContext context)
+ {
+ InstP2rI op = context.GetOp<InstP2rI>();
+
+ Operand srcA = GetSrcReg(context, op.SrcA);
+ Operand dest = GetSrcReg(context, op.Dest);
+ Operand mask = GetSrcImm(context, op.Imm20);
+
+ EmitP2r(context, srcA, dest, mask, op.ByteSel, op.Ccpr);
+ }
+
+ public static void P2rR(EmitterContext context)
+ {
+ InstP2rR op = context.GetOp<InstP2rR>();
+
+ Operand srcA = GetSrcReg(context, op.SrcA);
+ Operand dest = GetSrcReg(context, op.Dest);
+ Operand mask = GetSrcReg(context, op.SrcB);
+
+ EmitP2r(context, srcA, dest, mask, op.ByteSel, op.Ccpr);
+ }
+
+ private static void EmitP2r(
+ EmitterContext context,
+ Operand srcA,
+ Operand dest,
+ Operand mask,
+ ByteSel byteSel,
+ bool ccpr)
+ {
+ int count = ccpr ? RegisterConsts.FlagsCount : RegisterConsts.PredsCount;
+ int shift = (int)byteSel * 8;
+ mask = context.BitwiseAnd(mask, Const(0xff));
+
+ Operand insert = Const(0);
+ for (int i = 0; i < count; i++)
+ {
+ Operand condition = ccpr
+ ? Register(i, RegisterType.Flag)
+ : Register(i, RegisterType.Predicate);
+
+ Operand bit = context.ConditionalSelect(condition, Const(1 << (i + shift)), Const(0));
+ insert = context.BitwiseOr(insert, bit);
+ }
+
+ Operand maskShifted = context.ShiftLeft(mask, Const(shift));
+ Operand masked = context.BitwiseAnd(srcA, context.BitwiseNot(maskShifted));
+ Operand res = context.BitwiseOr(masked, context.BitwiseAnd(insert, maskShifted));
+
+ context.Copy(dest, res);
+ }
}
} \ No newline at end of file