diff options
| author | gdkchan <gab.dark.100@gmail.com> | 2024-01-20 11:11:28 -0300 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2024-01-20 11:11:28 -0300 |
| commit | 427b7d06b5ab6d2b06784a9d283eaf836a04c27e (patch) | |
| tree | b69b500432626c89f6a4b7171a948b46c46b3723 /src/Ryujinx.Cpu/LightningJit/Arm64 | |
| parent | 331c07807fd0db5d4452d6ef02962a6d19a56d7f (diff) | |
Implement a new JIT for Arm devices (#6057)
* Implement a new JIT for Arm devices
* Auto-format
* Make a lot of Assembler members read-only
* More read-only
* Fix more warnings
* ObjectDisposedException.ThrowIf
* New JIT cache for platforms that enforce W^X, currently unused
* Remove unused using
* Fix assert
* Pass memory manager type around
* Safe memory manager mode support + other improvements
* Actual safe memory manager mode masking support
* PR feedback
Diffstat (limited to 'src/Ryujinx.Cpu/LightningJit/Arm64')
| -rw-r--r-- | src/Ryujinx.Cpu/LightningJit/Arm64/A64Compiler.cs | 29 | ||||
| -rw-r--r-- | src/Ryujinx.Cpu/LightningJit/Arm64/Block.cs | 138 | ||||
| -rw-r--r-- | src/Ryujinx.Cpu/LightningJit/Arm64/ImmUtils.cs | 20 | ||||
| -rw-r--r-- | src/Ryujinx.Cpu/LightningJit/Arm64/InstFlags.cs | 108 | ||||
| -rw-r--r-- | src/Ryujinx.Cpu/LightningJit/Arm64/InstInfo.cs | 22 | ||||
| -rw-r--r-- | src/Ryujinx.Cpu/LightningJit/Arm64/InstName.cs | 1134 | ||||
| -rw-r--r-- | src/Ryujinx.Cpu/LightningJit/Arm64/MultiBlock.cs | 64 | ||||
| -rw-r--r-- | src/Ryujinx.Cpu/LightningJit/Arm64/RegisterAllocator.cs | 154 | ||||
| -rw-r--r-- | src/Ryujinx.Cpu/LightningJit/Arm64/RegisterUtils.cs | 495 | ||||
| -rw-r--r-- | src/Ryujinx.Cpu/LightningJit/Arm64/Target/Arm64/Compiler.cs | 743 | ||||
| -rw-r--r-- | src/Ryujinx.Cpu/LightningJit/Arm64/Target/Arm64/Decoder.cs | 384 | ||||
| -rw-r--r-- | src/Ryujinx.Cpu/LightningJit/Arm64/Target/Arm64/InstEmitMemory.cs | 593 | ||||
| -rw-r--r-- | src/Ryujinx.Cpu/LightningJit/Arm64/Target/Arm64/InstEmitSystem.cs | 610 | ||||
| -rw-r--r-- | src/Ryujinx.Cpu/LightningJit/Arm64/Target/Arm64/InstTable.cs | 1605 |
14 files changed, 6099 insertions, 0 deletions
diff --git a/src/Ryujinx.Cpu/LightningJit/Arm64/A64Compiler.cs b/src/Ryujinx.Cpu/LightningJit/Arm64/A64Compiler.cs new file mode 100644 index 00000000..b46ae3b0 --- /dev/null +++ b/src/Ryujinx.Cpu/LightningJit/Arm64/A64Compiler.cs @@ -0,0 +1,29 @@ +using ARMeilleure.Common; +using ARMeilleure.Memory; +using Ryujinx.Cpu.LightningJit.Arm64.Target.Arm64; +using System; +using System.Runtime.InteropServices; + +namespace Ryujinx.Cpu.LightningJit.Arm64 +{ + static class A64Compiler + { + public static CompiledFunction Compile( + CpuPreset cpuPreset, + IMemoryManager memoryManager, + ulong address, + AddressTable<ulong> funcTable, + IntPtr dispatchStubPtr, + Architecture targetArch) + { + if (targetArch == Architecture.Arm64) + { + return Compiler.Compile(cpuPreset, memoryManager, address, funcTable, dispatchStubPtr); + } + else + { + throw new PlatformNotSupportedException(); + } + } + } +} diff --git a/src/Ryujinx.Cpu/LightningJit/Arm64/Block.cs b/src/Ryujinx.Cpu/LightningJit/Arm64/Block.cs new file mode 100644 index 00000000..188630a1 --- /dev/null +++ b/src/Ryujinx.Cpu/LightningJit/Arm64/Block.cs @@ -0,0 +1,138 @@ +using Ryujinx.Cpu.LightningJit.Graph; +using System.Collections.Generic; +using System.Diagnostics; + +namespace Ryujinx.Cpu.LightningJit.Arm64 +{ + class Block : IBlock + { + public int Index { get; private set; } + + private readonly List<Block> _predecessors; + private readonly List<Block> _successors; + + public int PredecessorsCount => _predecessors.Count; + public int SuccessorsCount => _successors.Count; + + public readonly ulong Address; + public readonly ulong EndAddress; + public readonly List<InstInfo> Instructions; + public readonly bool EndsWithBranch; + public readonly bool IsTruncated; + public readonly bool IsLoopEnd; + + public Block(ulong address, ulong endAddress, List<InstInfo> instructions, bool endsWithBranch, bool isTruncated, bool isLoopEnd) + { + Debug.Assert((int)((endAddress - address) / 4) == instructions.Count); + + _predecessors = new(); + _successors = new(); + Address = address; + EndAddress = endAddress; + Instructions = instructions; + EndsWithBranch = endsWithBranch; + IsTruncated = isTruncated; + IsLoopEnd = isLoopEnd; + } + + public (Block, Block) SplitAtAddress(ulong address) + { + int splitIndex = (int)((address - Address) / 4); + int splitCount = Instructions.Count - splitIndex; + + // Technically those are valid, but we don't want to create empty blocks. + Debug.Assert(splitIndex != 0); + Debug.Assert(splitCount != 0); + + Block leftBlock = new( + Address, + address, + Instructions.GetRange(0, splitIndex), + false, + false, + false); + + Block rightBlock = new( + address, + EndAddress, + Instructions.GetRange(splitIndex, splitCount), + EndsWithBranch, + IsTruncated, + IsLoopEnd); + + return (leftBlock, rightBlock); + } + + public void Number(int index) + { + Index = index; + } + + public void AddSuccessor(Block block) + { + if (!_successors.Contains(block)) + { + _successors.Add(block); + } + } + + public void AddPredecessor(Block block) + { + if (!_predecessors.Contains(block)) + { + _predecessors.Add(block); + } + } + + public IBlock GetSuccessor(int index) + { + return _successors[index]; + } + + public IBlock GetPredecessor(int index) + { + return _predecessors[index]; + } + + public RegisterUse ComputeUseMasks() + { + if (Instructions.Count == 0) + { + return new(0u, 0u, 0u, 0u, 0u, 0u); + } + + RegisterUse use = Instructions[0].RegisterUse; + + for (int index = 1; index < Instructions.Count; index++) + { + RegisterUse currentUse = Instructions[index].RegisterUse; + + use = new(use.Read | (currentUse.Read & ~use.Write), use.Write | currentUse.Write); + } + + return use; + } + + public bool EndsWithContextLoad() + { + return !IsTruncated && EndsWithContextStoreAndLoad(); + } + + public bool EndsWithContextStore() + { + return EndsWithContextStoreAndLoad(); + } + + private bool EndsWithContextStoreAndLoad() + { + if (Instructions.Count == 0) + { + return false; + } + + InstName lastInstructionName = Instructions[^1].Name; + + return lastInstructionName.IsCall() || lastInstructionName.IsException(); + } + } +} diff --git a/src/Ryujinx.Cpu/LightningJit/Arm64/ImmUtils.cs b/src/Ryujinx.Cpu/LightningJit/Arm64/ImmUtils.cs new file mode 100644 index 00000000..8a12756b --- /dev/null +++ b/src/Ryujinx.Cpu/LightningJit/Arm64/ImmUtils.cs @@ -0,0 +1,20 @@ +namespace Ryujinx.Cpu.LightningJit.Arm64 +{ + static class ImmUtils + { + public static int ExtractSImm14Times4(uint encoding) + { + return ((int)(encoding >> 5) << 18) >> 16; + } + + public static int ExtractSImm19Times4(uint encoding) + { + return ((int)(encoding >> 5) << 13) >> 11; + } + + public static int ExtractSImm26Times4(uint encoding) + { + return (int)(encoding << 6) >> 4; + } + } +} diff --git a/src/Ryujinx.Cpu/LightningJit/Arm64/InstFlags.cs b/src/Ryujinx.Cpu/LightningJit/Arm64/InstFlags.cs new file mode 100644 index 00000000..5a6c3eb0 --- /dev/null +++ b/src/Ryujinx.Cpu/LightningJit/Arm64/InstFlags.cs @@ -0,0 +1,108 @@ +using System; + +namespace Ryujinx.Cpu.LightningJit.Arm64 +{ + [Flags] + enum InstFlags + { + None = 0, + Rd = 1 << 0, + RdSP = Rd | (1 << 1), + ReadRd = 1 << 2, + Rt = 1 << 3, + RtSeq = Rt | (1 << 4), + ReadRt = 1 << 5, + Rt2 = 1 << 6, + Rn = 1 << 7, + RnSeq = Rn | (1 << 8), + RnSP = Rn | (1 << 9), + Rm = 1 << 10, + Rs = 1 << 11, + Ra = 1 << 12, + Nzcv = 1 << 13, + C = 1 << 14, + S = 1 << 15, + Qc = 1 << 16, + FpSimd = 1 << 17, + FpSimdFromGpr = FpSimd | (1 << 18), + FpSimdToGpr = FpSimd | (1 << 19), + FpSimdFromToGpr = FpSimdFromGpr | FpSimdToGpr, + Memory = 1 << 20, + MemWBack = 1 << 21, + + RdFpSimd = Rd | FpSimd, + RdReadRd = Rd | ReadRd, + RdReadRdRn = Rd | ReadRd | Rn, + RdReadRdRnFpSimd = Rd | ReadRd | Rn | FpSimd, + RdReadRdRnFpSimdFromGpr = Rd | ReadRd | Rn | FpSimdFromGpr, + RdReadRdRnQcFpSimd = Rd | ReadRd | Rn | Qc | FpSimd, + RdReadRdRnRmFpSimd = Rd | ReadRd | Rn | Rm | FpSimd, + RdReadRdRnRmQcFpSimd = Rd | ReadRd | Rn | Rm | Qc | FpSimd, + RdRn = Rd | Rn, + RdRnFpSimd = Rd | Rn | FpSimd, + RdRnFpSimdFromGpr = Rd | Rn | FpSimdFromGpr, + RdRnFpSimdToGpr = Rd | Rn | FpSimdToGpr, + RdRnQcFpSimd = Rd | Rn | Qc | FpSimd, + RdRnRm = Rd | Rn | Rm, + RdRnRmC = Rd | Rn | Rm | C, + RdRnRmCS = Rd | Rn | Rm | C | S, + RdRnRmFpSimd = Rd | Rn | Rm | FpSimd, + RdRnRmNzcv = Rd | Rn | Rm | Nzcv, + RdRnRmNzcvFpSimd = Rd | Rn | Rm | Nzcv | FpSimd, + RdRnRmQcFpSimd = Rd | Rn | Rm | Qc | FpSimd, + RdRnRmRa = Rd | Rn | Rm | Ra, + RdRnRmRaFpSimd = Rd | Rn | Rm | Ra | FpSimd, + RdRnRmS = Rd | Rn | Rm | S, + RdRnRsS = Rd | Rn | Rs | S, + RdRnS = Rd | Rn | S, + RdRnSeqRmFpSimd = Rd | RnSeq | Rm | FpSimd, + RdRnSFpSimd = Rd | Rn | S | FpSimd, + RdRnSFpSimdFromToGpr = Rd | Rn | S | FpSimdFromToGpr, + RdRnSP = Rd | RnSP, + RdRnSPRmS = Rd | RnSP | Rm | S, + RdRnSPS = Rd | RnSP | S, + RdSPRn = RdSP | Rn, + RdSPRnSP = RdSP | RnSP, + RdSPRnSPRm = RdSP | RnSP | Rm, + RnC = Rn | C, + RnNzcvS = Rn | Nzcv | S, + RnRm = Rn | Rm, + RnRmNzcvS = Rn | Rm | Nzcv | S, + RnRmNzcvSFpSimd = Rn | Rm | Nzcv | S | FpSimd, + RnRmSFpSimd = Rn | Rm | S | FpSimd, + RnSPRm = RnSP | Rm, + RtFpSimd = Rt | FpSimd, + RtReadRt = Rt | ReadRt, + RtReadRtRnSP = Rt | ReadRt | RnSP, + RtReadRtRnSPFpSimd = Rt | ReadRt | RnSP | FpSimd, + RtReadRtRnSPFpSimdMemWBack = Rt | ReadRt | RnSP | FpSimd | MemWBack, + RtReadRtRnSPMemWBack = Rt | ReadRt | RnSP | MemWBack, + RtReadRtRnSPRm = Rt | ReadRt | RnSP | Rm, + RtReadRtRnSPRmFpSimd = Rt | ReadRt | RnSP | Rm | FpSimd, + RtReadRtRnSPRmFpSimdMemWBack = Rt | ReadRt | RnSP | Rm | FpSimd | MemWBack, + RtReadRtRnSPRs = Rt | ReadRt | RnSP | Rs, + RtReadRtRnSPRsS = Rt | ReadRt | RnSP | Rs | S, + RtReadRtRt2RnSP = Rt | ReadRt | Rt2 | RnSP, + RtReadRtRt2RnSPFpSimd = Rt | ReadRt | Rt2 | RnSP | FpSimd, + RtReadRtRt2RnSPFpSimdMemWBack = Rt | ReadRt | Rt2 | RnSP | FpSimd | MemWBack, + RtReadRtRt2RnSPMemWBack = Rt | ReadRt | Rt2 | RnSP | MemWBack, + RtReadRtRt2RnSPRs = Rt | ReadRt | Rt2 | RnSP | Rs, + RtReadRtRt2RnSPS = Rt | ReadRt | Rt2 | RnSP | S, + RtRnSP = Rt | RnSP, + RtRnSPFpSimd = Rt | RnSP | FpSimd, + RtRnSPFpSimdMemWBack = Rt | RnSP | FpSimd | MemWBack, + RtRnSPMemWBack = Rt | RnSP | MemWBack, + RtRnSPRm = Rt | RnSP | Rm, + RtRnSPRmFpSimd = Rt | RnSP | Rm | FpSimd, + RtRnSPRmFpSimdMemWBack = Rt | RnSP | Rm | FpSimd | MemWBack, + RtRnSPRs = Rt | RnSP | Rs, + RtRt2RnSP = Rt | Rt2 | RnSP, + RtRt2RnSPFpSimd = Rt | Rt2 | RnSP | FpSimd, + RtRt2RnSPFpSimdMemWBack = Rt | Rt2 | RnSP | FpSimd | MemWBack, + RtRt2RnSPMemWBack = Rt | Rt2 | RnSP | MemWBack, + RtSeqReadRtRnSPFpSimd = RtSeq | ReadRt | RnSP | FpSimd, + RtSeqReadRtRnSPRmFpSimdMemWBack = RtSeq | ReadRt | RnSP | Rm | FpSimd | MemWBack, + RtSeqRnSPFpSimd = RtSeq | RnSP | FpSimd, + RtSeqRnSPRmFpSimdMemWBack = RtSeq | RnSP | Rm | FpSimd | MemWBack, + } +} diff --git a/src/Ryujinx.Cpu/LightningJit/Arm64/InstInfo.cs b/src/Ryujinx.Cpu/LightningJit/Arm64/InstInfo.cs new file mode 100644 index 00000000..031a3657 --- /dev/null +++ b/src/Ryujinx.Cpu/LightningJit/Arm64/InstInfo.cs @@ -0,0 +1,22 @@ +using Ryujinx.Cpu.LightningJit.Graph; + +namespace Ryujinx.Cpu.LightningJit.Arm64 +{ + readonly struct InstInfo + { + public readonly uint Encoding; + public readonly InstName Name; + public readonly InstFlags Flags; + public readonly AddressForm AddressForm; + public readonly RegisterUse RegisterUse; + + public InstInfo(uint encoding, InstName name, InstFlags flags, AddressForm addressForm, in RegisterUse registerUse) + { + Encoding = encoding; + Name = name; + Flags = flags; + AddressForm = addressForm; + RegisterUse = registerUse; + } + } +} diff --git a/src/Ryujinx.Cpu/LightningJit/Arm64/InstName.cs b/src/Ryujinx.Cpu/LightningJit/Arm64/InstName.cs new file mode 100644 index 00000000..58d78ae6 --- /dev/null +++ b/src/Ryujinx.Cpu/LightningJit/Arm64/InstName.cs @@ -0,0 +1,1134 @@ +namespace Ryujinx.Cpu.LightningJit.Arm64 +{ + enum InstName + { + Abs, + AbsAdvsimdS, + AbsAdvsimdV, + Adc, + Adcs, + AddAddsubExt, + AddAddsubImm, + AddAddsubShift, + AddAdvsimdS, + AddAdvsimdV, + Addg, + AddhnAdvsimd, + AddpAdvsimdPair, + AddpAdvsimdVec, + AddsAddsubExt, + AddsAddsubImm, + AddsAddsubShift, + AddvAdvsimd, + Adr, + Adrp, + AesdAdvsimd, + AeseAdvsimd, + AesimcAdvsimd, + AesmcAdvsimd, + AndAdvsimd, + AndLogImm, + AndLogShift, + AndsLogImm, + AndsLogShift, + Asrv, + Autda, + Autdb, + AutiaGeneral, + AutiaSystem, + AutibGeneral, + AutibSystem, + Axflag, + BcaxAdvsimd, + BcCond, + BCond, + BfcvtFloat, + BfcvtnAdvsimd, + BfdotAdvsimdElt, + BfdotAdvsimdVec, + Bfm, + BfmlalAdvsimdElt, + BfmlalAdvsimdVec, + BfmmlaAdvsimd, + BicAdvsimdImm, + BicAdvsimdReg, + BicLogShift, + Bics, + BifAdvsimd, + BitAdvsimd, + Bl, + Blr, + Blra, + Br, + Bra, + Brk, + BslAdvsimd, + Bti, + BUncond, + Cas, + Casb, + Cash, + Casp, + Cbnz, + Cbz, + CcmnImm, + CcmnReg, + CcmpImm, + CcmpReg, + Cfinv, + Chkfeat, + Clrbhb, + Clrex, + ClsAdvsimd, + ClsInt, + ClzAdvsimd, + ClzInt, + CmeqAdvsimdRegS, + CmeqAdvsimdRegV, + CmeqAdvsimdZeroS, + CmeqAdvsimdZeroV, + CmgeAdvsimdRegS, + CmgeAdvsimdRegV, + CmgeAdvsimdZeroS, + CmgeAdvsimdZeroV, + CmgtAdvsimdRegS, + CmgtAdvsimdRegV, + CmgtAdvsimdZeroS, + CmgtAdvsimdZeroV, + CmhiAdvsimdS, + CmhiAdvsimdV, + CmhsAdvsimdS, + CmhsAdvsimdV, + CmleAdvsimdS, + CmleAdvsimdV, + CmltAdvsimdS, + CmltAdvsimdV, + CmtstAdvsimdS, + CmtstAdvsimdV, + Cnt, + CntAdvsimd, + Cpyfp, + Cpyfpn, + Cpyfprn, + Cpyfprt, + Cpyfprtn, + Cpyfprtrn, + Cpyfprtwn, + Cpyfpt, + Cpyfptn, + Cpyfptrn, + Cpyfptwn, + Cpyfpwn, + Cpyfpwt, + Cpyfpwtn, + Cpyfpwtrn, + Cpyfpwtwn, + Cpyp, + Cpypn, + Cpyprn, + Cpyprt, + Cpyprtn, + Cpyprtrn, + Cpyprtwn, + Cpypt, + Cpyptn, + Cpyptrn, + Cpyptwn, + Cpypwn, + Cpypwt, + Cpypwtn, + Cpypwtrn, + Cpypwtwn, + Crc32, + Crc32c, + Csdb, + Csel, + Csinc, + Csinv, + Csneg, + Ctz, + Dcps1, + Dcps2, + Dcps3, + Dgh, + Dmb, + Drps, + DsbDsbMemory, + DsbDsbNxs, + DupAdvsimdEltScalarFromElement, + DupAdvsimdEltVectorFromElement, + DupAdvsimdGen, + Eon, + Eor3Advsimd, + EorAdvsimd, + EorLogImm, + EorLogShift, + Eret, + Ereta, + Esb, + ExtAdvsimd, + Extr, + FabdAdvsimdS, + FabdAdvsimdSH, + FabdAdvsimdV, + FabdAdvsimdVH, + FabsAdvsimdHalf, + FabsAdvsimdSingleAndDouble, + FabsFloat, + FacgeAdvsimdS, + FacgeAdvsimdSH, + FacgeAdvsimdV, + FacgeAdvsimdVH, + FacgtAdvsimdS, + FacgtAdvsimdSH, + FacgtAdvsimdV, + FacgtAdvsimdVH, + FaddAdvsimdHalf, + FaddAdvsimdSingleAndDouble, + FaddFloat, + FaddpAdvsimdPairHalf, + FaddpAdvsimdPairSingleAndDouble, + FaddpAdvsimdVecHalf, + FaddpAdvsimdVecSingleAndDouble, + FcaddAdvsimdVec, + FccmpeFloat, + FccmpFloat, + FcmeqAdvsimdRegS, + FcmeqAdvsimdRegSH, + FcmeqAdvsimdRegV, + FcmeqAdvsimdRegVH, + FcmeqAdvsimdZeroS, + FcmeqAdvsimdZeroSH, + FcmeqAdvsimdZeroV, + FcmeqAdvsimdZeroVH, + FcmgeAdvsimdRegS, + FcmgeAdvsimdRegSH, + FcmgeAdvsimdRegV, + FcmgeAdvsimdRegVH, + FcmgeAdvsimdZeroS, + FcmgeAdvsimdZeroSH, + FcmgeAdvsimdZeroV, + FcmgeAdvsimdZeroVH, + FcmgtAdvsimdRegS, + FcmgtAdvsimdRegSH, + FcmgtAdvsimdRegV, + FcmgtAdvsimdRegVH, + FcmgtAdvsimdZeroS, + FcmgtAdvsimdZeroSH, + FcmgtAdvsimdZeroV, + FcmgtAdvsimdZeroVH, + FcmlaAdvsimdElt, + FcmlaAdvsimdVec, + FcmleAdvsimdS, + FcmleAdvsimdSH, + FcmleAdvsimdV, + FcmleAdvsimdVH, + FcmltAdvsimdS, + FcmltAdvsimdSH, + FcmltAdvsimdV, + FcmltAdvsimdVH, + FcmpeFloat, + FcmpFloat, + FcselFloat, + FcvtasAdvsimdS, + FcvtasAdvsimdSH, + FcvtasAdvsimdV, + FcvtasAdvsimdVH, + FcvtasFloat, + FcvtauAdvsimdS, + FcvtauAdvsimdSH, + FcvtauAdvsimdV, + FcvtauAdvsimdVH, + FcvtauFloat, + FcvtFloat, + FcvtlAdvsimd, + FcvtmsAdvsimdS, + FcvtmsAdvsimdSH, + FcvtmsAdvsimdV, + FcvtmsAdvsimdVH, + FcvtmsFloat, + FcvtmuAdvsimdS, + FcvtmuAdvsimdSH, + FcvtmuAdvsimdV, + FcvtmuAdvsimdVH, + FcvtmuFloat, + FcvtnAdvsimd, + FcvtnsAdvsimdS, + FcvtnsAdvsimdSH, + FcvtnsAdvsimdV, + FcvtnsAdvsimdVH, + FcvtnsFloat, + FcvtnuAdvsimdS, + FcvtnuAdvsimdSH, + FcvtnuAdvsimdV, + FcvtnuAdvsimdVH, + FcvtnuFloat, + FcvtpsAdvsimdS, + FcvtpsAdvsimdSH, + FcvtpsAdvsimdV, + FcvtpsAdvsimdVH, + FcvtpsFloat, + FcvtpuAdvsimdS, + FcvtpuAdvsimdSH, + FcvtpuAdvsimdV, + FcvtpuAdvsimdVH, + FcvtpuFloat, + FcvtxnAdvsimdS, + FcvtxnAdvsimdV, + FcvtzsAdvsimdFixS, + FcvtzsAdvsimdFixV, + FcvtzsAdvsimdIntS, + FcvtzsAdvsimdIntSH, + FcvtzsAdvsimdIntV, + FcvtzsAdvsimdIntVH, + FcvtzsFloatFix, + FcvtzsFloatInt, + FcvtzuAdvsimdFixS, + FcvtzuAdvsimdFixV, + FcvtzuAdvsimdIntS, + FcvtzuAdvsimdIntSH, + FcvtzuAdvsimdIntV, + FcvtzuAdvsimdIntVH, + FcvtzuFloatFix, + FcvtzuFloatInt, + FdivAdvsimdHalf, + FdivAdvsimdSingleAndDouble, + FdivFloat, + Fjcvtzs, + FmaddFloat, + FmaxAdvsimdHalf, + FmaxAdvsimdSingleAndDouble, + FmaxFloat, + FmaxnmAdvsimdHalf, + FmaxnmAdvsimdSingleAndDouble, + FmaxnmFloat, + FmaxnmpAdvsimdPairHalf, + FmaxnmpAdvsimdPairSingleAndDouble, + FmaxnmpAdvsimdVecHalf, + FmaxnmpAdvsimdVecSingleAndDouble, + FmaxnmvAdvsimdHalf, + FmaxnmvAdvsimdSingleAndDouble, + FmaxpAdvsimdPairHalf, + FmaxpAdvsimdPairSingleAndDouble, + FmaxpAdvsimdVecHalf, + FmaxpAdvsimdVecSingleAndDouble, + FmaxvAdvsimdHalf, + FmaxvAdvsimdSingleAndDouble, + FminAdvsimdHalf, + FminAdvsimdSingleAndDouble, + FminFloat, + FminnmAdvsimdHalf, + FminnmAdvsimdSingleAndDouble, + FminnmFloat, + FminnmpAdvsimdPairHalf, + FminnmpAdvsimdPairSingleAndDouble, + FminnmpAdvsimdVecHalf, + FminnmpAdvsimdVecSingleAndDouble, + FminnmvAdvsimdHalf, + FminnmvAdvsimdSingleAndDouble, + FminpAdvsimdPairHalf, + FminpAdvsimdPairSingleAndDouble, + FminpAdvsimdVecHalf, + FminpAdvsimdVecSingleAndDouble, + FminvAdvsimdHalf, + FminvAdvsimdSingleAndDouble, + FmlaAdvsimdElt2regElementHalf, + FmlaAdvsimdElt2regElementSingleAndDouble, + FmlaAdvsimdElt2regScalarHalf, + FmlaAdvsimdElt2regScalarSingleAndDouble, + FmlaAdvsimdVecHalf, + FmlaAdvsimdVecSingleAndDouble, + FmlalAdvsimdEltFmlal, + FmlalAdvsimdEltFmlal2, + FmlalAdvsimdVecFmlal, + FmlalAdvsimdVecFmlal2, + FmlsAdvsimdElt2regElementHalf, + FmlsAdvsimdElt2regElementSingleAndDouble, + FmlsAdvsimdElt2regScalarHalf, + FmlsAdvsimdElt2regScalarSingleAndDouble, + FmlsAdvsimdVecHalf, + FmlsAdvsimdVecSingleAndDouble, + FmlslAdvsimdEltFmlsl, + FmlslAdvsimdEltFmlsl2, + FmlslAdvsimdVecFmlsl, + FmlslAdvsimdVecFmlsl2, + FmovAdvsimdPerHalf, + FmovAdvsimdSingleAndDouble, + FmovFloat, + FmovFloatGen, + FmovFloatImm, + FmsubFloat, + FmulAdvsimdElt2regElementHalf, + FmulAdvsimdElt2regElementSingleAndDouble, + FmulAdvsimdElt2regScalarHalf, + FmulAdvsimdElt2regScalarSingleAndDouble, + FmulAdvsimdVecHalf, + FmulAdvsimdVecSingleAndDouble, + FmulFloat, + FmulxAdvsimdElt2regElementHalf, + FmulxAdvsimdElt2regElementSingleAndDouble, + FmulxAdvsimdElt2regScalarHalf, + FmulxAdvsimdElt2regScalarSingleAndDouble, + FmulxAdvsimdVecS, + FmulxAdvsimdVecSH, + FmulxAdvsimdVecV, + FmulxAdvsimdVecVH, + FnegAdvsimdHalf, + FnegAdvsimdSingleAndDouble, + FnegFloat, + FnmaddFloat, + FnmsubFloat, + FnmulFloat, + FrecpeAdvsimdS, + FrecpeAdvsimdSH, + FrecpeAdvsimdV, + FrecpeAdvsimdVH, + FrecpsAdvsimdS, + FrecpsAdvsimdSH, + FrecpsAdvsimdV, + FrecpsAdvsimdVH, + FrecpxAdvsimdHalf, + FrecpxAdvsimdSingleAndDouble, + Frint32xAdvsimd, + Frint32xFloat, + Frint32zAdvsimd, + Frint32zFloat, + Frint64xAdvsimd, + Frint64xFloat, + Frint64zAdvsimd, + Frint64zFloat, + FrintaAdvsimdHalf, + FrintaAdvsimdSingleAndDouble, + FrintaFloat, + FrintiAdvsimdHalf, + FrintiAdvsimdSingleAndDouble, + FrintiFloat, + FrintmAdvsimdHalf, + FrintmAdvsimdSingleAndDouble, + FrintmFloat, + FrintnAdvsimdHalf, + FrintnAdvsimdSingleAndDouble, + FrintnFloat, + FrintpAdvsimdHalf, + FrintpAdvsimdSingleAndDouble, + FrintpFloat, + FrintxAdvsimdHalf, + FrintxAdvsimdSingleAndDouble, + FrintxFloat, + FrintzAdvsimdHalf, + FrintzAdvsimdSingleAndDouble, + FrintzFloat, + FrsqrteAdvsimdS, + FrsqrteAdvsimdSH, + FrsqrteAdvsimdV, + FrsqrteAdvsimdVH, + FrsqrtsAdvsimdS, + FrsqrtsAdvsimdSH, + FrsqrtsAdvsimdV, + FrsqrtsAdvsimdVH, + FsqrtAdvsimdHalf, + FsqrtAdvsimdSingleAndDouble, + FsqrtFloat, + FsubAdvsimdHalf, + FsubAdvsimdSingleAndDouble, + FsubFloat, + Gcsb, + Gcsstr, + Gcssttr, + Gmi, + Hint, + Hlt, + Hvc, + InsAdvsimdElt, + InsAdvsimdGen, + Irg, + Isb, + Ld1AdvsimdMultAsNoPostIndex, + Ld1AdvsimdMultAsPostIndex, + Ld1AdvsimdSnglAsNoPostIndex, + Ld1AdvsimdSnglAsPostIndex, + Ld1rAdvsimdAsNoPostIndex, + Ld1rAdvsimdAsPostIndex, + Ld2AdvsimdMultAsNoPostIndex, + Ld2AdvsimdMultAsPostIndex, + Ld2AdvsimdSnglAsNoPostIndex, + Ld2AdvsimdSnglAsPostIndex, + Ld2rAdvsimdAsNoPostIndex, + Ld2rAdvsimdAsPostIndex, + Ld3AdvsimdMultAsNoPostIndex, + Ld3AdvsimdMultAsPostIndex, + Ld3AdvsimdSnglAsNoPostIndex, + Ld3AdvsimdSnglAsPostIndex, + Ld3rAdvsimdAsNoPostIndex, + Ld3rAdvsimdAsPostIndex, + Ld4AdvsimdMultAsNoPostIndex, + Ld4AdvsimdMultAsPostIndex, + Ld4AdvsimdSnglAsNoPostIndex, + Ld4AdvsimdSnglAsPostIndex, + Ld4rAdvsimdAsNoPostIndex, + Ld4rAdvsimdAsPostIndex, + Ld64b, + Ldadd, + Ldaddb, + Ldaddh, + Ldap1AdvsimdSngl, + Ldaprb, + LdaprBaseRegister, + Ldaprh, + LdaprPostIndexed, + Ldapurb, + LdapurFpsimd, + LdapurGen, + Ldapurh, + Ldapursb, + Ldapursh, + Ldapursw, + Ldar, + Ldarb, + Ldarh, + Ldaxp, + Ldaxr, + Ldaxrb, + Ldaxrh, + Ldclr, + Ldclrb, + Ldclrh, + Ldclrp, + Ldeor, + Ldeorb, + Ldeorh, + Ldg, + Ldgm, + Ldiapp, + Ldlar, + Ldlarb, + Ldlarh, + LdnpFpsimd, + LdnpGen, + LdpFpsimdPostIndexed, + LdpFpsimdPreIndexed, + LdpFpsimdSignedScaledOffset, + LdpGenPostIndexed, + LdpGenPreIndexed, + LdpGenSignedScaledOffset, + LdpswPostIndexed, + LdpswPreIndexed, + LdpswSignedScaledOffset, + Ldra, + LdrbImmPostIndexed, + LdrbImmPreIndexed, + LdrbImmUnsignedScaledOffset, + LdrbReg, + LdrhImmPostIndexed, + LdrhImmPreIndexed, + LdrhImmUnsignedScaledOffset, + LdrhReg, + LdrImmFpsimdPostIndexed, + LdrImmFpsimdPreIndexed, + LdrImmFpsimdUnsignedScaledOffset, + LdrImmGenPostIndexed, + LdrImmGenPreIndexed, + LdrImmGenUnsignedScaledOffset, + LdrLitFpsimd, + LdrLitGen, + LdrRegFpsimd, + LdrRegGen, + LdrsbImmPostIndexed, + LdrsbImmPreIndexed, + LdrsbImmUnsignedScaledOffset, + LdrsbReg, + LdrshImmPostIndexed, + LdrshImmPreIndexed, + LdrshImmUnsignedScaledOffset, + LdrshReg, + LdrswImmPostIndexed, + LdrswImmPreIndexed, + LdrswImmUnsignedScaledOffset, + LdrswLit, + LdrswReg, + Ldset, + Ldsetb, + Ldseth, + Ldsetp, + Ldsmax, + Ldsmaxb, + Ldsmaxh, + Ldsmin, + Ldsminb, + Ldsminh, + Ldtr, + Ldtrb, + Ldtrh, + Ldtrsb, + Ldtrsh, + Ldtrsw, + Ldumax, + Ldumaxb, + Ldumaxh, + Ldumin, + Lduminb, + Lduminh, + Ldurb, + LdurFpsimd, + LdurGen, + Ldurh, + Ldursb, + Ldursh, + Ldursw, + Ldxp, + Ldxr, + Ldxrb, + Ldxrh, + Lslv, + Lsrv, + Madd, + MlaAdvsimdElt, + MlaAdvsimdVec, + MlsAdvsimdElt, + MlsAdvsimdVec, + MoviAdvsimd, + Movk, + Movn, + Movz, + Mrrs, + Mrs, + MsrImm, + Msrr, + MsrReg, + Msub, + MulAdvsimdElt, + MulAdvsimdVec, + MvniAdvsimd, + NegAdvsimdS, + NegAdvsimdV, + Nop, + NotAdvsimd, + OrnAdvsimd, + OrnLogShift, + OrrAdvsimdImm, + OrrAdvsimdReg, + OrrLogImm, + OrrLogShift, + Pacda, + Pacdb, + Pacga, + PaciaGeneral, + PaciaSystem, + PacibGeneral, + PacibSystem, + PmulAdvsimd, + PmullAdvsimd, + PrfmImm, + PrfmLit, + PrfmReg, + Prfum, + Psb, + RaddhnAdvsimd, + Rax1Advsimd, + RbitAdvsimd, + RbitInt, + Rcwcas, + Rcwcasp, + Rcwclr, + Rcwclrp, + Rcwscas, + Rcwscasp, + Rcwsclr, + Rcwsclrp, + Rcwset, + Rcwsetp, + Rcwsset, + Rcwssetp, + Rcwsswp, + Rcwsswpp, + Rcwswp, + Rcwswpp, + Ret, + Reta, + Rev, + Rev16Advsimd, + Rev16Int, + Rev32Advsimd, + Rev32Int, + Rev64Advsimd, + Rmif, + Rorv, + RprfmReg, + RshrnAdvsimd, + RsubhnAdvsimd, + SabaAdvsimd, + SabalAdvsimd, + SabdAdvsimd, + SabdlAdvsimd, + SadalpAdvsimd, + SaddlAdvsimd, + SaddlpAdvsimd, + SaddlvAdvsimd, + SaddwAdvsimd, + Sb, + Sbc, + Sbcs, + Sbfm, + ScvtfAdvsimdFixS, + ScvtfAdvsimdFixV, + ScvtfAdvsimdIntS, + ScvtfAdvsimdIntSH, + ScvtfAdvsimdIntV, + ScvtfAdvsimdIntVH, + ScvtfFloatFix, + ScvtfFloatInt, + Sdiv, + SdotAdvsimdElt, + SdotAdvsimdVec, + Setf, + Setgp, + Setgpn, + Setgpt, + Setgptn, + Setp, + Setpn, + Setpt, + Setptn, + Sev, + Sevl, + Sha1cAdvsimd, + Sha1hAdvsimd, + Sha1mAdvsimd, + Sha1pAdvsimd, + Sha1su0Advsimd, + Sha1su1Advsimd, + Sha256h2Advsimd, + Sha256hAdvsimd, + Sha256su0Advsimd, + Sha256su1Advsimd, + Sha512h2Advsimd, + Sha512hAdvsimd, + Sha512su0Advsimd, + Sha512su1Advsimd, + ShaddAdvsimd, + ShlAdvsimdS, + ShlAdvsimdV, + ShllAdvsimd, + ShrnAdvsimd, + ShsubAdvsimd, + SliAdvsimdS, + SliAdvsimdV, + Sm3partw1Advsimd, + Sm3partw2Advsimd, + Sm3ss1Advsimd, + Sm3tt1aAdvsimd, + Sm3tt1bAdvsimd, + Sm3tt2aAdvsimd, + Sm3tt2bAdvsimd, + Sm4eAdvsimd, + Sm4ekeyAdvsimd, + Smaddl, + SmaxAdvsimd, + SmaxImm, + SmaxpAdvsimd, + SmaxReg, + SmaxvAdvsimd, + Smc, + SminAdvsimd, + SminImm, + SminpAdvsimd, + SminReg, + SminvAdvsimd, + SmlalAdvsimdElt, + SmlalAdvsimdVec, + SmlslAdvsimdElt, + SmlslAdvsimdVec, + SmmlaAdvsimdVec, + SmovAdvsimd, + Smsubl, + Smulh, + SmullAdvsimdElt, + SmullAdvsimdVec, + SqabsAdvsimdS, + SqabsAdvsimdV, + SqaddAdvsimdS, + SqaddAdvsimdV, + SqdmlalAdvsimdElt2regElement, + SqdmlalAdvsimdElt2regScalar, + SqdmlalAdvsimdVecS, + SqdmlalAdvsimdVecV, + SqdmlslAdvsimdElt2regElement, + SqdmlslAdvsimdElt2regScalar, + SqdmlslAdvsimdVecS, + SqdmlslAdvsimdVecV, + SqdmulhAdvsimdElt2regElement, + SqdmulhAdvsimdElt2regScalar, + SqdmulhAdvsimdVecS, + SqdmulhAdvsimdVecV, + SqdmullAdvsimdElt2regElement, + SqdmullAdvsimdElt2regScalar, + SqdmullAdvsimdVecS, + SqdmullAdvsimdVecV, + SqnegAdvsimdS, + SqnegAdvsimdV, + SqrdmlahAdvsimdElt2regElement, + SqrdmlahAdvsimdElt2regScalar, + SqrdmlahAdvsimdVecS, + SqrdmlahAdvsimdVecV, + SqrdmlshAdvsimdElt2regElement, + SqrdmlshAdvsimdElt2regScalar, + SqrdmlshAdvsimdVecS, + SqrdmlshAdvsimdVecV, + SqrdmulhAdvsimdElt2regElement, + SqrdmulhAdvsimdElt2regScalar, + SqrdmulhAdvsimdVecS, + SqrdmulhAdvsimdVecV, + SqrshlAdvsimdS, + SqrshlAdvsimdV, + SqrshrnAdvsimdS, + SqrshrnAdvsimdV, + SqrshrunAdvsimdS, + SqrshrunAdvsimdV, + SqshlAdvsimdImmS, + SqshlAdvsimdImmV, + SqshlAdvsimdRegS, + SqshlAdvsimdRegV, + SqshluAdvsimdS, + SqshluAdvsimdV, + SqshrnAdvsimdS, + SqshrnAdvsimdV, + SqshrunAdvsimdS, + SqshrunAdvsimdV, + SqsubAdvsimdS, + SqsubAdvsimdV, + SqxtnAdvsimdS, + SqxtnAdvsimdV, + SqxtunAdvsimdS, + SqxtunAdvsimdV, + SrhaddAdvsimd, + SriAdvsimdS, + SriAdvsimdV, + SrshlAdvsimdS, + SrshlAdvsimdV, + SrshrAdvsimdS, + SrshrAdvsimdV, + SrsraAdvsimdS, + SrsraAdvsimdV, + SshlAdvsimdS, + SshlAdvsimdV, + SshllAdvsimd, + SshrAdvsimdS, + SshrAdvsimdV, + SsraAdvsimdS, + SsraAdvsimdV, + SsublAdvsimd, + SsubwAdvsimd, + St1AdvsimdMultAsNoPostIndex, + St1AdvsimdMultAsPostIndex, + St1AdvsimdSnglAsNoPostIndex, + St1AdvsimdSnglAsPostIndex, + St2AdvsimdMultAsNoPostIndex, + St2AdvsimdMultAsPostIndex, + St2AdvsimdSnglAsNoPostIndex, + St2AdvsimdSnglAsPostIndex, + St2gPostIndexed, + St2gPreIndexed, + St2gSignedScaledOffset, + St3AdvsimdMultAsNoPostIndex, + St3AdvsimdMultAsPostIndex, + St3AdvsimdSnglAsNoPostIndex, + St3AdvsimdSnglAsPostIndex, + St4AdvsimdMultAsNoPostIndex, + St4AdvsimdMultAsPostIndex, + St4AdvsimdSnglAsNoPostIndex, + St4AdvsimdSnglAsPostIndex, + St64b, + St64bv, + St64bv0, + Stgm, + StgPostIndexed, + StgpPostIndexed, + StgpPreIndexed, + StgPreIndexed, + StgpSignedScaledOffset, + StgSignedScaledOffset, + Stilp, + Stl1AdvsimdSngl, + Stllr, + Stllrb, + Stllrh, + Stlrb, + StlrBaseRegister, + Stlrh, + StlrPreIndexed, + Stlurb, + StlurFpsimd, + StlurGen, + Stlurh, + Stlxp, + Stlxr, + Stlxrb, + Stlxrh, + StnpFpsimd, + StnpGen, + StpFpsimdPostIndexed, + StpFpsimdPreIndexed, + StpFpsimdSignedScaledOffset, + StpGenPostIndexed, + StpGenPreIndexed, + StpGenSignedScaledOffset, + StrbImmPostIndexed, + StrbImmPreIndexed, + StrbImmUnsignedScaledOffset, + StrbReg, + StrhImmPostIndexed, + StrhImmPreIndexed, + StrhImmUnsignedScaledOffset, + StrhReg, + StrImmFpsimdPostIndexed, + StrImmFpsimdPreIndexed, + StrImmFpsimdUnsignedScaledOffset, + StrImmGenPostIndexed, + StrImmGenPreIndexed, + StrImmGenUnsignedScaledOffset, + StrRegFpsimd, + StrRegGen, + Sttr, + Sttrb, + Sttrh, + Sturb, + SturFpsimd, + SturGen, + Sturh, + Stxp, + Stxr, + Stxrb, + Stxrh, + Stz2gPostIndexed, + Stz2gPreIndexed, + Stz2gSignedScaledOffset, + Stzgm, + StzgPostIndexed, + StzgPreIndexed, + StzgSignedScaledOffset, + SubAddsubExt, + SubAddsubImm, + SubAddsubShift, + SubAdvsimdS, + SubAdvsimdV, + Subg, + SubhnAdvsimd, + Subp, + Subps, + SubsAddsubExt, + SubsAddsubImm, + SubsAddsubShift, + SudotAdvsimdElt, + SuqaddAdvsimdS, + SuqaddAdvsimdV, + Svc, + Swp, + Swpb, + Swph, + Swpp, + Sys, + Sysl, + Sysp, + TblAdvsimd, + Tbnz, + TbxAdvsimd, + Tbz, + Tcancel, + Tcommit, + Trn1Advsimd, + Trn2Advsimd, + Tsb, + Tstart, + Ttest, + UabaAdvsimd, + UabalAdvsimd, + UabdAdvsimd, + UabdlAdvsimd, + UadalpAdvsimd, + UaddlAdvsimd, + UaddlpAdvsimd, + UaddlvAdvsimd, + UaddwAdvsimd, + Ubfm, + UcvtfAdvsimdFixS, + UcvtfAdvsimdFixV, + UcvtfAdvsimdIntS, + UcvtfAdvsimdIntSH, + UcvtfAdvsimdIntV, + UcvtfAdvsimdIntVH, + UcvtfFloatFix, + UcvtfFloatInt, + UdfPermUndef, + Udiv, + UdotAdvsimdElt, + UdotAdvsimdVec, + UhaddAdvsimd, + UhsubAdvsimd, + Umaddl, + UmaxAdvsimd, + UmaxImm, + UmaxpAdvsimd, + UmaxReg, + UmaxvAdvsimd, + UminAdvsimd, + UminImm, + UminpAdvsimd, + UminReg, + UminvAdvsimd, + UmlalAdvsimdElt, + UmlalAdvsimdVec, + UmlslAdvsimdElt, + UmlslAdvsimdVec, + UmmlaAdvsimdVec, + UmovAdvsimd, + Umsubl, + Umulh, + UmullAdvsimdElt, + UmullAdvsimdVec, + UqaddAdvsimdS, + UqaddAdvsimdV, + UqrshlAdvsimdS, + UqrshlAdvsimdV, + UqrshrnAdvsimdS, + UqrshrnAdvsimdV, + UqshlAdvsimdImmS, + UqshlAdvsimdImmV, + UqshlAdvsimdRegS, + UqshlAdvsimdRegV, + UqshrnAdvsimdS, + UqshrnAdvsimdV, + UqsubAdvsimdS, + UqsubAdvsimdV, + UqxtnAdvsimdS, + UqxtnAdvsimdV, + UrecpeAdvsimd, + UrhaddAdvsimd, + UrshlAdvsimdS, + UrshlAdvsimdV, + UrshrAdvsimdS, + UrshrAdvsimdV, + UrsqrteAdvsimd, + UrsraAdvsimdS, + UrsraAdvsimdV, + UsdotAdvsimdElt, + UsdotAdvsimdVec, + UshlAdvsimdS, + UshlAdvsimdV, + UshllAdvsimd, + UshrAdvsimdS, + UshrAdvsimdV, + UsmmlaAdvsimdVec, + UsqaddAdvsimdS, + UsqaddAdvsimdV, + UsraAdvsimdS, + UsraAdvsimdV, + UsublAdvsimd, + UsubwAdvsimd, + Uzp1Advsimd, + Uzp2Advsimd, + Wfe, + Wfet, + Wfi, + Wfit, + Xaflag, + XarAdvsimd, + XpacGeneral, + XpacSystem, + XtnAdvsimd, + Yield, + Zip1Advsimd, + Zip2Advsimd, + } + + static class InstNameExtensions + { + public static bool IsCall(this InstName name) + { + return name == InstName.Bl || name == InstName.Blr; + } + + public static bool IsControlFlowOrException(this InstName name) + { + switch (name) + { + case InstName.BUncond: + case InstName.BCond: + case InstName.Bl: + case InstName.Blr: + case InstName.Br: + case InstName.Brk: + case InstName.Cbnz: + case InstName.Cbz: + case InstName.Ret: + case InstName.Tbnz: + case InstName.Tbz: + case InstName.Svc: + case InstName.UdfPermUndef: + return true; + } + + return false; + } + + public static bool IsException(this InstName name) + { + switch (name) + { + case InstName.Brk: + case InstName.Svc: + case InstName.UdfPermUndef: + return true; + } + + return false; + } + + public static bool IsSystem(this InstName name) + { + switch (name) + { + case InstName.Mrs: + case InstName.MsrImm: + case InstName.MsrReg: + return true; + } + + return name.IsException(); + } + + public static bool IsSystemOrCall(this InstName name) + { + switch (name) + { + case InstName.Bl: + case InstName.Blr: + case InstName.Svc: + case InstName.Mrs: + case InstName.MsrImm: + case InstName.MsrReg: + return true; + } + + return false; + } + + public static bool IsPrivileged(this InstName name) + { + switch (name) + { + case InstName.Dcps1: + case InstName.Dcps2: + case InstName.Dcps3: + case InstName.Drps: + case InstName.Eret: + case InstName.Ereta: + case InstName.Hvc: + case InstName.MsrImm: + case InstName.Smc: + return true; + } + + return false; + } + } +} diff --git a/src/Ryujinx.Cpu/LightningJit/Arm64/MultiBlock.cs b/src/Ryujinx.Cpu/LightningJit/Arm64/MultiBlock.cs new file mode 100644 index 00000000..8ac65059 --- /dev/null +++ b/src/Ryujinx.Cpu/LightningJit/Arm64/MultiBlock.cs @@ -0,0 +1,64 @@ +using Ryujinx.Cpu.LightningJit.Graph; +using System; +using System.Collections.Generic; + +namespace Ryujinx.Cpu.LightningJit.Arm64 +{ + class MultiBlock : IBlockList + { + public readonly List<Block> Blocks; + public readonly RegisterMask[] ReadMasks; + public readonly RegisterMask[] WriteMasks; + public readonly RegisterMask GlobalUseMask; + public readonly bool HasHostCall; + public readonly bool HasMemoryInstruction; + public readonly bool IsTruncated; + + public int Count => Blocks.Count; + + public IBlock this[int index] => Blocks[index]; + + public MultiBlock(List<Block> blocks, RegisterMask globalUseMask, bool hasHostCall, bool hasMemoryInstruction) + { + Blocks = blocks; + + (ReadMasks, WriteMasks) = DataFlow.GetGlobalUses(this); + + GlobalUseMask = globalUseMask; + HasHostCall = hasHostCall; + HasMemoryInstruction = hasMemoryInstruction; + IsTruncated = blocks[^1].IsTruncated; + } + + public void PrintDebugInfo() + { + foreach (Block block in Blocks) + { + Console.WriteLine($"bb {block.Index}"); + + List<int> predList = new(); + List<int> succList = new(); + + for (int index = 0; index < block.PredecessorsCount; index++) + { + predList.Add(block.GetPredecessor(index).Index); + } + + for (int index = 0; index < block.SuccessorsCount; index++) + { + succList.Add(block.GetSuccessor(index).Index); + } + + Console.WriteLine($" predecessors: {string.Join(' ', predList)}"); + Console.WriteLine($" successors: {string.Join(' ', succList)}"); + Console.WriteLine($" gpr read mask: 0x{ReadMasks[block.Index].GprMask:X} 0x{block.ComputeUseMasks().Read.GprMask:X}"); + Console.WriteLine($" gpr write mask: 0x{WriteMasks[block.Index].GprMask:X}"); + + for (int index = 0; index < block.Instructions.Count; index++) + { + Console.WriteLine($" {index} 0x{block.Instructions[index].Encoding:X8} {block.Instructions[index].Name}"); + } + } + } + } +} diff --git a/src/Ryujinx.Cpu/LightningJit/Arm64/RegisterAllocator.cs b/src/Ryujinx.Cpu/LightningJit/Arm64/RegisterAllocator.cs new file mode 100644 index 00000000..c9a93209 --- /dev/null +++ b/src/Ryujinx.Cpu/LightningJit/Arm64/RegisterAllocator.cs @@ -0,0 +1,154 @@ +using Ryujinx.Cpu.LightningJit.CodeGen.Arm64; +using System; +using System.Diagnostics; +using System.Numerics; + +namespace Ryujinx.Cpu.LightningJit.Arm64 +{ + class RegisterAllocator + { + public const int MaxTemps = 1; + public const int MaxTempsInclFixed = MaxTemps + 2; + + private uint _gprMask; + private readonly uint _fpSimdMask; + private readonly uint _pStateMask; + + private uint _tempGprsMask; + + private readonly int[] _registerMap; + + public int FixedContextRegister { get; } + public int FixedPageTableRegister { get; } + + public uint AllGprMask => (_gprMask & ~RegisterUtils.ReservedRegsMask) | _tempGprsMask; + public uint AllFpSimdMask => _fpSimdMask; + public uint AllPStateMask => _pStateMask; + + public RegisterAllocator(uint gprMask, uint fpSimdMask, uint pStateMask, bool hasHostCall) + { + _gprMask = gprMask; + _fpSimdMask = fpSimdMask; + _pStateMask = pStateMask; + + if (hasHostCall) + { + // If the function has calls, we can avoid the need to spill those registers across + // calls by puting them on callee saved registers. + + FixedContextRegister = AllocateAndMarkTempGprRegisterWithPreferencing(); + FixedPageTableRegister = AllocateAndMarkTempGprRegisterWithPreferencing(); + } + else + { + FixedContextRegister = AllocateAndMarkTempGprRegister(); + FixedPageTableRegister = AllocateAndMarkTempGprRegister(); + } + + _tempGprsMask = (1u << FixedContextRegister) | (1u << FixedPageTableRegister); + + _registerMap = new int[32]; + + for (int index = 0; index < _registerMap.Length; index++) + { + _registerMap[index] = index; + } + + BuildRegisterMap(_registerMap); + + Span<int> tempRegisters = stackalloc int[MaxTemps]; + + for (int index = 0; index < tempRegisters.Length; index++) + { + tempRegisters[index] = AllocateAndMarkTempGprRegister(); + } + + for (int index = 0; index < tempRegisters.Length; index++) + { + FreeTempGprRegister(tempRegisters[index]); + } + } + + private void BuildRegisterMap(Span<int> map) + { + uint mask = _gprMask & RegisterUtils.ReservedRegsMask; + + while (mask != 0) + { + int index = BitOperations.TrailingZeroCount(mask); + int remapIndex = AllocateAndMarkTempGprRegister(); + + map[index] = remapIndex; + _tempGprsMask |= 1u << remapIndex; + + mask &= ~(1u << index); + } + } + + public int RemapReservedGprRegister(int index) + { + return _registerMap[index]; + } + + private int AllocateAndMarkTempGprRegister() + { + int index = AllocateTempGprRegister(); + _tempGprsMask |= 1u << index; + + return index; + } + + private int AllocateAndMarkTempGprRegisterWithPreferencing() + { + int index = AllocateTempRegisterWithPreferencing(); + _tempGprsMask |= 1u << index; + + return index; + } + + public int AllocateTempGprRegister() + { + return AllocateTempRegister(ref _gprMask); + } + + public void FreeTempGprRegister(int index) + { + FreeTempRegister(ref _gprMask, index); + } + + private int AllocateTempRegisterWithPreferencing() + { + int firstCalleeSaved = BitOperations.TrailingZeroCount(~_gprMask & AbiConstants.GprCalleeSavedRegsMask); + if (firstCalleeSaved < 32) + { + uint regMask = 1u << firstCalleeSaved; + if ((regMask & RegisterUtils.ReservedRegsMask) == 0) + { + _gprMask |= regMask; + + return firstCalleeSaved; + } + } + + return AllocateTempRegister(ref _gprMask); + } + + private static int AllocateTempRegister(ref uint mask) + { + int index = BitOperations.TrailingZeroCount(~(mask | RegisterUtils.ReservedRegsMask)); + if (index == sizeof(uint) * 8) + { + throw new InvalidOperationException("No free registers."); + } + + mask |= 1u << index; + + return index; + } + + private static void FreeTempRegister(ref uint mask, int index) + { + mask &= ~(1u << index); + } + } +} diff --git a/src/Ryujinx.Cpu/LightningJit/Arm64/RegisterUtils.cs b/src/Ryujinx.Cpu/LightningJit/Arm64/RegisterUtils.cs new file mode 100644 index 00000000..eb3fc229 --- /dev/null +++ b/src/Ryujinx.Cpu/LightningJit/Arm64/RegisterUtils.cs @@ -0,0 +1,495 @@ +using System.Diagnostics; + +namespace Ryujinx.Cpu.LightningJit.Arm64 +{ + static class RegisterUtils + { + private const int RdRtBit = 0; + private const int RnBit = 5; + private const int RmRsBit = 16; + private const int RaRt2Bit = 10; + + // Some of those register have specific roles and can't be used as general purpose registers. + // X18 - Reserved for platform specific usage. + // X29 - Frame pointer. + // X30 - Return address. + // X31 - Not an actual register, in some cases maps to SP, and in others to ZR. + public const uint ReservedRegsMask = (1u << 18) | (1u << 29) | (1u << 30) | (1u << 31); + + public const int LrIndex = 30; + public const int SpIndex = 31; + public const int ZrIndex = 31; + public const int SpecialZrIndex = 32; + + public static uint RemapRegisters(RegisterAllocator regAlloc, InstFlags flags, uint encoding) + { + if (flags.HasFlag(InstFlags.Rd) && (!flags.HasFlag(InstFlags.FpSimd) || IsFpToGpr(flags, encoding))) + { + encoding = ReplaceGprRegister(regAlloc, encoding, RdRtBit, flags.HasFlag(InstFlags.RdSP)); + } + + if (flags.HasFlag(InstFlags.Rn) && (!flags.HasFlag(InstFlags.FpSimd) || IsFpFromGpr(flags, encoding) || flags.HasFlag(InstFlags.Memory))) + { + encoding = ReplaceGprRegister(regAlloc, encoding, RnBit, flags.HasFlag(InstFlags.RnSP)); + } + + if (!flags.HasFlag(InstFlags.FpSimd)) + { + if (flags.HasFlag(InstFlags.Rm) || flags.HasFlag(InstFlags.Rs)) + { + encoding = ReplaceGprRegister(regAlloc, encoding, RmRsBit); + } + + if (flags.HasFlag(InstFlags.Ra) || flags.HasFlag(InstFlags.Rt2)) + { + encoding = ReplaceGprRegister(regAlloc, encoding, RaRt2Bit); + } + + if (flags.HasFlag(InstFlags.Rt)) + { + encoding = ReplaceGprRegister(regAlloc, encoding, RdRtBit); + } + } + else if (flags.HasFlag(InstFlags.Rm) && flags.HasFlag(InstFlags.Memory)) + { + encoding = ReplaceGprRegister(regAlloc, encoding, RmRsBit); + } + + return encoding; + } + + public static uint ReplaceRt(uint encoding, int newIndex) + { + return ReplaceRegister(encoding, newIndex, RdRtBit); + } + + public static uint ReplaceRn(uint encoding, int newIndex) + { + return ReplaceRegister(encoding, newIndex, RnBit); + } + + private static uint ReplaceRegister(uint encoding, int newIndex, int bit) + { + encoding &= ~(0x1fu << bit); + encoding |= (uint)newIndex << bit; + + return encoding; + } + + private static uint ReplaceGprRegister(RegisterAllocator regAlloc, uint encoding, int bit, bool hasSP = false) + { + int oldIndex = (int)(encoding >> bit) & 0x1f; + if (oldIndex == ZrIndex && !hasSP) + { + return encoding; + } + + int newIndex = regAlloc.RemapReservedGprRegister(oldIndex); + + encoding &= ~(0x1fu << bit); + encoding |= (uint)newIndex << bit; + + return encoding; + } + + public static (uint, uint) PopulateReadMasks(InstName name, InstFlags flags, uint encoding) + { + uint gprMask = 0; + uint fpSimdMask = 0; + + if (flags.HasFlag(InstFlags.FpSimd)) + { + if (flags.HasFlag(InstFlags.Rd) && flags.HasFlag(InstFlags.ReadRd)) + { + uint mask = MaskFromIndex(ExtractRd(flags, encoding)); + + if (IsFpToGpr(flags, encoding)) + { + gprMask |= mask; + } + else + { + fpSimdMask |= mask; + } + } + + if (flags.HasFlag(InstFlags.Rn)) + { + uint mask = MaskFromIndex(ExtractRn(flags, encoding)); + + if (flags.HasFlag(InstFlags.RnSeq)) + { + int count = GetRnSequenceCount(encoding); + + for (int index = 0; index < count; index++, mask <<= 1) + { + fpSimdMask |= mask; + } + } + else if (IsFpFromGpr(flags, encoding) || flags.HasFlag(InstFlags.Memory)) + { + gprMask |= mask; + } + else + { + fpSimdMask |= mask; + } + } + + if (flags.HasFlag(InstFlags.Rm)) + { + uint mask = MaskFromIndex(ExtractRm(flags, encoding)); + + if (flags.HasFlag(InstFlags.Memory)) + { + gprMask |= mask; + } + else + { + fpSimdMask |= mask; + } + } + + if (flags.HasFlag(InstFlags.Ra)) + { + fpSimdMask |= MaskFromIndex(ExtractRa(flags, encoding)); + } + + if (flags.HasFlag(InstFlags.ReadRt)) + { + if (flags.HasFlag(InstFlags.Rt)) + { + uint mask = MaskFromIndex(ExtractRt(flags, encoding)); + + if (flags.HasFlag(InstFlags.RtSeq)) + { + int count = GetRtSequenceCount(name, encoding); + + for (int index = 0; index < count; index++, mask <<= 1) + { + fpSimdMask |= mask; + } + } + else + { + fpSimdMask |= mask; + } + } + + if (flags.HasFlag(InstFlags.Rt2)) + { + fpSimdMask |= MaskFromIndex(ExtractRt2(flags, encoding)); + } + } + } + else + { + if (flags.HasFlag(InstFlags.Rd) && flags.HasFlag(InstFlags.ReadRd)) + { + gprMask |= MaskFromIndex(ExtractRd(flags, encoding)); + } + + if (flags.HasFlag(InstFlags.Rn)) + { + gprMask |= MaskFromIndex(ExtractRn(flags, encoding)); + } + + if (flags.HasFlag(InstFlags.Rm)) + { + gprMask |= MaskFromIndex(ExtractRm(flags, encoding)); + } + + if (flags.HasFlag(InstFlags.Ra)) + { + gprMask |= MaskFromIndex(ExtractRa(flags, encoding)); + } + + if (flags.HasFlag(InstFlags.ReadRt)) + { + if (flags.HasFlag(InstFlags.Rt)) + { + gprMask |= MaskFromIndex(ExtractRt(flags, encoding)); + } + + if (flags.HasFlag(InstFlags.Rt2)) + { + gprMask |= MaskFromIndex(ExtractRt2(flags, encoding)); + } + } + } + + return (gprMask, fpSimdMask); + } + + public static (uint, uint) PopulateWriteMasks(InstName name, InstFlags flags, uint encoding) + { + uint gprMask = 0; + uint fpSimdMask = 0; + + if (flags.HasFlag(InstFlags.MemWBack)) + { + gprMask |= MaskFromIndex(ExtractRn(flags, encoding)); + } + + if (flags.HasFlag(InstFlags.FpSimd)) + { + if (flags.HasFlag(InstFlags.Rd)) + { + uint mask = MaskFromIndex(ExtractRd(flags, encoding)); + + if (IsFpToGpr(flags, encoding)) + { + gprMask |= mask; + } + else + { + fpSimdMask |= mask; + } + } + + if (!flags.HasFlag(InstFlags.ReadRt)) + { + if (flags.HasFlag(InstFlags.Rt)) + { + uint mask = MaskFromIndex(ExtractRt(flags, encoding)); + + if (flags.HasFlag(InstFlags.RtSeq)) + { + int count = GetRtSequenceCount(name, encoding); + + for (int index = 0; index < count; index++, mask <<= 1) + { + fpSimdMask |= mask; + } + } + else + { + fpSimdMask |= mask; + } + } + + if (flags.HasFlag(InstFlags.Rt2)) + { + fpSimdMask |= MaskFromIndex(ExtractRt2(flags, encoding)); + } + } + } + else + { + if (flags.HasFlag(InstFlags.Rd)) + { + gprMask |= MaskFromIndex(ExtractRd(flags, encoding)); + } + + if (!flags.HasFlag(InstFlags.ReadRt)) + { + if (flags.HasFlag(InstFlags.Rt)) + { + gprMask |= MaskFromIndex(ExtractRt(flags, encoding)); + } + + if (flags.HasFlag(InstFlags.Rt2)) + { + gprMask |= MaskFromIndex(ExtractRt2(flags, encoding)); + } + } + + if (flags.HasFlag(InstFlags.Rs)) + { + gprMask |= MaskFromIndex(ExtractRs(flags, encoding)); + } + } + + return (gprMask, fpSimdMask); + } + + private static uint MaskFromIndex(int index) + { + if (index < SpecialZrIndex) + { + return 1u << index; + } + + return 0u; + } + + private static bool IsFpFromGpr(InstFlags flags, uint encoding) + { + InstFlags bothFlags = InstFlags.FpSimdFromGpr | InstFlags.FpSimdToGpr; + + if ((flags & bothFlags) == bothFlags) // FMOV (general) + { + return (encoding & (1u << 16)) != 0; + } + + return flags.HasFlag(InstFlags.FpSimdFromGpr); + } + + private static bool IsFpToGpr(InstFlags flags, uint encoding) + { + InstFlags bothFlags = InstFlags.FpSimdFromGpr | InstFlags.FpSimdToGpr; + + if ((flags & bothFlags) == bothFlags) // FMOV (general) + { + return (encoding & (1u << 16)) == 0; + } + + return flags.HasFlag(InstFlags.FpSimdToGpr); + } + + private static int GetRtSequenceCount(InstName name, uint encoding) + { + switch (name) + { + case InstName.Ld1AdvsimdMultAsNoPostIndex: + case InstName.Ld1AdvsimdMultAsPostIndex: + case InstName.St1AdvsimdMultAsNoPostIndex: + case InstName.St1AdvsimdMultAsPostIndex: + return ((encoding >> 12) & 0xf) switch + { + 0b0000 => 4, + 0b0010 => 4, + 0b0100 => 3, + 0b0110 => 3, + 0b0111 => 1, + 0b1000 => 2, + 0b1010 => 2, + _ => 1, + }; + case InstName.Ld1rAdvsimdAsNoPostIndex: + case InstName.Ld1rAdvsimdAsPostIndex: + case InstName.Ld1AdvsimdSnglAsNoPostIndex: + case InstName.Ld1AdvsimdSnglAsPostIndex: + case InstName.St1AdvsimdSnglAsNoPostIndex: + case InstName.St1AdvsimdSnglAsPostIndex: + return 1; + case InstName.Ld2rAdvsimdAsNoPostIndex: + case InstName.Ld2rAdvsimdAsPostIndex: + case InstName.Ld2AdvsimdMultAsNoPostIndex: + case InstName.Ld2AdvsimdMultAsPostIndex: + case InstName.Ld2AdvsimdSnglAsNoPostIndex: + case InstName.Ld2AdvsimdSnglAsPostIndex: + case InstName.St2AdvsimdMultAsNoPostIndex: + case InstName.St2AdvsimdMultAsPostIndex: + case InstName.St2AdvsimdSnglAsNoPostIndex: + case InstName.St2AdvsimdSnglAsPostIndex: + return 2; + case InstName.Ld3rAdvsimdAsNoPostIndex: + case InstName.Ld3rAdvsimdAsPostIndex: + case InstName.Ld3AdvsimdMultAsNoPostIndex: + case InstName.Ld3AdvsimdMultAsPostIndex: + case InstName.Ld3AdvsimdSnglAsNoPostIndex: + case InstName.Ld3AdvsimdSnglAsPostIndex: + case InstName.St3AdvsimdMultAsNoPostIndex: + case InstName.St3AdvsimdMultAsPostIndex: + case InstName.St3AdvsimdSnglAsNoPostIndex: + case InstName.St3AdvsimdSnglAsPostIndex: + return 3; + case InstName.Ld4rAdvsimdAsNoPostIndex: + case InstName.Ld4rAdvsimdAsPostIndex: + case InstName.Ld4AdvsimdMultAsNoPostIndex: + case InstName.Ld4AdvsimdMultAsPostIndex: + case InstName.Ld4AdvsimdSnglAsNoPostIndex: + case InstName.Ld4AdvsimdSnglAsPostIndex: + case InstName.St4AdvsimdMultAsNoPostIndex: + case InstName.St4AdvsimdMultAsPostIndex: + case InstName.St4AdvsimdSnglAsNoPostIndex: + case InstName.St4AdvsimdSnglAsPostIndex: + return 4; + } + + return 1; + } + + private static int GetRnSequenceCount(uint encoding) + { + return ((int)(encoding >> 13) & 3) + 1; + } + + public static int ExtractRd(InstFlags flags, uint encoding) + { + Debug.Assert(flags.HasFlag(InstFlags.Rd)); + int index = (int)(encoding >> RdRtBit) & 0x1f; + + if (!flags.HasFlag(InstFlags.RdSP) && index == ZrIndex) + { + return SpecialZrIndex; + } + + return index; + } + + public static int ExtractRn(uint encoding) + { + return (int)(encoding >> RnBit) & 0x1f; + } + + public static int ExtractRn(InstFlags flags, uint encoding) + { + Debug.Assert(flags.HasFlag(InstFlags.Rn)); + int index = ExtractRn(encoding); + + if (!flags.HasFlag(InstFlags.RnSP) && index == ZrIndex) + { + return SpecialZrIndex; + } + + return index; + } + + public static int ExtractRm(uint encoding) + { + return (int)(encoding >> RmRsBit) & 0x1f; + } + + public static int ExtractRm(InstFlags flags, uint encoding) + { + Debug.Assert(flags.HasFlag(InstFlags.Rm)); + int index = ExtractRm(encoding); + + return index == ZrIndex ? SpecialZrIndex : index; + } + + public static int ExtractRs(uint encoding) + { + return (int)(encoding >> RmRsBit) & 0x1f; + } + + public static int ExtractRs(InstFlags flags, uint encoding) + { + Debug.Assert(flags.HasFlag(InstFlags.Rs)); + int index = ExtractRs(encoding); + + return index == ZrIndex ? SpecialZrIndex : index; + } + + public static int ExtractRa(InstFlags flags, uint encoding) + { + Debug.Assert(flags.HasFlag(InstFlags.Ra)); + int index = (int)(encoding >> RaRt2Bit) & 0x1f; + + return index == ZrIndex ? SpecialZrIndex : index; + } + + public static int ExtractRt(uint encoding) + { + return (int)(encoding >> RdRtBit) & 0x1f; + } + + public static int ExtractRt(InstFlags flags, uint encoding) + { + Debug.Assert(flags.HasFlag(InstFlags.Rt)); + int index = ExtractRt(encoding); + + return index == ZrIndex ? SpecialZrIndex : index; + } + + public static int ExtractRt2(InstFlags flags, uint encoding) + { + Debug.Assert(flags.HasFlag(InstFlags.Rt2)); + int index = (int)(encoding >> RaRt2Bit) & 0x1f; + + return index == ZrIndex ? SpecialZrIndex : index; + } + } +} diff --git a/src/Ryujinx.Cpu/LightningJit/Arm64/Target/Arm64/Compiler.cs b/src/Ryujinx.Cpu/LightningJit/Arm64/Target/Arm64/Compiler.cs new file mode 100644 index 00000000..7ef3bf49 --- /dev/null +++ b/src/Ryujinx.Cpu/LightningJit/Arm64/Target/Arm64/Compiler.cs @@ -0,0 +1,743 @@ +using ARMeilleure.Common; +using ARMeilleure.Memory; +using Ryujinx.Cpu.LightningJit.CodeGen; +using Ryujinx.Cpu.LightningJit.CodeGen.Arm64; +using Ryujinx.Cpu.LightningJit.Graph; +using System; +using System.Collections.Generic; +using System.Diagnostics; +using System.Numerics; + +namespace Ryujinx.Cpu.LightningJit.Arm64.Target.Arm64 +{ + static class Compiler + { + private const int Encodable26BitsOffsetLimit = 0x2000000; + + private readonly struct Context + { + public readonly CodeWriter Writer; + public readonly RegisterAllocator RegisterAllocator; + public readonly TailMerger TailMerger; + public readonly AddressTable<ulong> FuncTable; + public readonly IntPtr DispatchStubPointer; + + private readonly MultiBlock _multiBlock; + private readonly RegisterSaveRestore _registerSaveRestore; + private readonly IntPtr _pageTablePointer; + + public Context( + CodeWriter writer, + RegisterAllocator registerAllocator, + TailMerger tailMerger, + RegisterSaveRestore registerSaveRestore, + MultiBlock multiBlock, + AddressTable<ulong> funcTable, + IntPtr dispatchStubPointer, + IntPtr pageTablePointer) + { + Writer = writer; + RegisterAllocator = registerAllocator; + TailMerger = tailMerger; + _registerSaveRestore = registerSaveRestore; + _multiBlock = multiBlock; + FuncTable = funcTable; + DispatchStubPointer = dispatchStubPointer; + _pageTablePointer = pageTablePointer; + } + + public readonly int GetLrRegisterIndex() + { + return RemapGprRegister(RegisterUtils.LrIndex); + } + + public readonly int RemapGprRegister(int index) + { + return RegisterAllocator.RemapReservedGprRegister(index); + } + + public readonly int GetReservedStackOffset() + { + return _registerSaveRestore.GetReservedStackOffset(); + } + + public readonly void WritePrologue() + { + Assembler asm = new(Writer); + + _registerSaveRestore.WritePrologue(ref asm); + + // If needed, set up the fixed registers with the pointers we will use. + // First one is the context pointer (passed as first argument), + // second one is the page table or address space base, it is at a fixed memory location and considered constant. + + if (RegisterAllocator.FixedContextRegister != 0) + { + asm.Mov(Register(RegisterAllocator.FixedContextRegister), Register(0)); + } + + if (_multiBlock.HasMemoryInstruction) + { + asm.Mov(Register(RegisterAllocator.FixedPageTableRegister), (ulong)_pageTablePointer); + } + + // This assumes that the block with the index 0 is always the entry block. + LoadFromContext(ref asm, _multiBlock.ReadMasks[0]); + } + + public readonly void WriteEpilogueWithoutContext() + { + Assembler asm = new(Writer); + + _registerSaveRestore.WriteEpilogue(ref asm); + } + + public void LoadFromContextAfterCall(int blockIndex) + { + Block block = _multiBlock.Blocks[blockIndex]; + + if (block.SuccessorsCount != 0) + { + Assembler asm = new(Writer); + + RegisterMask readMask = _multiBlock.ReadMasks[block.GetSuccessor(0).Index]; + + for (int sIndex = 1; sIndex < block.SuccessorsCount; sIndex++) + { + IBlock successor = block.GetSuccessor(sIndex); + + readMask |= _multiBlock.ReadMasks[successor.Index]; + } + + LoadFromContext(ref asm, readMask); + } + } + + private void LoadFromContext(ref Assembler asm, RegisterMask readMask) + { + LoadGprFromContext(ref asm, readMask.GprMask, NativeContextOffsets.GprBaseOffset); + LoadFpSimdFromContext(ref asm, readMask.FpSimdMask, NativeContextOffsets.FpSimdBaseOffset); + LoadPStateFromContext(ref asm, readMask.PStateMask, NativeContextOffsets.FlagsBaseOffset); + } + + public void StoreToContextBeforeCall(int blockIndex, ulong? newLrValue = null) + { + Assembler asm = new(Writer); + + StoreToContext(ref asm, _multiBlock.WriteMasks[blockIndex], newLrValue); + } + + private void StoreToContext(ref Assembler asm, RegisterMask writeMask, ulong? newLrValue) + { + StoreGprToContext(ref asm, writeMask.GprMask, NativeContextOffsets.GprBaseOffset, newLrValue); + StoreFpSimdToContext(ref asm, writeMask.FpSimdMask, NativeContextOffsets.FpSimdBaseOffset); + StorePStateToContext(ref asm, writeMask.PStateMask, NativeContextOffsets.FlagsBaseOffset); + } + + private void LoadGprFromContext(ref Assembler asm, uint mask, int baseOffset) + { + Operand contextPtr = Register(RegisterAllocator.FixedContextRegister); + + while (mask != 0) + { + int reg = BitOperations.TrailingZeroCount(mask); + int offset = baseOffset + reg * 8; + + if (reg < 31 && (mask & (2u << reg)) != 0 && offset < RegisterSaveRestore.Encodable9BitsOffsetLimit) + { + mask &= ~(3u << reg); + + asm.LdpRiUn( + Register(RegisterAllocator.RemapReservedGprRegister(reg)), + Register(RegisterAllocator.RemapReservedGprRegister(reg + 1)), + contextPtr, + offset); + } + else + { + mask &= ~(1u << reg); + + asm.LdrRiUn(Register(RegisterAllocator.RemapReservedGprRegister(reg)), contextPtr, offset); + } + } + } + + private void LoadFpSimdFromContext(ref Assembler asm, uint mask, int baseOffset) + { + Operand contextPtr = Register(RegisterAllocator.FixedContextRegister); + + while (mask != 0) + { + int reg = BitOperations.TrailingZeroCount(mask); + int offset = baseOffset + reg * 16; + + mask &= ~(1u << reg); + + asm.LdrRiUn(Register(reg, OperandType.V128), contextPtr, offset); + } + } + + private void LoadPStateFromContext(ref Assembler asm, uint mask, int baseOffset) + { + if (mask == 0) + { + return; + } + + Operand contextPtr = Register(RegisterAllocator.FixedContextRegister); + + int tempRegister = RegisterAllocator.AllocateTempGprRegister(); + + Operand rt = Register(tempRegister, OperandType.I32); + + asm.LdrRiUn(rt, contextPtr, baseOffset); + asm.MsrNzcv(rt); + + RegisterAllocator.FreeTempGprRegister(tempRegister); + } + + private void StoreGprToContext(ref Assembler asm, uint mask, int baseOffset, ulong? newLrValue) + { + Operand contextPtr = Register(RegisterAllocator.FixedContextRegister); + + int tempRegister = -1; + + if (newLrValue.HasValue) + { + // This is required for BLR X30 instructions, where we need to get the target address + // before it is overwritten with the return address that the call would write there. + + tempRegister = RegisterAllocator.AllocateTempGprRegister(); + + asm.Mov(Register(tempRegister), newLrValue.Value); + } + + while (mask != 0) + { + int reg = BitOperations.TrailingZeroCount(mask); + int offset = baseOffset + reg * 8; + + if (reg < 31 && (mask & (2u << reg)) != 0 && offset < RegisterSaveRestore.Encodable9BitsOffsetLimit) + { + mask &= ~(3u << reg); + + asm.StpRiUn( + Register(RemapReservedGprRegister(reg, tempRegister)), + Register(RemapReservedGprRegister(reg + 1, tempRegister)), + contextPtr, + offset); + } + else + { + mask &= ~(1u << reg); + + asm.StrRiUn(Register(RemapReservedGprRegister(reg, tempRegister)), contextPtr, offset); + } + } + + if (tempRegister >= 0) + { + RegisterAllocator.FreeTempGprRegister(tempRegister); + } + } + + private int RemapReservedGprRegister(int index, int tempRegister) + { + if (tempRegister >= 0 && index == RegisterUtils.LrIndex) + { + return tempRegister; + } + + return RegisterAllocator.RemapReservedGprRegister(index); + } + + private void StoreFpSimdToContext(ref Assembler asm, uint mask, int baseOffset) + { + Operand contextPtr = Register(RegisterAllocator.FixedContextRegister); + + while (mask != 0) + { + int reg = BitOperations.TrailingZeroCount(mask); + int offset = baseOffset + reg * 16; + + mask &= ~(1u << reg); + + asm.StrRiUn(Register(reg, OperandType.V128), contextPtr, offset); + } + } + + private void StorePStateToContext(ref Assembler asm, uint mask, int baseOffset) + { + if (mask == 0) + { + return; + } + + Operand contextPtr = Register(RegisterAllocator.FixedContextRegister); + + int tempRegister = RegisterAllocator.AllocateTempGprRegister(); + + Operand rt = Register(tempRegister, OperandType.I32); + + asm.MrsNzcv(rt); + asm.StrRiUn(rt, contextPtr, baseOffset); + + RegisterAllocator.FreeTempGprRegister(tempRegister); + } + } + + private readonly struct PendingBranch + { + public readonly int BlockIndex; + public readonly ulong Pc; + public readonly InstName Name; + public readonly uint Encoding; + public readonly int WriterPointer; + + public PendingBranch(int blockIndex, ulong pc, InstName name, uint encoding, int writerPointer) + { + BlockIndex = blockIndex; + Pc = pc; + Name = name; + Encoding = encoding; + WriterPointer = writerPointer; + } + } + + public static CompiledFunction Compile(CpuPreset cpuPreset, IMemoryManager memoryManager, ulong address, AddressTable<ulong> funcTable, IntPtr dispatchStubPtr) + { + MultiBlock multiBlock = Decoder.DecodeMulti(cpuPreset, memoryManager, address); + + Dictionary<ulong, int> targets = new(); + List<PendingBranch> pendingBranches = new(); + + uint gprUseMask = multiBlock.GlobalUseMask.GprMask; + uint fpSimdUseMask = multiBlock.GlobalUseMask.FpSimdMask; + uint pStateUseMask = multiBlock.GlobalUseMask.PStateMask; + + CodeWriter writer = new(); + RegisterAllocator regAlloc = new(gprUseMask, fpSimdUseMask, pStateUseMask, multiBlock.HasHostCall); + RegisterSaveRestore rsr = new( + regAlloc.AllGprMask & AbiConstants.GprCalleeSavedRegsMask, + regAlloc.AllFpSimdMask & AbiConstants.FpSimdCalleeSavedRegsMask, + OperandType.FP64, + multiBlock.HasHostCall, + multiBlock.HasHostCall ? CalculateStackSizeForCallSpill(regAlloc.AllGprMask, regAlloc.AllFpSimdMask, regAlloc.AllPStateMask) : 0); + + TailMerger tailMerger = new(); + + Context context = new(writer, regAlloc, tailMerger, rsr, multiBlock, funcTable, dispatchStubPtr, memoryManager.PageTablePointer); + + context.WritePrologue(); + + ulong pc = address; + + for (int blockIndex = 0; blockIndex < multiBlock.Blocks.Count; blockIndex++) + { + Block block = multiBlock.Blocks[blockIndex]; + + Debug.Assert(block.Address == pc); + + targets.Add(pc, writer.InstructionPointer); + + int instCount = block.EndsWithBranch ? block.Instructions.Count - 1 : block.Instructions.Count; + + for (int index = 0; index < instCount; index++) + { + InstInfo instInfo = block.Instructions[index]; + + uint encoding = RegisterUtils.RemapRegisters(regAlloc, instInfo.Flags, instInfo.Encoding); + + if (instInfo.AddressForm != AddressForm.None) + { + InstEmitMemory.RewriteInstruction( + memoryManager.AddressSpaceBits, + memoryManager.Type, + writer, + regAlloc, + instInfo.Name, + instInfo.Flags, + instInfo.AddressForm, + pc, + encoding); + } + else if (instInfo.Name == InstName.Sys) + { + InstEmitMemory.RewriteSysInstruction(memoryManager.AddressSpaceBits, memoryManager.Type, writer, regAlloc, encoding); + } + else if (instInfo.Name.IsSystem()) + { + bool needsContextStoreLoad = InstEmitSystem.NeedsContextStoreLoad(instInfo.Name); + + if (needsContextStoreLoad) + { + context.StoreToContextBeforeCall(blockIndex); + } + + InstEmitSystem.RewriteInstruction(writer, regAlloc, tailMerger, instInfo.Name, pc, encoding, rsr.GetReservedStackOffset()); + + if (needsContextStoreLoad) + { + context.LoadFromContextAfterCall(blockIndex); + } + } + else + { + writer.WriteInstruction(encoding); + } + + pc += 4UL; + } + + if (block.IsLoopEnd) + { + // If this is a loop, the code might run for a long time uninterrupted. + // We insert a "sync point" here to ensure the loop can be interrupted if needed. + + InstEmitSystem.WriteSyncPoint(writer, context.RegisterAllocator, tailMerger, context.GetReservedStackOffset()); + } + + if (blockIndex < multiBlock.Blocks.Count - 1) + { + InstInfo lastInstructionInfo = block.Instructions[^1]; + InstName lastInstructionName = lastInstructionInfo.Name; + InstFlags lastInstructionFlags = lastInstructionInfo.Flags; + uint lastInstructionEncoding = lastInstructionInfo.Encoding; + + lastInstructionEncoding = RegisterUtils.RemapRegisters(regAlloc, lastInstructionFlags, lastInstructionEncoding); + + if (lastInstructionName.IsCall()) + { + context.StoreToContextBeforeCall(blockIndex, pc + 4UL); + + InstEmitSystem.RewriteCallInstruction( + writer, + regAlloc, + tailMerger, + context.WriteEpilogueWithoutContext, + funcTable, + dispatchStubPtr, + lastInstructionName, + pc, + lastInstructionEncoding, + context.GetReservedStackOffset()); + + context.LoadFromContextAfterCall(blockIndex); + + pc += 4UL; + } + else if (lastInstructionName == InstName.Ret) + { + RewriteBranchInstruction(context, blockIndex, lastInstructionName, pc, lastInstructionEncoding); + + pc += 4UL; + } + else if (block.EndsWithBranch) + { + pendingBranches.Add(new(blockIndex, pc, lastInstructionName, lastInstructionEncoding, writer.InstructionPointer)); + writer.WriteInstruction(0u); // Placeholder. + + pc += 4UL; + } + } + } + + int lastBlockIndex = multiBlock.Blocks[^1].Index; + + if (multiBlock.IsTruncated) + { + Assembler asm = new(writer); + + WriteTailCallConstant(context, ref asm, lastBlockIndex, pc); + } + else + { + InstInfo lastInstructionInfo = multiBlock.Blocks[^1].Instructions[^1]; + InstName lastInstructionName = lastInstructionInfo.Name; + InstFlags lastInstructionFlags = lastInstructionInfo.Flags; + uint lastInstructionEncoding = lastInstructionInfo.Encoding; + + lastInstructionEncoding = RegisterUtils.RemapRegisters(regAlloc, lastInstructionFlags, lastInstructionEncoding); + + RewriteBranchInstruction(context, lastBlockIndex, lastInstructionName, pc, lastInstructionEncoding); + + pc += 4; + } + + foreach (PendingBranch pendingBranch in pendingBranches) + { + RewriteBranchInstructionWithTarget( + context, + pendingBranch.BlockIndex, + pendingBranch.Name, + pendingBranch.Pc, + pendingBranch.Encoding, + pendingBranch.WriterPointer, + targets); + } + + tailMerger.WriteReturn(writer, context.WriteEpilogueWithoutContext); + + return new(writer.AsByteSpan(), (int)(pc - address)); + } + + private static int CalculateStackSizeForCallSpill(uint gprUseMask, uint fpSimdUseMask, uint pStateUseMask) + { + // Note that we don't discard callee saved FP/SIMD register because only the lower 64 bits is callee saved, + // so if the function is using the full register, that won't be enough. + // We could do better, but it's likely not worth it since this case happens very rarely in practice. + + return BitOperations.PopCount(gprUseMask & ~AbiConstants.GprCalleeSavedRegsMask) * 8 + + BitOperations.PopCount(fpSimdUseMask) * 16 + + (pStateUseMask != 0 ? 8 : 0); + } + + private static void RewriteBranchInstruction(in Context context, int blockIndex, InstName name, ulong pc, uint encoding) + { + CodeWriter writer = context.Writer; + Assembler asm = new(writer); + + int originalOffset; + ulong nextAddress = pc + 4UL; + ulong targetAddress; + + switch (name) + { + case InstName.BUncond: + originalOffset = ImmUtils.ExtractSImm26Times4(encoding); + targetAddress = pc + (ulong)originalOffset; + + WriteTailCallConstant(context, ref asm, blockIndex, targetAddress); + break; + + case InstName.Bl: + case InstName.Blr: + case InstName.Br: + if (name == InstName.Bl) + { + asm.Mov(Register(context.GetLrRegisterIndex()), nextAddress); + + int imm = ImmUtils.ExtractSImm26Times4(encoding); + + WriteTailCallConstant(context, ref asm, blockIndex, pc + (ulong)imm); + } + else + { + bool isCall = name == InstName.Blr; + if (isCall) + { + context.StoreToContextBeforeCall(blockIndex, nextAddress); + } + else + { + context.StoreToContextBeforeCall(blockIndex); + } + + InstEmitSystem.RewriteCallInstruction( + context.Writer, + context.RegisterAllocator, + context.TailMerger, + context.WriteEpilogueWithoutContext, + context.FuncTable, + context.DispatchStubPointer, + name, + pc, + encoding, + context.GetReservedStackOffset(), + isTail: true); + } + break; + + case InstName.Ret: + int rnIndex = RegisterUtils.ExtractRn(encoding); + if (rnIndex == RegisterUtils.ZrIndex) + { + WriteTailCallConstant(context, ref asm, blockIndex, 0UL); + } + else + { + rnIndex = context.RemapGprRegister(rnIndex); + context.StoreToContextBeforeCall(blockIndex); + + if (rnIndex != 0) + { + asm.Mov(Register(0), Register(rnIndex)); + } + + context.TailMerger.AddUnconditionalReturn(writer, asm); + } + break; + + case InstName.BCond: + case InstName.Cbnz: + case InstName.Cbz: + case InstName.Tbnz: + case InstName.Tbz: + uint branchMask; + + if (name == InstName.Tbnz || name == InstName.Tbz) + { + originalOffset = ImmUtils.ExtractSImm14Times4(encoding); + branchMask = 0x3fff; + } + else + { + originalOffset = ImmUtils.ExtractSImm19Times4(encoding); + branchMask = 0x7ffff; + } + + targetAddress = pc + (ulong)originalOffset; + + int branchIndex = writer.InstructionPointer; + + writer.WriteInstruction(0u); // Reserved for branch. + WriteTailCallConstant(context, ref asm, blockIndex, nextAddress); + + int targetIndex = writer.InstructionPointer; + + writer.WriteInstructionAt(branchIndex, (encoding & ~(branchMask << 5)) | (uint)(((targetIndex - branchIndex) & branchMask) << 5)); + WriteTailCallConstant(context, ref asm, blockIndex, targetAddress); + break; + + default: + Debug.Fail($"Unknown branch instruction \"{name}\"."); + break; + } + } + + private static void RewriteBranchInstructionWithTarget( + in Context context, + int blockIndex, + InstName name, + ulong pc, + uint encoding, + int branchIndex, + Dictionary<ulong, int> targets) + { + CodeWriter writer = context.Writer; + Assembler asm = new(writer); + + int delta; + int targetIndex; + int originalOffset; + ulong targetAddress; + + switch (name) + { + case InstName.BUncond: + originalOffset = ImmUtils.ExtractSImm26Times4(encoding); + targetAddress = pc + (ulong)originalOffset; + + if (targets.TryGetValue(targetAddress, out targetIndex)) + { + delta = targetIndex - branchIndex; + + if (delta >= -Encodable26BitsOffsetLimit && delta < Encodable26BitsOffsetLimit) + { + writer.WriteInstructionAt(branchIndex, (encoding & ~0x3ffffffu) | (uint)(delta & 0x3ffffff)); + break; + } + } + + targetIndex = writer.InstructionPointer; + delta = targetIndex - branchIndex; + + writer.WriteInstructionAt(branchIndex, (encoding & ~0x3ffffffu) | (uint)(delta & 0x3ffffff)); + WriteTailCallConstant(context, ref asm, blockIndex, targetAddress); + break; + + case InstName.BCond: + case InstName.Cbnz: + case InstName.Cbz: + case InstName.Tbnz: + case InstName.Tbz: + uint branchMask; + + if (name == InstName.Tbnz || name == InstName.Tbz) + { + originalOffset = ImmUtils.ExtractSImm14Times4(encoding); + branchMask = 0x3fff; + } + else + { + originalOffset = ImmUtils.ExtractSImm19Times4(encoding); + branchMask = 0x7ffff; + } + + int branchMax = (int)(branchMask + 1) / 2; + + targetAddress = pc + (ulong)originalOffset; + + if (targets.TryGetValue(targetAddress, out targetIndex)) + { + delta = targetIndex - branchIndex; + + if (delta >= -branchMax && delta < branchMax) + { + writer.WriteInstructionAt(branchIndex, (encoding & ~(branchMask << 5)) | (uint)((delta & branchMask) << 5)); + break; + } + } + + targetIndex = writer.InstructionPointer; + delta = targetIndex - branchIndex; + + if (delta >= -branchMax && delta < branchMax) + { + writer.WriteInstructionAt(branchIndex, (encoding & ~(branchMask << 5)) | (uint)((delta & branchMask) << 5)); + WriteTailCallConstant(context, ref asm, blockIndex, targetAddress); + } + else + { + // If the branch target is too far away, we use a regular unconditional branch + // instruction instead which has a much higher range. + // We branch directly to the end of the function, where we put the conditional branch, + // and then branch back to the next instruction or return the branch target depending + // on the branch being taken or not. + + uint branchInst = 0x14000000u | ((uint)delta & 0x3ffffff); + Debug.Assert(ImmUtils.ExtractSImm26Times4(branchInst) == delta * 4); + + writer.WriteInstructionAt(branchIndex, branchInst); + + int movedBranchIndex = writer.InstructionPointer; + + writer.WriteInstruction(0u); // Placeholder + asm.B((branchIndex + 1 - writer.InstructionPointer) * 4); + + delta = writer.InstructionPointer - movedBranchIndex; + + writer.WriteInstructionAt(movedBranchIndex, (encoding & ~(branchMask << 5)) | (uint)((delta & branchMask) << 5)); + WriteTailCallConstant(context, ref asm, blockIndex, targetAddress); + } + break; + + default: + Debug.Fail($"Unknown branch instruction \"{name}\"."); + break; + } + } + + private static void WriteTailCallConstant(in Context context, ref Assembler asm, int blockIndex, ulong address) + { + context.StoreToContextBeforeCall(blockIndex); + InstEmitSystem.WriteCallWithGuestAddress( + context.Writer, + ref asm, + context.RegisterAllocator, + context.TailMerger, + context.WriteEpilogueWithoutContext, + context.FuncTable, + context.DispatchStubPointer, + context.GetReservedStackOffset(), + 0UL, + new Operand(OperandKind.Constant, OperandType.I64, address), + isTail: true); + } + + private static Operand Register(int register, OperandType type = OperandType.I64) + { + return new Operand(register, RegisterType.Integer, type); + } + } +} diff --git a/src/Ryujinx.Cpu/LightningJit/Arm64/Target/Arm64/Decoder.cs b/src/Ryujinx.Cpu/LightningJit/Arm64/Target/Arm64/Decoder.cs new file mode 100644 index 00000000..738b8a32 --- /dev/null +++ b/src/Ryujinx.Cpu/LightningJit/Arm64/Target/Arm64/Decoder.cs @@ -0,0 +1,384 @@ +using ARMeilleure.Memory; +using Ryujinx.Cpu.LightningJit.Graph; +using System.Collections.Generic; +using System.Diagnostics; +using System.Numerics; + +namespace Ryujinx.Cpu.LightningJit.Arm64.Target.Arm64 +{ + static class Decoder + { + private const int MaxInstructionsPerBlock = 1000; + + private const uint NzcvFlags = 0xfu << 28; + private const uint CFlag = 0x1u << 29; + + public static MultiBlock DecodeMulti(CpuPreset cpuPreset, IMemoryManager memoryManager, ulong address) + { + List<Block> blocks = new(); + List<ulong> branchTargets = new(); + + RegisterMask useMask = RegisterMask.Zero; + + bool hasHostCall = false; + bool hasMemoryInstruction = false; + + while (true) + { + Block block = Decode(cpuPreset, memoryManager, address, ref useMask, ref hasHostCall, ref hasMemoryInstruction); + + if (!block.IsTruncated && TryGetBranchTarget(block, out ulong targetAddress)) + { + branchTargets.Add(targetAddress); + } + + blocks.Add(block); + + if (block.IsTruncated || !HasNextBlock(block, block.EndAddress - 4UL, branchTargets)) + { + break; + } + + address = block.EndAddress; + } + + branchTargets.Sort(); + SplitBlocks(blocks, branchTargets); + NumberAndLinkBlocks(blocks); + + return new(blocks, useMask, hasHostCall, hasMemoryInstruction); + } + + private static bool TryGetBranchTarget(Block block, out ulong targetAddress) + { + return TryGetBranchTarget(block.Instructions[^1].Name, block.EndAddress - 4UL, block.Instructions[^1].Encoding, out targetAddress); + } + + private static bool TryGetBranchTarget(InstName name, ulong pc, uint encoding, out ulong targetAddress) + { + int originalOffset; + + switch (name) + { + case InstName.BUncond: + originalOffset = ImmUtils.ExtractSImm26Times4(encoding); + targetAddress = pc + (ulong)originalOffset; + + return true; + + case InstName.BCond: + case InstName.Cbnz: + case InstName.Cbz: + case InstName.Tbnz: + case InstName.Tbz: + if (name == InstName.Tbnz || name == InstName.Tbz) + { + originalOffset = ImmUtils.ExtractSImm14Times4(encoding); + } + else + { + originalOffset = ImmUtils.ExtractSImm19Times4(encoding); + } + + targetAddress = pc + (ulong)originalOffset; + + return true; + } + + targetAddress = 0; + + return false; + } + + private static void SplitBlocks(List<Block> blocks, List<ulong> branchTargets) + { + int btIndex = 0; + + while (btIndex < branchTargets.Count) + { + for (int blockIndex = 0; blockIndex < blocks.Count && btIndex < branchTargets.Count; blockIndex++) + { + Block block = blocks[blockIndex]; + ulong currentBranchTarget = branchTargets[btIndex]; + + while (currentBranchTarget >= block.Address && currentBranchTarget < block.EndAddress) + { + if (block.Address != currentBranchTarget) + { + (Block leftBlock, Block rightBlock) = block.SplitAtAddress(currentBranchTarget); + + blocks.Insert(blockIndex, leftBlock); + blocks[blockIndex + 1] = rightBlock; + + block = leftBlock; + } + + btIndex++; + + while (btIndex < branchTargets.Count && branchTargets[btIndex] == currentBranchTarget) + { + btIndex++; + } + + if (btIndex >= branchTargets.Count) + { + break; + } + + currentBranchTarget = branchTargets[btIndex]; + } + } + + Debug.Assert(btIndex < int.MaxValue); + btIndex++; + } + } + + private static void NumberAndLinkBlocks(List<Block> blocks) + { + Dictionary<ulong, Block> blocksByAddress = new(); + + for (int blockIndex = 0; blockIndex < blocks.Count; blockIndex++) + { + Block block = blocks[blockIndex]; + + blocksByAddress.Add(block.Address, block); + } + + for (int blockIndex = 0; blockIndex < blocks.Count; blockIndex++) + { + Block block = blocks[blockIndex]; + + block.Number(blockIndex); + + if (!block.IsTruncated) + { + bool hasNext = !block.EndsWithBranch; + bool hasBranch = false; + + switch (block.Instructions[^1].Name) + { + case InstName.BUncond: + hasBranch = true; + break; + + case InstName.BCond: + case InstName.Cbnz: + case InstName.Cbz: + case InstName.Tbnz: + case InstName.Tbz: + hasNext = true; + hasBranch = true; + break; + + case InstName.Bl: + case InstName.Blr: + hasNext = true; + break; + + case InstName.Ret: + hasNext = false; + hasBranch = false; + break; + } + + if (hasNext && blocksByAddress.TryGetValue(block.EndAddress, out Block nextBlock)) + { + block.AddSuccessor(nextBlock); + nextBlock.AddPredecessor(block); + } + + if (hasBranch && + TryGetBranchTarget(block, out ulong targetAddress) && + blocksByAddress.TryGetValue(targetAddress, out Block branchBlock)) + { + block.AddSuccessor(branchBlock); + branchBlock.AddPredecessor(block); + } + } + } + } + + private static bool HasNextBlock(in Block block, ulong pc, List<ulong> branchTargets) + { + switch (block.Instructions[^1].Name) + { + case InstName.BUncond: + return branchTargets.Contains(pc + 4UL) || + (TryGetBranchTarget(block, out ulong targetAddress) && targetAddress >= pc && targetAddress < pc + 0x1000); + + case InstName.BCond: + case InstName.Bl: + case InstName.Blr: + case InstName.Cbnz: + case InstName.Cbz: + case InstName.Tbnz: + case InstName.Tbz: + return true; + + case InstName.Br: + return false; + + case InstName.Ret: + return branchTargets.Contains(pc + 4UL); + } + + return !block.EndsWithBranch; + } + + private static Block Decode( + CpuPreset cpuPreset, + IMemoryManager memoryManager, + ulong address, + ref RegisterMask useMask, + ref bool hasHostCall, + ref bool hasMemoryInstruction) + { + ulong startAddress = address; + + List<InstInfo> insts = new(); + + uint gprUseMask = useMask.GprMask; + uint fpSimdUseMask = useMask.FpSimdMask; + uint pStateUseMask = useMask.PStateMask; + + uint encoding; + InstName name; + InstFlags flags; + bool isControlFlow; + bool isTruncated = false; + + do + { + encoding = memoryManager.Read<uint>(address); + address += 4UL; + + (name, flags, AddressForm addressForm) = InstTable.GetInstNameAndFlags(encoding, cpuPreset.Version, cpuPreset.Features); + + if (name.IsPrivileged()) + { + name = InstName.UdfPermUndef; + flags = InstFlags.None; + addressForm = AddressForm.None; + } + + (uint instGprReadMask, uint instFpSimdReadMask) = RegisterUtils.PopulateReadMasks(name, flags, encoding); + (uint instGprWriteMask, uint instFpSimdWriteMask) = RegisterUtils.PopulateWriteMasks(name, flags, encoding); + + if (name.IsCall()) + { + instGprWriteMask |= 1u << RegisterUtils.LrIndex; + } + + uint tempGprUseMask = gprUseMask | instGprReadMask | instGprWriteMask; + + if (CalculateAvailableTemps(tempGprUseMask) < CalculateRequiredGprTemps(tempGprUseMask) || insts.Count >= MaxInstructionsPerBlock) + { + isTruncated = true; + address -= 4UL; + + break; + } + + gprUseMask = tempGprUseMask; + + uint instPStateReadMask = 0; + uint instPStateWriteMask = 0; + + if (flags.HasFlag(InstFlags.Nzcv) || IsMrsNzcv(encoding)) + { + instPStateReadMask = NzcvFlags; + } + else if (flags.HasFlag(InstFlags.C)) + { + instPStateReadMask = CFlag; + } + + if (flags.HasFlag(InstFlags.S) || IsMsrNzcv(encoding)) + { + instPStateWriteMask = NzcvFlags; + } + + if (flags.HasFlag(InstFlags.Memory) || name == InstName.Sys) + { + hasMemoryInstruction = true; + } + + fpSimdUseMask |= instFpSimdReadMask | instFpSimdWriteMask; + pStateUseMask |= instPStateReadMask | instPStateWriteMask; + + if (name.IsSystemOrCall() && !hasHostCall) + { + hasHostCall = name.IsCall() || InstEmitSystem.NeedsCall(encoding); + } + + isControlFlow = name.IsControlFlowOrException(); + + RegisterUse registerUse = new( + instGprReadMask, + instGprWriteMask, + instFpSimdReadMask, + instFpSimdWriteMask, + instPStateReadMask, + instPStateWriteMask); + + insts.Add(new(encoding, name, flags, addressForm, registerUse)); + } + while (!isControlFlow); + + bool isLoopEnd = false; + + if (!isTruncated && IsBackwardsBranch(name, encoding)) + { + hasHostCall = true; + isLoopEnd = true; + } + + useMask = new(gprUseMask, fpSimdUseMask, pStateUseMask); + + return new(startAddress, address, insts, !isTruncated && !name.IsException(), isTruncated, isLoopEnd); + } + + private static bool IsMrsNzcv(uint encoding) + { + return (encoding & ~0x1fu) == 0xd53b4200u; + } + + private static bool IsMsrNzcv(uint encoding) + { + return (encoding & ~0x1fu) == 0xd51b4200u; + } + + private static bool IsBackwardsBranch(InstName name, uint encoding) + { + switch (name) + { + case InstName.BUncond: + return ImmUtils.ExtractSImm26Times4(encoding) < 0; + + case InstName.BCond: + case InstName.Cbnz: + case InstName.Cbz: + case InstName.Tbnz: + case InstName.Tbz: + int imm = name == InstName.Tbnz || name == InstName.Tbz + ? ImmUtils.ExtractSImm14Times4(encoding) + : ImmUtils.ExtractSImm19Times4(encoding); + + return imm < 0; + } + + return false; + } + + private static int CalculateRequiredGprTemps(uint gprUseMask) + { + return BitOperations.PopCount(gprUseMask & RegisterUtils.ReservedRegsMask) + RegisterAllocator.MaxTempsInclFixed; + } + + private static int CalculateAvailableTemps(uint gprUseMask) + { + return BitOperations.PopCount(~(gprUseMask | RegisterUtils.ReservedRegsMask)); + } + } +} diff --git a/src/Ryujinx.Cpu/LightningJit/Arm64/Target/Arm64/InstEmitMemory.cs b/src/Ryujinx.Cpu/LightningJit/Arm64/Target/Arm64/InstEmitMemory.cs new file mode 100644 index 00000000..ece1520f --- /dev/null +++ b/src/Ryujinx.Cpu/LightningJit/Arm64/Target/Arm64/InstEmitMemory.cs @@ -0,0 +1,593 @@ +using ARMeilleure.Memory; +using Ryujinx.Cpu.LightningJit.CodeGen; +using Ryujinx.Cpu.LightningJit.CodeGen.Arm64; +using System; +using System.Diagnostics; + +namespace Ryujinx.Cpu.LightningJit.Arm64.Target.Arm64 +{ + static class InstEmitMemory + { + private const uint XMask = 0x3f808000u; + private const uint XValue = 0x8000000u; + + public static void RewriteSysInstruction(int asBits, MemoryManagerType mmType, CodeWriter writer, RegisterAllocator regAlloc, uint encoding) + { + int rtIndex = RegisterUtils.ExtractRt(encoding); + if (rtIndex == RegisterUtils.ZrIndex) + { + writer.WriteInstruction(encoding); + + return; + } + + int tempRegister = regAlloc.AllocateTempGprRegister(); + Operand rt = new(tempRegister, RegisterType.Integer, OperandType.I64); + Operand guestAddress = new(rtIndex, RegisterType.Integer, OperandType.I64); + + Assembler asm = new(writer); + + WriteAddressTranslation(asBits, mmType, regAlloc, ref asm, rt, guestAddress); + + encoding = RegisterUtils.ReplaceRt(encoding, tempRegister); + + writer.WriteInstruction(encoding); + + regAlloc.FreeTempGprRegister(tempRegister); + } + + public static void RewriteInstruction( + int asBits, + MemoryManagerType mmType, + CodeWriter writer, + RegisterAllocator regAlloc, + InstName name, + InstFlags flags, + AddressForm addressForm, + ulong pc, + uint encoding) + { + switch (addressForm) + { + case AddressForm.OffsetReg: + RewriteOffsetRegMemoryInstruction(asBits, mmType, writer, regAlloc, flags, encoding); + break; + case AddressForm.PostIndexed: + RewritePostIndexedMemoryInstruction(asBits, mmType, writer, regAlloc, flags, encoding); + break; + case AddressForm.PreIndexed: + RewritePreIndexedMemoryInstruction(asBits, mmType, writer, regAlloc, flags, encoding); + break; + case AddressForm.SignedScaled: + RewriteSignedScaledMemoryInstruction(asBits, mmType, writer, regAlloc, flags, encoding); + break; + case AddressForm.UnsignedScaled: + RewriteUnsignedScaledMemoryInstruction(asBits, mmType, writer, regAlloc, flags, encoding); + break; + case AddressForm.BaseRegister: + // Some applications uses unordered memory instructions in places where + // it does need proper ordering, and only work on some CPUs. + // To work around this, make all exclusive access operations ordered. + + if ((encoding & XMask) == XValue) + { + // Set ordered flag. + encoding |= 1u << 15; + } + + RewriteBaseRegisterMemoryInstruction(asBits, mmType, writer, regAlloc, encoding); + break; + case AddressForm.StructNoOffset: + RewriteBaseRegisterMemoryInstruction(asBits, mmType, writer, regAlloc, encoding); + break; + case AddressForm.BasePlusOffset: + RewriteBasePlusOffsetMemoryInstruction(asBits, mmType, writer, regAlloc, encoding); + break; + case AddressForm.Literal: + RewriteLiteralMemoryInstruction(asBits, mmType, writer, regAlloc, name, pc, encoding); + break; + case AddressForm.StructPostIndexedReg: + RewriteStructPostIndexedRegMemoryInstruction(asBits, mmType, writer, regAlloc, encoding); + break; + default: + writer.WriteInstruction(encoding); + break; + } + } + + private static void RewriteOffsetRegMemoryInstruction(int asBits, MemoryManagerType mmType, CodeWriter writer, RegisterAllocator regAlloc, InstFlags flags, uint encoding) + { + // TODO: Some unallocated encoding cases. + + ArmExtensionType extensionType = (ArmExtensionType)((encoding >> 13) & 7); + + uint size = encoding >> 30; + + if (flags.HasFlag(InstFlags.FpSimd)) + { + size |= (encoding >> 21) & 4u; + } + + int shift = (encoding & (1u << 12)) != 0 ? (int)size : 0; + + int tempRegister = regAlloc.AllocateTempGprRegister(); + Operand rn = new(tempRegister, RegisterType.Integer, OperandType.I64); + Operand guestAddress = new(RegisterUtils.ExtractRn(encoding), RegisterType.Integer, OperandType.I64); + Operand guestOffset = new(RegisterUtils.ExtractRm(encoding), RegisterType.Integer, OperandType.I64); + + Assembler asm = new(writer); + + asm.Add(rn, guestAddress, guestOffset, extensionType, shift); + + WriteAddressTranslation(asBits, mmType, regAlloc, ref asm, rn, rn); + + encoding = RegisterUtils.ReplaceRn(encoding, tempRegister); + encoding = (encoding & ~(0xfffu << 10)) | (1u << 24); // Register -> Unsigned offset + + writer.WriteInstruction(encoding); + + regAlloc.FreeTempGprRegister(tempRegister); + } + + private static void RewritePostIndexedMemoryInstruction(int asBits, MemoryManagerType mmType, CodeWriter writer, RegisterAllocator regAlloc, InstFlags flags, uint encoding) + { + bool isPair = flags.HasFlag(InstFlags.Rt2); + int imm = isPair ? ExtractSImm7Scaled(flags, encoding) : ExtractSImm9(encoding); + + int tempRegister = regAlloc.AllocateTempGprRegister(); + Operand rn = new(tempRegister, RegisterType.Integer, OperandType.I64); + Operand guestAddress = new(RegisterUtils.ExtractRn(encoding), RegisterType.Integer, OperandType.I64); + + Assembler asm = new(writer); + + WriteAddressTranslation(asBits, mmType, regAlloc, ref asm, rn, guestAddress); + + encoding = RegisterUtils.ReplaceRn(encoding, tempRegister); + + if (isPair) + { + // Post-index -> Signed offset + encoding &= ~(0x7fu << 15); + encoding ^= 3u << 23; + } + else + { + // Post-index -> Unsigned offset + encoding = (encoding & ~(0xfffu << 10)) | (1u << 24); + } + + writer.WriteInstruction(encoding); + + WriteAddConstant(ref asm, guestAddress, guestAddress, imm); + + regAlloc.FreeTempGprRegister(tempRegister); + } + + private static void RewritePreIndexedMemoryInstruction(int asBits, MemoryManagerType mmType, CodeWriter writer, RegisterAllocator regAlloc, InstFlags flags, uint encoding) + { + bool isPair = flags.HasFlag(InstFlags.Rt2); + int imm = isPair ? ExtractSImm7Scaled(flags, encoding) : ExtractSImm9(encoding); + + int tempRegister = regAlloc.AllocateTempGprRegister(); + Operand rn = new(tempRegister, RegisterType.Integer, OperandType.I64); + Operand guestAddress = new(RegisterUtils.ExtractRn(encoding), RegisterType.Integer, OperandType.I64); + + Assembler asm = new(writer); + + WriteAddConstant(ref asm, guestAddress, guestAddress, imm); + WriteAddressTranslation(asBits, mmType, regAlloc, ref asm, rn, guestAddress); + + encoding = RegisterUtils.ReplaceRn(encoding, tempRegister); + + if (isPair) + { + // Pre-index -> Signed offset + encoding &= ~(0x7fu << 15); + encoding &= ~(1u << 23); + } + else + { + // Pre-index -> Unsigned offset + encoding = (encoding & ~(0xfffu << 10)) | (1u << 24); + } + + writer.WriteInstruction(encoding); + + regAlloc.FreeTempGprRegister(tempRegister); + } + + private static void RewriteSignedScaledMemoryInstruction(int asBits, MemoryManagerType mmType, CodeWriter writer, RegisterAllocator regAlloc, InstFlags flags, uint encoding) + { + RewriteMemoryInstruction(asBits, mmType, writer, regAlloc, encoding, ExtractSImm7Scaled(flags, encoding), 0x7fu << 15); + } + + private static void RewriteUnsignedScaledMemoryInstruction(int asBits, MemoryManagerType mmType, CodeWriter writer, RegisterAllocator regAlloc, InstFlags flags, uint encoding) + { + RewriteMemoryInstruction(asBits, mmType, writer, regAlloc, encoding, ExtractUImm12Scaled(flags, encoding), 0xfffu << 10); + } + + private static void RewriteBaseRegisterMemoryInstruction(int asBits, MemoryManagerType mmType, CodeWriter writer, RegisterAllocator regAlloc, uint encoding) + { + RewriteMemoryInstruction(asBits, mmType, writer, regAlloc, encoding, 0, 0u); + } + + private static void RewriteBasePlusOffsetMemoryInstruction(int asBits, MemoryManagerType mmType, CodeWriter writer, RegisterAllocator regAlloc, uint encoding) + { + RewriteMemoryInstruction(asBits, mmType, writer, regAlloc, encoding, ExtractSImm9(encoding), 0x1ffu << 12); + } + + private static void RewriteMemoryInstruction(int asBits, MemoryManagerType mmType, CodeWriter writer, RegisterAllocator regAlloc, uint encoding, int imm, uint immMask) + { + int tempRegister = regAlloc.AllocateTempGprRegister(); + Operand rn = new(tempRegister, RegisterType.Integer, OperandType.I64); + Operand guestAddress = new(RegisterUtils.ExtractRn(encoding), RegisterType.Integer, OperandType.I64); + + Assembler asm = new(writer); + + bool canFoldOffset = CanFoldOffset(mmType, imm); + if (canFoldOffset) + { + imm = 0; + } + + WriteAddressTranslation(asBits, mmType, regAlloc, ref asm, rn, guestAddress, imm); + + encoding = RegisterUtils.ReplaceRn(encoding, tempRegister); + + if (!canFoldOffset) + { + encoding &= ~immMask; // Clear offset + } + + writer.WriteInstruction(encoding); + + regAlloc.FreeTempGprRegister(tempRegister); + } + + private static void RewriteLiteralMemoryInstruction(int asBits, MemoryManagerType mmType, CodeWriter writer, RegisterAllocator regAlloc, InstName name, ulong pc, uint encoding) + { + Assembler asm = new(writer); + + ulong targetAddress; + long imm; + int rtIndex = (int)(encoding & 0x1f); + + if (rtIndex == RegisterUtils.ZrIndex && name != InstName.PrfmLit) + { + return; + } + + Operand rt; + + if (name == InstName.LdrLitFpsimd) + { + uint opc = encoding >> 30; + + // TODO: Undefined if opc is invalid? + + rt = new(rtIndex, RegisterType.Vector, opc switch + { + 0 => OperandType.FP32, + 1 => OperandType.FP64, + _ => OperandType.V128, + }); + } + else + { + rt = new(rtIndex, RegisterType.Integer, OperandType.I64); + } + + switch (name) + { + case InstName.Adr: + case InstName.Adrp: + imm = ((long)(encoding >> 29) & 3) | ((long)(encoding >> 3) & 0x1ffffc); + imm <<= 43; + + if (name == InstName.Adrp) + { + imm >>= 31; + targetAddress = (pc & ~0xfffUL) + (ulong)imm; + } + else + { + imm >>= 43; + targetAddress = pc + (ulong)imm; + } + + asm.Mov(rt, targetAddress); + break; + case InstName.LdrLitGen: + case InstName.LdrswLit: + case InstName.LdrLitFpsimd: + case InstName.PrfmLit: + imm = encoding & ~0x1fu; + imm <<= 40; + imm >>= 43; + targetAddress = pc + (ulong)imm; + + int tempRegister = regAlloc.AllocateTempGprRegister(); + Operand rn = new(tempRegister, RegisterType.Integer, OperandType.I64); + + WriteAddressTranslation(asBits, mmType, regAlloc, ref asm, rn, targetAddress); + + switch (name) + { + case InstName.LdrLitGen: + case InstName.LdrLitFpsimd: + asm.LdrRiUn(rt, rn, 0); + break; + case InstName.LdrswLit: + asm.LdrswRiUn(rt, rn, 0); + break; + case InstName.PrfmLit: + asm.PrfmR(rt, rn); + break; + } + + regAlloc.FreeTempGprRegister(tempRegister); + break; + default: + Debug.Fail($"Invalid literal memory instruction '{name}'."); + break; + } + } + + private static void RewriteStructPostIndexedRegMemoryInstruction(int asBits, MemoryManagerType mmType, CodeWriter writer, RegisterAllocator regAlloc, uint encoding) + { + // TODO: Some unallocated encoding cases. + + int tempRegister = regAlloc.AllocateTempGprRegister(); + Operand rn = new(tempRegister, RegisterType.Integer, OperandType.I64); + Operand guestAddress = new(RegisterUtils.ExtractRn(encoding), RegisterType.Integer, OperandType.I64); + + int rmIndex = RegisterUtils.ExtractRm(encoding); + + Assembler asm = new(writer); + + WriteAddressTranslation(asBits, mmType, regAlloc, ref asm, rn, guestAddress); + + encoding = RegisterUtils.ReplaceRn(encoding, tempRegister); + encoding &= ~((0x1fu << 16) | (1u << 23)); // Post-index -> No offset + + writer.WriteInstruction(encoding); + + if (rmIndex == RegisterUtils.ZrIndex) + { + bool isSingleStruct = (encoding & (1u << 24)) != 0; + int offset; + + if (isSingleStruct) + { + int sElems = (int)(((encoding >> 12) & 2u) | ((encoding >> 21) & 1u)) + 1; + + int size = (int)(encoding >> 10) & 3; + int s = (int)(encoding >> 12) & 1; + int scale = (int)(encoding >> 14) & 3; + int l = (int)(encoding >> 22) & 1; + + switch (scale) + { + case 1: + if ((size & 1) != 0) + { + // Undef. + } + + break; + + case 2: + if ((size & 2) != 0 || + ((size & 1) != 0 && s != 0)) + { + // Undef. + } + + if ((size & 1) != 0) + { + scale = 3; + } + + break; + + case 3: + if (l == 0 || s != 0) + { + // Undef. + } + + scale = size; + + break; + } + + int eBytes = 1 << scale; + + offset = eBytes * sElems; + } + else + { + int reps; + int sElems; + + switch ((encoding >> 12) & 0xf) + { + case 0b0000: + reps = 1; + sElems = 4; + break; + case 0b0010: + reps = 4; + sElems = 1; + break; + case 0b0100: + reps = 1; + sElems = 3; + break; + case 0b0110: + reps = 3; + sElems = 1; + break; + case 0b0111: + reps = 1; + sElems = 1; + break; + case 0b1000: + reps = 1; + sElems = 2; + break; + case 0b1010: + reps = 2; + sElems = 1; + break; + + default: + // Undef. + reps = 0; + sElems = 0; + break; + } + + int size = (int)(encoding >> 10) & 3; + bool q = (encoding & (1u << 30)) != 0; + + if (!q && size == 3 && sElems != 1) + { + // Undef. + } + + offset = reps * (q ? 16 : 8) * sElems; + } + + asm.Add(guestAddress, guestAddress, new Operand(OperandKind.Constant, OperandType.I32, (ulong)offset)); + } + else + { + Operand guestOffset = new(rmIndex, RegisterType.Integer, OperandType.I64); + + asm.Add(guestAddress, guestAddress, guestOffset); + } + + regAlloc.FreeTempGprRegister(tempRegister); + } + + private static void WriteAddressTranslation( + int asBits, + MemoryManagerType mmType, + RegisterAllocator regAlloc, + ref Assembler asm, + Operand destination, + Operand guestAddress, + int offset) + { + if (offset != 0) + { + // They are assumed to be on different registers, otherwise this operation will thrash the address. + Debug.Assert(destination.Value != guestAddress.Value); + + if (Math.Abs(offset) >= 0x1000) + { + // Too high to encode as 12-bit immediate, do a separate move. + asm.Mov(destination, (ulong)offset); + asm.Add(destination, destination, guestAddress); + } + else + { + // Encode as 12-bit immediate. + WriteAddConstant(ref asm, destination, guestAddress, offset); + } + + guestAddress = destination; + } + + WriteAddressTranslation(asBits, mmType, regAlloc, ref asm, destination, guestAddress); + } + + private static void WriteAddressTranslation(int asBits, MemoryManagerType mmType, RegisterAllocator regAlloc, ref Assembler asm, Operand destination, ulong guestAddress) + { + asm.Mov(destination, guestAddress); + + WriteAddressTranslation(asBits, mmType, regAlloc, ref asm, destination, destination); + } + + private static void WriteAddressTranslation(int asBits, MemoryManagerType mmType, RegisterAllocator regAlloc, ref Assembler asm, Operand destination, Operand guestAddress) + { + Operand basePointer = new(regAlloc.FixedPageTableRegister, RegisterType.Integer, OperandType.I64); + + if (mmType == MemoryManagerType.HostMapped || mmType == MemoryManagerType.HostMappedUnsafe) + { + if (mmType == MemoryManagerType.HostMapped) + { + asm.And(destination, guestAddress, new Operand(OperandKind.Constant, OperandType.I64, ulong.MaxValue >> (64 - asBits))); + guestAddress = destination; + } + + asm.Add(destination, basePointer, guestAddress); + } + else + { + throw new NotImplementedException(mmType.ToString()); + } + } + + private static void WriteAddConstant(ref Assembler asm, Operand rd, Operand rn, int value) + { + if (value < 0) + { + asm.Sub(rd, rn, new Operand(OperandKind.Constant, OperandType.I32, (ulong)-value)); + } + else + { + asm.Add(rd, rn, new Operand(OperandKind.Constant, OperandType.I32, (ulong)value)); + } + } + + private static bool CanFoldOffset(MemoryManagerType mmType, int offset) + { + return mmType == MemoryManagerType.HostMappedUnsafe; + } + + private static int ExtractSImm7Scaled(InstFlags flags, uint encoding) + { + uint opc = flags.HasFlag(InstFlags.FpSimd) ? encoding >> 30 : encoding >> 31; + return ExtractSImm7(encoding) << (int)(2 + opc); + } + + private static int ExtractSImm7(uint encoding) + { + int imm = (int)(encoding >> 15); + + imm <<= 25; + imm >>= 25; + + return imm; + } + + private static int ExtractSImm9(uint encoding) + { + int imm = (int)(encoding >> 12); + + imm <<= 23; + imm >>= 23; + + return imm; + } + + private static int ExtractUImm12Scaled(InstFlags flags, uint encoding) + { + uint size = encoding >> 30; + + if (flags.HasFlag(InstFlags.FpSimd)) + { + size |= (encoding >> 21) & 4u; + } + + return ExtractUImm12(encoding) << (int)size; + } + + private static int ExtractUImm12(uint encoding) + { + return (int)(encoding >> 10) & 0xfff; + } + } +} diff --git a/src/Ryujinx.Cpu/LightningJit/Arm64/Target/Arm64/InstEmitSystem.cs b/src/Ryujinx.Cpu/LightningJit/Arm64/Target/Arm64/InstEmitSystem.cs new file mode 100644 index 00000000..3d4204fc --- /dev/null +++ b/src/Ryujinx.Cpu/LightningJit/Arm64/Target/Arm64/InstEmitSystem.cs @@ -0,0 +1,610 @@ +using ARMeilleure.Common; +using Ryujinx.Cpu.LightningJit.CodeGen; +using Ryujinx.Cpu.LightningJit.CodeGen.Arm64; +using System; +using System.Diagnostics; +using System.Numerics; +using System.Runtime.CompilerServices; +using System.Runtime.InteropServices; + +namespace Ryujinx.Cpu.LightningJit.Arm64.Target.Arm64 +{ + static class InstEmitSystem + { + private delegate void SoftwareInterruptHandler(ulong address, int imm); + private delegate ulong Get64(); + private delegate bool GetBool(); + + public static void RewriteInstruction( + CodeWriter writer, + RegisterAllocator regAlloc, + TailMerger tailMerger, + InstName name, + ulong pc, + uint encoding, + int spillBaseOffset) + { + if (name == InstName.Brk) + { + Assembler asm = new(writer); + + WriteCall(ref asm, regAlloc, GetBrkHandlerPtr(), spillBaseOffset, null, pc, encoding); + WriteSyncPoint(writer, ref asm, regAlloc, tailMerger, spillBaseOffset); + } + else if (name == InstName.Svc) + { + uint svcId = (ushort)(encoding >> 5); + + Assembler asm = new(writer); + + WriteCall(ref asm, regAlloc, GetSvcHandlerPtr(), spillBaseOffset, null, pc, svcId); + WriteSyncPoint(writer, ref asm, regAlloc, tailMerger, spillBaseOffset); + } + else if (name == InstName.UdfPermUndef) + { + Assembler asm = new(writer); + + WriteCall(ref asm, regAlloc, GetUdfHandlerPtr(), spillBaseOffset, null, pc, encoding); + WriteSyncPoint(writer, ref asm, regAlloc, tailMerger, spillBaseOffset); + } + else if ((encoding & ~0x1f) == 0xd53bd060) // mrs x0, tpidrro_el0 + { + uint rd = encoding & 0x1f; + + if (rd != RegisterUtils.ZrIndex) + { + Assembler asm = new(writer); + + asm.LdrRiUn(Register((int)rd), Register(regAlloc.FixedContextRegister), NativeContextOffsets.TpidrroEl0Offset); + } + } + else if ((encoding & ~0x1f) == 0xd53bd040) // mrs x0, tpidr_el0 + { + uint rd = encoding & 0x1f; + + if (rd != RegisterUtils.ZrIndex) + { + Assembler asm = new(writer); + + asm.LdrRiUn(Register((int)rd), Register(regAlloc.FixedContextRegister), NativeContextOffsets.TpidrEl0Offset); + } + } + else if ((encoding & ~0x1f) == 0xd53b0020 && IsAppleOS()) // mrs x0, ctr_el0 + { + uint rd = encoding & 0x1f; + + if (rd != RegisterUtils.ZrIndex) + { + Assembler asm = new(writer); + + // TODO: Use host value? But that register can't be accessed on macOS... + asm.Mov(Register((int)rd, OperandType.I32), 0x8444c004); + } + } + else if ((encoding & ~0x1f) == 0xd53be020) // mrs x0, cntpct_el0 + { + uint rd = encoding & 0x1f; + + if (rd != RegisterUtils.ZrIndex) + { + Assembler asm = new(writer); + + WriteCall(ref asm, regAlloc, GetCntpctEl0Ptr(), spillBaseOffset, (int)rd); + } + } + else if ((encoding & ~0x1f) == 0xd51bd040) // msr tpidr_el0, x0 + { + uint rd = encoding & 0x1f; + + if (rd != RegisterUtils.ZrIndex) + { + Assembler asm = new(writer); + + asm.StrRiUn(Register((int)rd), Register(regAlloc.FixedContextRegister), NativeContextOffsets.TpidrEl0Offset); + } + } + else + { + writer.WriteInstruction(encoding); + } + } + + public static bool NeedsCall(uint encoding) + { + if ((encoding & ~(0xffffu << 5)) == 0xd4000001u) // svc #0 + { + return true; + } + else if ((encoding & ~0x1f) == 0xd53b0020 && IsAppleOS()) // mrs x0, ctr_el0 + { + return true; + } + else if ((encoding & ~0x1f) == 0xd53be020) // mrs x0, cntpct_el0 + { + return true; + } + + return false; + } + + private static bool IsAppleOS() + { + return OperatingSystem.IsMacOS() || OperatingSystem.IsIOS(); + } + + public static bool NeedsContextStoreLoad(InstName name) + { + return name == InstName.Svc; + } + + private static IntPtr GetBrkHandlerPtr() + { + return Marshal.GetFunctionPointerForDelegate<SoftwareInterruptHandler>(NativeInterface.Break); + } + + private static IntPtr GetSvcHandlerPtr() + { + return Marshal.GetFunctionPointerForDelegate<SoftwareInterruptHandler>(NativeInterface.SupervisorCall); + } + + private static IntPtr GetUdfHandlerPtr() + { + return Marshal.GetFunctionPointerForDelegate<SoftwareInterruptHandler>(NativeInterface.Undefined); + } + + private static IntPtr GetCntpctEl0Ptr() + { + return Marshal.GetFunctionPointerForDelegate<Get64>(NativeInterface.GetCntpctEl0); + } + + private static IntPtr CheckSynchronizationPtr() + { + return Marshal.GetFunctionPointerForDelegate<GetBool>(NativeInterface.CheckSynchronization); + } + + public static void WriteSyncPoint(CodeWriter writer, RegisterAllocator regAlloc, TailMerger tailMerger, int spillBaseOffset) + { + Assembler asm = new(writer); + + WriteSyncPoint(writer, ref asm, regAlloc, tailMerger, spillBaseOffset); + } + + private static void WriteSyncPoint(CodeWriter writer, ref Assembler asm, RegisterAllocator regAlloc, TailMerger tailMerger, int spillBaseOffset) + { + int tempRegister = regAlloc.AllocateTempGprRegister(); + + Operand rt = Register(tempRegister, OperandType.I32); + + asm.LdrRiUn(rt, Register(regAlloc.FixedContextRegister), NativeContextOffsets.CounterOffset); + + int branchIndex = writer.InstructionPointer; + asm.Cbnz(rt, 0); + + WriteSpill(ref asm, regAlloc, 1u << tempRegister, spillBaseOffset, tempRegister); + + Operand rn = Register(tempRegister == 0 ? 1 : 0); + + asm.Mov(rn, (ulong)CheckSynchronizationPtr()); + asm.Blr(rn); + + tailMerger.AddConditionalZeroReturn(writer, asm, Register(0, OperandType.I32)); + + WriteFill(ref asm, regAlloc, 1u << tempRegister, spillBaseOffset, tempRegister); + + asm.LdrRiUn(rt, Register(regAlloc.FixedContextRegister), NativeContextOffsets.CounterOffset); + + uint branchInst = writer.ReadInstructionAt(branchIndex); + writer.WriteInstructionAt(branchIndex, branchInst | (((uint)(writer.InstructionPointer - branchIndex) & 0x7ffff) << 5)); + + asm.Sub(rt, rt, new Operand(OperandKind.Constant, OperandType.I32, 1)); + asm.StrRiUn(rt, Register(regAlloc.FixedContextRegister), NativeContextOffsets.CounterOffset); + + regAlloc.FreeTempGprRegister(tempRegister); + } + + public static void RewriteCallInstruction( + CodeWriter writer, + RegisterAllocator regAlloc, + TailMerger tailMerger, + Action writeEpilogue, + AddressTable<ulong> funcTable, + IntPtr dispatchStubPtr, + InstName name, + ulong pc, + uint encoding, + int spillBaseOffset, + bool isTail = false) + { + Assembler asm = new(writer); + + switch (name) + { + case InstName.BUncond: + case InstName.Bl: + case InstName.Blr: + case InstName.Br: + if (name == InstName.BUncond || name == InstName.Bl) + { + int imm = ImmUtils.ExtractSImm26Times4(encoding); + + WriteCallWithGuestAddress( + writer, + ref asm, + regAlloc, + tailMerger, + writeEpilogue, + funcTable, + dispatchStubPtr, + spillBaseOffset, + pc, + new(OperandKind.Constant, OperandType.I64, pc + (ulong)imm), + isTail); + } + else + { + int rnIndex = RegisterUtils.ExtractRn(encoding); + if (rnIndex == RegisterUtils.ZrIndex) + { + WriteCallWithGuestAddress( + writer, + ref asm, + regAlloc, + tailMerger, + writeEpilogue, + funcTable, + dispatchStubPtr, + spillBaseOffset, + pc, + new(OperandKind.Constant, OperandType.I64, 0UL), + isTail); + } + else + { + rnIndex = regAlloc.RemapReservedGprRegister(rnIndex); + + WriteCallWithGuestAddress( + writer, + ref asm, + regAlloc, + tailMerger, + writeEpilogue, + funcTable, + dispatchStubPtr, + spillBaseOffset, + pc, + Register(rnIndex), + isTail); + } + } + break; + + default: + Debug.Fail($"Unknown branch instruction \"{name}\"."); + break; + } + } + + public unsafe static void WriteCallWithGuestAddress( + CodeWriter writer, + ref Assembler asm, + RegisterAllocator regAlloc, + TailMerger tailMerger, + Action writeEpilogue, + AddressTable<ulong> funcTable, + IntPtr funcPtr, + int spillBaseOffset, + ulong pc, + Operand guestAddress, + bool isTail = false) + { + int tempRegister; + + if (guestAddress.Kind == OperandKind.Constant) + { + tempRegister = regAlloc.AllocateTempGprRegister(); + + asm.Mov(Register(tempRegister), guestAddress.Value); + asm.StrRiUn(Register(tempRegister), Register(regAlloc.FixedContextRegister), NativeContextOffsets.DispatchAddressOffset); + + regAlloc.FreeTempGprRegister(tempRegister); + } + else + { + asm.StrRiUn(guestAddress, Register(regAlloc.FixedContextRegister), NativeContextOffsets.DispatchAddressOffset); + } + + tempRegister = regAlloc.FixedContextRegister == 1 ? 2 : 1; + + if (!isTail) + { + WriteSpillSkipContext(ref asm, regAlloc, spillBaseOffset); + } + + Operand rn = Register(tempRegister); + + if (regAlloc.FixedContextRegister != 0) + { + asm.Mov(Register(0), Register(regAlloc.FixedContextRegister)); + } + + if (guestAddress.Kind == OperandKind.Constant && funcTable != null) + { + ulong funcPtrLoc = (ulong)Unsafe.AsPointer(ref funcTable.GetValue(guestAddress.Value)); + + asm.Mov(rn, funcPtrLoc & ~0xfffUL); + asm.LdrRiUn(rn, rn, (int)(funcPtrLoc & 0xfffUL)); + } + else + { + asm.Mov(rn, (ulong)funcPtr); + } + + if (isTail) + { + writeEpilogue(); + asm.Br(rn); + } + else + { + asm.Blr(rn); + + ulong nextAddress = pc + 4UL; + + asm.Mov(rn, nextAddress); + asm.Cmp(Register(0), rn); + + tailMerger.AddConditionalReturn(writer, asm, ArmCondition.Ne); + + WriteFillSkipContext(ref asm, regAlloc, spillBaseOffset); + } + } + + private static void WriteCall( + ref Assembler asm, + RegisterAllocator regAlloc, + IntPtr funcPtr, + int spillBaseOffset, + int? resultRegister, + params ulong[] callArgs) + { + uint resultMask = 0u; + + if (resultRegister.HasValue) + { + resultMask = 1u << resultRegister.Value; + } + + int tempRegister = callArgs.Length; + + if (resultRegister.HasValue && tempRegister == resultRegister.Value) + { + tempRegister++; + } + + WriteSpill(ref asm, regAlloc, resultMask, spillBaseOffset, tempRegister); + + // We only support up to 7 arguments right now. + // ABI defines the first 8 integer arguments to be passed on registers X0-X7. + // We need at least one register to put the function address on, so that reduces the number of + // registers we can use for that by one. + + Debug.Assert(callArgs.Length < 8); + + for (int index = 0; index < callArgs.Length; index++) + { + asm.Mov(Register(index), callArgs[index]); + } + + Operand rn = Register(tempRegister); + + asm.Mov(rn, (ulong)funcPtr); + asm.Blr(rn); + + if (resultRegister.HasValue && resultRegister.Value != 0) + { + asm.Mov(Register(resultRegister.Value), Register(0)); + } + + WriteFill(ref asm, regAlloc, resultMask, spillBaseOffset, tempRegister); + } + + private static void WriteSpill(ref Assembler asm, RegisterAllocator regAlloc, uint exceptMask, int spillOffset, int tempRegister) + { + WriteSpillOrFill(ref asm, regAlloc, exceptMask, spillOffset, tempRegister, spill: true); + } + + private static void WriteFill(ref Assembler asm, RegisterAllocator regAlloc, uint exceptMask, int spillOffset, int tempRegister) + { + WriteSpillOrFill(ref asm, regAlloc, exceptMask, spillOffset, tempRegister, spill: false); + } + + private static void WriteSpillOrFill( + ref Assembler asm, + RegisterAllocator regAlloc, + uint exceptMask, + int spillOffset, + int tempRegister, + bool spill) + { + uint gprMask = regAlloc.AllGprMask & ~(AbiConstants.GprCalleeSavedRegsMask | exceptMask); + + if (regAlloc.AllPStateMask != 0 && !spill) + { + // We must reload the status register before reloading the GPRs, + // since we might otherwise trash one of them by using it as temp register. + + Operand rt = Register(tempRegister, OperandType.I32); + + asm.LdrRiUn(rt, Register(RegisterUtils.SpIndex), spillOffset + BitOperations.PopCount(gprMask) * 8); + asm.MsrNzcv(rt); + } + + while (gprMask != 0) + { + int reg = BitOperations.TrailingZeroCount(gprMask); + + if (reg < 31 && (gprMask & (2u << reg)) != 0 && spillOffset < RegisterSaveRestore.Encodable9BitsOffsetLimit) + { + if (spill) + { + asm.StpRiUn( + Register(regAlloc.RemapReservedGprRegister(reg)), + Register(regAlloc.RemapReservedGprRegister(reg + 1)), + Register(RegisterUtils.SpIndex), + spillOffset); + } + else + { + asm.LdpRiUn( + Register(regAlloc.RemapReservedGprRegister(reg)), + Register(regAlloc.RemapReservedGprRegister(reg + 1)), + Register(RegisterUtils.SpIndex), + spillOffset); + } + + gprMask &= ~(3u << reg); + spillOffset += 16; + } + else + { + if (spill) + { + asm.StrRiUn(Register(regAlloc.RemapReservedGprRegister(reg)), Register(RegisterUtils.SpIndex), spillOffset); + } + else + { + asm.LdrRiUn(Register(regAlloc.RemapReservedGprRegister(reg)), Register(RegisterUtils.SpIndex), spillOffset); + } + + gprMask &= ~(1u << reg); + spillOffset += 8; + } + } + + if (regAlloc.AllPStateMask != 0) + { + if (spill) + { + Operand rt = Register(tempRegister, OperandType.I32); + + asm.MrsNzcv(rt); + asm.StrRiUn(rt, Register(RegisterUtils.SpIndex), spillOffset); + } + + spillOffset += 8; + } + + if ((spillOffset & 8) != 0) + { + spillOffset += 8; + } + + uint fpSimdMask = regAlloc.AllFpSimdMask; + + while (fpSimdMask != 0) + { + int reg = BitOperations.TrailingZeroCount(fpSimdMask); + + if (reg < 31 && (fpSimdMask & (2u << reg)) != 0 && spillOffset < RegisterSaveRestore.Encodable9BitsOffsetLimit) + { + if (spill) + { + asm.StpRiUn( + Register(reg, OperandType.V128), + Register(reg + 1, OperandType.V128), + Register(RegisterUtils.SpIndex), + spillOffset); + } + else + { + asm.LdpRiUn( + Register(reg, OperandType.V128), + Register(reg + 1, OperandType.V128), + Register(RegisterUtils.SpIndex), + spillOffset); + } + + fpSimdMask &= ~(3u << reg); + spillOffset += 32; + } + else + { + if (spill) + { + asm.StrRiUn(Register(reg, OperandType.V128), Register(RegisterUtils.SpIndex), spillOffset); + } + else + { + asm.LdrRiUn(Register(reg, OperandType.V128), Register(RegisterUtils.SpIndex), spillOffset); + } + + fpSimdMask &= ~(1u << reg); + spillOffset += 16; + } + } + } + + private static void WriteSpillSkipContext(ref Assembler asm, RegisterAllocator regAlloc, int spillOffset) + { + WriteSpillOrFillSkipContext(ref asm, regAlloc, spillOffset, spill: true); + } + + private static void WriteFillSkipContext(ref Assembler asm, RegisterAllocator regAlloc, int spillOffset) + { + WriteSpillOrFillSkipContext(ref asm, regAlloc, spillOffset, spill: false); + } + + private static void WriteSpillOrFillSkipContext(ref Assembler asm, RegisterAllocator regAlloc, int spillOffset, bool spill) + { + uint gprMask = regAlloc.AllGprMask & ((1u << regAlloc.FixedContextRegister) | (1u << regAlloc.FixedPageTableRegister)); + gprMask &= ~AbiConstants.GprCalleeSavedRegsMask; + + while (gprMask != 0) + { + int reg = BitOperations.TrailingZeroCount(gprMask); + + if (reg < 31 && (gprMask & (2u << reg)) != 0 && spillOffset < RegisterSaveRestore.Encodable9BitsOffsetLimit) + { + if (spill) + { + asm.StpRiUn( + Register(regAlloc.RemapReservedGprRegister(reg)), + Register(regAlloc.RemapReservedGprRegister(reg + 1)), + Register(RegisterUtils.SpIndex), + spillOffset); + } + else + { + asm.LdpRiUn( + Register(regAlloc.RemapReservedGprRegister(reg)), + Register(regAlloc.RemapReservedGprRegister(reg + 1)), + Register(RegisterUtils.SpIndex), + spillOffset); + } + + gprMask &= ~(3u << reg); + spillOffset += 16; + } + else + { + if (spill) + { + asm.StrRiUn(Register(regAlloc.RemapReservedGprRegister(reg)), Register(RegisterUtils.SpIndex), spillOffset); + } + else + { + asm.LdrRiUn(Register(regAlloc.RemapReservedGprRegister(reg)), Register(RegisterUtils.SpIndex), spillOffset); + } + + gprMask &= ~(1u << reg); + spillOffset += 8; + } + } + } + + private static Operand Register(int register, OperandType type = OperandType.I64) + { + return new Operand(register, RegisterType.Integer, type); + } + } +} diff --git a/src/Ryujinx.Cpu/LightningJit/Arm64/Target/Arm64/InstTable.cs b/src/Ryujinx.Cpu/LightningJit/Arm64/Target/Arm64/InstTable.cs new file mode 100644 index 00000000..88718afb --- /dev/null +++ b/src/Ryujinx.Cpu/LightningJit/Arm64/Target/Arm64/InstTable.cs @@ -0,0 +1,1605 @@ +using Ryujinx.Cpu.LightningJit.Table; +using System.Collections.Generic; + +namespace Ryujinx.Cpu.LightningJit.Arm64.Target.Arm64 +{ + static class InstTable + { + private static readonly InstTableLevel<InstInfo> _table; + + private readonly struct InstInfo : IInstInfo + { + public uint Encoding { get; } + public uint EncodingMask { get; } + public InstEncoding[] Constraints { get; } + public InstName Name { get; } + public IsaVersion Version { get; } + public IsaFeature Feature { get; } + public InstFlags Flags { get; } + public AddressForm AddressForm { get; } + + public InstInfo( + uint encoding, + uint encodingMask, + InstEncoding[] constraints, + InstName name, + IsaVersion isaVersion, + IsaFeature isaFeature, + InstFlags flags, + AddressForm addressForm = AddressForm.None) + { + if (addressForm != AddressForm.None) + { + flags |= InstFlags.Memory; + } + + Encoding = encoding; + EncodingMask = encodingMask; + Constraints = constraints; + Name = name; + Version = isaVersion; + Feature = isaFeature; + Flags = flags; + AddressForm = addressForm; + } + + public InstInfo( + uint encoding, + uint encodingMask, + InstEncoding[] constraints, + InstName name, + IsaVersion isaVersion, + InstFlags flags, + AddressForm addressForm = AddressForm.None) : this(encoding, encodingMask, constraints, name, isaVersion, IsaFeature.None, flags, addressForm) + { + } + + public InstInfo( + uint encoding, + uint encodingMask, + InstName name, + IsaVersion isaVersion, + IsaFeature isaFeature, + InstFlags flags, + AddressForm addressForm = AddressForm.None) : this(encoding, encodingMask, null, name, isaVersion, isaFeature, flags, addressForm) + { + } + + public InstInfo( + uint encoding, + uint encodingMask, + InstName name, + IsaVersion isaVersion, + InstFlags flags, + AddressForm addressForm = AddressForm.None) : this(encoding, encodingMask, null, name, isaVersion, IsaFeature.None, flags, addressForm) + { + } + + public bool IsConstrained(uint encoding) + { + if (Constraints != null) + { + foreach (InstEncoding constraint in Constraints) + { + if ((encoding & constraint.EncodingMask) == constraint.Encoding) + { + return true; + } + } + } + + return false; + } + } + + static InstTable() + { + InstEncoding[] qsizeConstraints = new InstEncoding[] + { + new(0x00C00000, 0x40C00000), + }; + + InstEncoding[] sizeConstraints = new InstEncoding[] + { + new(0x00C00000, 0x00C00000), + }; + + InstEncoding[] opuOpuOpuConstraints = new InstEncoding[] + { + new(0x00001400, 0x00001C00), + new(0x00001800, 0x00001C00), + new(0x00001C00, 0x00001C00), + }; + + InstEncoding[] shiftSfimm6Constraints = new InstEncoding[] + { + new(0x00C00000, 0x00C00000), + new(0x00008000, 0x80008000), + }; + + InstEncoding[] qsizeSizeConstraints = new InstEncoding[] + { + new(0x00800000, 0x40C00000), + new(0x00C00000, 0x00C00000), + }; + + InstEncoding[] nimmsNimmsNimmsNimmsNimmsNimmsNimmsNimmsSfnConstraints = new InstEncoding[] + { + new(0x0040FC00, 0x0040FC00), + new(0x00007C00, 0x0040FC00), + new(0x0000BC00, 0x0040FC00), + new(0x0000DC00, 0x0040FC00), + new(0x0000EC00, 0x0040FC00), + new(0x0000F400, 0x0040FC00), + new(0x0000F800, 0x0040FC00), + new(0x0000FC00, 0x0040FC00), + new(0x00400000, 0x80400000), + }; + + InstEncoding[] sfimm6Constraints = new InstEncoding[] + { + new(0x00008000, 0x80008000), + }; + + InstEncoding[] sfnSfnSfimmr5Sfimms5Constraints = new InstEncoding[] + { + new(0x80000000, 0x80400000), + new(0x00400000, 0x80400000), + new(0x00200000, 0x80200000), + new(0x00008000, 0x80008000), + }; + + InstEncoding[] cmodeopqConstraints = new InstEncoding[] + { + new(0x2000F000, 0x6000F000), + }; + + InstEncoding[] rsRtConstraints = new InstEncoding[] + { + new(0x00010000, 0x00010000), + new(0x00000001, 0x00000001), + }; + + InstEncoding[] sfszSfszSfszSfszConstraints = new InstEncoding[] + { + new(0x80000000, 0x80000C00), + new(0x80000400, 0x80000C00), + new(0x80000800, 0x80000C00), + new(0x00000C00, 0x80000C00), + }; + + InstEncoding[] imm5Constraints = new InstEncoding[] + { + new(0x00000000, 0x000F0000), + }; + + InstEncoding[] imm5Imm5qConstraints = new InstEncoding[] + { + new(0x00000000, 0x000F0000), + new(0x00080000, 0x400F0000), + }; + + InstEncoding[] nsfNsfSfimmsConstraints = new InstEncoding[] + { + new(0x00400000, 0x80400000), + new(0x80000000, 0x80400000), + new(0x00008000, 0x80008000), + }; + + InstEncoding[] qimm4Constraints = new InstEncoding[] + { + new(0x00004000, 0x40004000), + }; + + InstEncoding[] qszConstraints = new InstEncoding[] + { + new(0x00400000, 0x40400000), + }; + + InstEncoding[] euacEuacEuacConstraints = new InstEncoding[] + { + new(0x00000800, 0x20800800), + new(0x00800000, 0x20800800), + new(0x00800800, 0x20800800), + }; + + InstEncoding[] qszEuacEuacEuacConstraints = new InstEncoding[] + { + new(0x00400000, 0x40400000), + new(0x00000800, 0x20800800), + new(0x00800000, 0x20800800), + new(0x00800800, 0x20800800), + }; + + InstEncoding[] szConstraints = new InstEncoding[] + { + new(0x00400000, 0x00400000), + }; + + InstEncoding[] sizeQsizeConstraints = new InstEncoding[] + { + new(0x00000000, 0x00C00000), + new(0x00C00000, 0x40C00000), + }; + + InstEncoding[] sizeSizeSizelSizeqSizehqConstraints = new InstEncoding[] + { + new(0x00000000, 0x00C00000), + new(0x00C00000, 0x00C00000), + new(0x00A00000, 0x00E00000), + new(0x00800000, 0x40C00000), + new(0x00400800, 0x40C00800), + }; + + InstEncoding[] szConstraints2 = new InstEncoding[] + { + new(0x00000000, 0x00400000), + }; + + InstEncoding[] immhConstraints = new InstEncoding[] + { + new(0x00000000, 0x00780000), + }; + + InstEncoding[] immhQimmhConstraints = new InstEncoding[] + { + new(0x00000000, 0x00780000), + new(0x00400000, 0x40400000), + }; + + InstEncoding[] sfscaleConstraints = new InstEncoding[] + { + new(0x00000000, 0x80008000), + }; + + InstEncoding[] ftypeopcFtypeopcFtypeopcFtypeopcFtypeOpcConstraints = new InstEncoding[] + { + new(0x00000000, 0x00C18000), + new(0x00408000, 0x00C18000), + new(0x00810000, 0x00C18000), + new(0x00C18000, 0x00C18000), + new(0x00800000, 0x00C00000), + new(0x00010000, 0x00018000), + }; + + InstEncoding[] szlConstraints = new InstEncoding[] + { + new(0x00600000, 0x00600000), + }; + + InstEncoding[] szlQszConstraints = new InstEncoding[] + { + new(0x00600000, 0x00600000), + new(0x00400000, 0x40400000), + }; + + InstEncoding[] qConstraints = new InstEncoding[] + { + new(0x00000000, 0x40000000), + }; + + InstEncoding[] sfftypermodeSfftypermodeConstraints = new InstEncoding[] + { + new(0x00400000, 0x80C80000), + new(0x80000000, 0x80C80000), + }; + + InstEncoding[] uo1o2Constraints = new InstEncoding[] + { + new(0x20800000, 0x20801000), + }; + + InstEncoding[] qszUo1o2Constraints = new InstEncoding[] + { + new(0x00400000, 0x40400000), + new(0x20800000, 0x20801000), + }; + + InstEncoding[] sConstraints = new InstEncoding[] + { + new(0x00001000, 0x00001000), + }; + + InstEncoding[] opcodesizeOpcodesizeOpcodesizesOpcodesizeConstraints = new InstEncoding[] + { + new(0x00004400, 0x0000C400), + new(0x00008800, 0x0000C800), + new(0x00009400, 0x0000D400), + new(0x0000C000, 0x0000C000), + }; + + InstEncoding[] qsizeConstraints2 = new InstEncoding[] + { + new(0x00000C00, 0x40000C00), + }; + + InstEncoding[] rtRtConstraints = new InstEncoding[] + { + new(0x00000018, 0x00000018), + new(0x00000001, 0x00000001), + }; + + InstEncoding[] opc1sizeOpc1sizeOpc1sizeConstraints = new InstEncoding[] + { + new(0x40800000, 0xC0800000), + new(0x80800000, 0xC0800000), + new(0xC0800000, 0xC0800000), + }; + + InstEncoding[] rtRt2Constraints = new InstEncoding[] + { + new(0x0000001F, 0x0000001F), + new(0x001F0000, 0x001F0000), + }; + + InstEncoding[] opcConstraints = new InstEncoding[] + { + new(0xC0000000, 0xC0000000), + }; + + InstEncoding[] opcConstraints2 = new InstEncoding[] + { + new(0x40000000, 0x40000000), + }; + + InstEncoding[] opclOpcConstraints = new InstEncoding[] + { + new(0x40000000, 0x40400000), + new(0xC0000000, 0xC0000000), + }; + + InstEncoding[] optionConstraints = new InstEncoding[] + { + new(0x00000000, 0x00004000), + }; + + InstEncoding[] opc1sizeOpc1sizeOpc1sizeOptionConstraints = new InstEncoding[] + { + new(0x40800000, 0xC0800000), + new(0x80800000, 0xC0800000), + new(0xC0800000, 0xC0800000), + new(0x00000000, 0x00004000), + }; + + InstEncoding[] sizeSizeConstraints = new InstEncoding[] + { + new(0x00000000, 0x00C00000), + new(0x00C00000, 0x00C00000), + }; + + InstEncoding[] sfhwConstraints = new InstEncoding[] + { + new(0x00400000, 0x80400000), + }; + + InstEncoding[] rtConstraints = new InstEncoding[] + { + new(0x00000001, 0x00000001), + }; + + InstEncoding[] usizeUsizeUsizeSizeConstraints = new InstEncoding[] + { + new(0x20400000, 0x20C00000), + new(0x20800000, 0x20C00000), + new(0x20C00000, 0x20C00000), + new(0x00C00000, 0x00C00000), + }; + + InstEncoding[] sizeSizeConstraints2 = new InstEncoding[] + { + new(0x00400000, 0x00C00000), + new(0x00800000, 0x00C00000), + }; + + InstEncoding[] rtConstraints2 = new InstEncoding[] + { + new(0x00000018, 0x00000018), + }; + + InstEncoding[] sfopcConstraints = new InstEncoding[] + { + new(0x00000400, 0x80000400), + }; + + InstEncoding[] sizeSizeSizeConstraints = new InstEncoding[] + { + new(0x00400000, 0x00C00000), + new(0x00800000, 0x00C00000), + new(0x00C00000, 0x00C00000), + }; + + InstEncoding[] sizeSizeConstraints3 = new InstEncoding[] + { + new(0x00800000, 0x00C00000), + new(0x00C00000, 0x00C00000), + }; + + InstEncoding[] sfConstraints = new InstEncoding[] + { + new(0x00000000, 0x80000000), + }; + + InstEncoding[] immhImmhConstraints = new InstEncoding[] + { + new(0x00000000, 0x00780000), + new(0x00400000, 0x00400000), + }; + + InstEncoding[] sizeSizeConstraints4 = new InstEncoding[] + { + new(0x00C00000, 0x00C00000), + new(0x00000000, 0x00C00000), + }; + + InstEncoding[] ssizeSsizeSsizeConstraints = new InstEncoding[] + { + new(0x00000000, 0x00C00800), + new(0x00400000, 0x00C00800), + new(0x00800000, 0x00C00800), + }; + + InstEncoding[] immhOpuConstraints = new InstEncoding[] + { + new(0x00000000, 0x00780000), + new(0x00000000, 0x20001000), + }; + + InstEncoding[] immhQimmhOpuConstraints = new InstEncoding[] + { + new(0x00000000, 0x00780000), + new(0x00400000, 0x40400000), + new(0x00000000, 0x20001000), + }; + + List<InstInfo> insts = new() + { + new(0x5AC02000, 0x7FFFFC00, InstName.Abs, IsaVersion.v89, InstFlags.RdRn), + new(0x5EE0B800, 0xFFFFFC00, InstName.AbsAdvsimdS, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x0E20B800, 0xBF3FFC00, qsizeConstraints, InstName.AbsAdvsimdV, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x1A000000, 0x7FE0FC00, InstName.Adc, IsaVersion.v80, InstFlags.RdRnRmC), + new(0x3A000000, 0x7FE0FC00, InstName.Adcs, IsaVersion.v80, InstFlags.RdRnRmCS), + new(0x91800000, 0xFFC0C000, InstName.Addg, IsaVersion.v85, InstFlags.None), + new(0x0E204000, 0xBF20FC00, sizeConstraints, InstName.AddhnAdvsimd, IsaVersion.v80, InstFlags.RdReadRdRnRmFpSimd), + new(0x5EF1B800, 0xFFFFFC00, InstName.AddpAdvsimdPair, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x0E20BC00, 0xBF20FC00, qsizeConstraints, InstName.AddpAdvsimdVec, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x2B200000, 0x7FE00000, opuOpuOpuConstraints, InstName.AddsAddsubExt, IsaVersion.v80, InstFlags.RdRnSPRmS), + new(0x31000000, 0x7F800000, InstName.AddsAddsubImm, IsaVersion.v80, InstFlags.RdRnSPS), + new(0x2B000000, 0x7F200000, shiftSfimm6Constraints, InstName.AddsAddsubShift, IsaVersion.v80, InstFlags.RdRnRmS), + new(0x0E31B800, 0xBF3FFC00, qsizeSizeConstraints, InstName.AddvAdvsimd, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x0B200000, 0x7FE00000, opuOpuOpuConstraints, InstName.AddAddsubExt, IsaVersion.v80, InstFlags.RdSPRnSPRm), + new(0x11000000, 0x7F800000, InstName.AddAddsubImm, IsaVersion.v80, InstFlags.RdSPRnSP), + new(0x0B000000, 0x7F200000, shiftSfimm6Constraints, InstName.AddAddsubShift, IsaVersion.v80, InstFlags.RdRnRm), + new(0x5EE08400, 0xFFE0FC00, InstName.AddAdvsimdS, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x0E208400, 0xBF20FC00, qsizeConstraints, InstName.AddAdvsimdV, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x10000000, 0x9F000000, InstName.Adr, IsaVersion.v80, InstFlags.Rd, AddressForm.Literal), + new(0x90000000, 0x9F000000, InstName.Adrp, IsaVersion.v80, InstFlags.Rd, AddressForm.Literal), + new(0x4E285800, 0xFFFFFC00, InstName.AesdAdvsimd, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x4E284800, 0xFFFFFC00, InstName.AeseAdvsimd, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x4E287800, 0xFFFFFC00, InstName.AesimcAdvsimd, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x4E286800, 0xFFFFFC00, InstName.AesmcAdvsimd, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x72000000, 0x7F800000, nimmsNimmsNimmsNimmsNimmsNimmsNimmsNimmsSfnConstraints, InstName.AndsLogImm, IsaVersion.v80, InstFlags.RdRnS), + new(0x6A000000, 0x7F200000, sfimm6Constraints, InstName.AndsLogShift, IsaVersion.v80, InstFlags.RdRnRmS), + new(0x0E201C00, 0xBFE0FC00, InstName.AndAdvsimd, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x12000000, 0x7F800000, nimmsNimmsNimmsNimmsNimmsNimmsNimmsNimmsSfnConstraints, InstName.AndLogImm, IsaVersion.v80, InstFlags.RdSPRn), + new(0x0A000000, 0x7F200000, sfimm6Constraints, InstName.AndLogShift, IsaVersion.v80, InstFlags.RdRnRm), + new(0x1AC02800, 0x7FE0FC00, InstName.Asrv, IsaVersion.v80, InstFlags.RdRnRm), + new(0xDAC11800, 0xFFFFDC00, InstName.Autda, IsaVersion.v83, InstFlags.RdRnSP), + new(0xDAC11C00, 0xFFFFDC00, InstName.Autdb, IsaVersion.v83, InstFlags.RdRnSP), + new(0xDAC11000, 0xFFFFDC00, InstName.AutiaGeneral, IsaVersion.v83, InstFlags.RdRnSP), + new(0xD503219F, 0xFFFFFDDF, InstName.AutiaSystem, IsaVersion.v83, InstFlags.None), + new(0xDAC11400, 0xFFFFDC00, InstName.AutibGeneral, IsaVersion.v83, InstFlags.RdRnSP), + new(0xD50321DF, 0xFFFFFDDF, InstName.AutibSystem, IsaVersion.v83, InstFlags.None), + new(0xD500405F, 0xFFFFFFFF, InstName.Axflag, IsaVersion.v85, InstFlags.C), + new(0xCE200000, 0xFFE08000, InstName.BcaxAdvsimd, IsaVersion.v82, InstFlags.RdRnRmRaFpSimd), + new(0x54000010, 0xFF000010, InstName.BcCond, IsaVersion.v88, InstFlags.Nzcv), + new(0x0EA16800, 0xBFFFFC00, InstName.BfcvtnAdvsimd, IsaVersion.v86, InstFlags.RdRnFpSimd), + new(0x1E634000, 0xFFFFFC00, InstName.BfcvtFloat, IsaVersion.v86, InstFlags.RdRnFpSimd), + new(0x0F40F000, 0xBFC0F400, InstName.BfdotAdvsimdElt, IsaVersion.v86, InstFlags.RdReadRdRnRmFpSimd), + new(0x2E40FC00, 0xBFE0FC00, InstName.BfdotAdvsimdVec, IsaVersion.v86, InstFlags.RdReadRdRnRmFpSimd), + new(0x33000000, 0x7F800000, sfnSfnSfimmr5Sfimms5Constraints, InstName.Bfm, IsaVersion.v80, InstFlags.RdReadRdRn), + new(0x0FC0F000, 0xBFC0F400, InstName.BfmlalAdvsimdElt, IsaVersion.v86, InstFlags.RdRnRmFpSimd), + new(0x2EC0FC00, 0xBFE0FC00, InstName.BfmlalAdvsimdVec, IsaVersion.v86, InstFlags.RdRnRmFpSimd), + new(0x6E40EC00, 0xFFE0FC00, InstName.BfmmlaAdvsimd, IsaVersion.v86, InstFlags.RdRnRmFpSimd), + new(0x6A200000, 0x7F200000, sfimm6Constraints, InstName.Bics, IsaVersion.v80, InstFlags.RdRnRmS), + new(0x2F001400, 0xBFF81C00, cmodeopqConstraints, InstName.BicAdvsimdImm, IsaVersion.v80, InstFlags.RdFpSimd), + new(0x0E601C00, 0xBFE0FC00, InstName.BicAdvsimdReg, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x0A200000, 0x7F200000, sfimm6Constraints, InstName.BicLogShift, IsaVersion.v80, InstFlags.RdRnRm), + new(0x2EE01C00, 0xBFE0FC00, InstName.BifAdvsimd, IsaVersion.v80, InstFlags.RdReadRdRnRmFpSimd), + new(0x2EA01C00, 0xBFE0FC00, InstName.BitAdvsimd, IsaVersion.v80, InstFlags.RdReadRdRnRmFpSimd), + new(0x94000000, 0xFC000000, InstName.Bl, IsaVersion.v80, InstFlags.None), + new(0xD63F0000, 0xFFFFFC1F, InstName.Blr, IsaVersion.v80, InstFlags.Rn), + new(0xD63F0800, 0xFEFFF800, InstName.Blra, IsaVersion.v83, InstFlags.RnRm), + new(0xD61F0000, 0xFFFFFC1F, InstName.Br, IsaVersion.v80, InstFlags.Rn), + new(0xD61F0800, 0xFEFFF800, InstName.Bra, IsaVersion.v83, InstFlags.RnRm), + new(0xD4200000, 0xFFE0001F, InstName.Brk, IsaVersion.v80, InstFlags.None), + new(0x2E601C00, 0xBFE0FC00, InstName.BslAdvsimd, IsaVersion.v80, InstFlags.RdReadRdRnRmFpSimd), + new(0xD503241F, 0xFFFFFF3F, InstName.Bti, IsaVersion.v85, InstFlags.None), + new(0x54000000, 0xFF000010, InstName.BCond, IsaVersion.v80, InstFlags.Nzcv), + new(0x14000000, 0xFC000000, InstName.BUncond, IsaVersion.v80, InstFlags.None), + new(0x88A07C00, 0xBFA07C00, InstName.Cas, IsaVersion.v81, InstFlags.RtReadRtRnSPRs, AddressForm.BaseRegister), + new(0x08A07C00, 0xFFA07C00, InstName.Casb, IsaVersion.v81, InstFlags.RtReadRtRnSPRs, AddressForm.BaseRegister), + new(0x48A07C00, 0xFFA07C00, InstName.Cash, IsaVersion.v81, InstFlags.RtReadRtRnSPRs, AddressForm.BaseRegister), + new(0x08207C00, 0xBFA07C00, rsRtConstraints, InstName.Casp, IsaVersion.v81, InstFlags.RtReadRtRnSPRs, AddressForm.BaseRegister), + new(0x35000000, 0x7F000000, InstName.Cbnz, IsaVersion.v80, InstFlags.RtReadRt), + new(0x34000000, 0x7F000000, InstName.Cbz, IsaVersion.v80, InstFlags.RtReadRt), + new(0x3A400800, 0x7FE00C10, InstName.CcmnImm, IsaVersion.v80, InstFlags.RnNzcvS), + new(0x3A400000, 0x7FE00C10, InstName.CcmnReg, IsaVersion.v80, InstFlags.RnRmNzcvS), + new(0x7A400800, 0x7FE00C10, InstName.CcmpImm, IsaVersion.v80, InstFlags.RnNzcvS), + new(0x7A400000, 0x7FE00C10, InstName.CcmpReg, IsaVersion.v80, InstFlags.RnRmNzcvS), + new(0xD500401F, 0xFFFFFFFF, InstName.Cfinv, IsaVersion.v84, InstFlags.C), + new(0xD503251F, 0xFFFFFFFF, InstName.Chkfeat, IsaVersion.None, InstFlags.None), + new(0xD50322DF, 0xFFFFFFFF, InstName.Clrbhb, IsaVersion.v89, InstFlags.None), + new(0xD503305F, 0xFFFFF0FF, InstName.Clrex, IsaVersion.v80, InstFlags.None), + new(0x0E204800, 0xBF3FFC00, sizeConstraints, InstName.ClsAdvsimd, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x5AC01400, 0x7FFFFC00, InstName.ClsInt, IsaVersion.v80, InstFlags.RdRn), + new(0x2E204800, 0xBF3FFC00, sizeConstraints, InstName.ClzAdvsimd, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x5AC01000, 0x7FFFFC00, InstName.ClzInt, IsaVersion.v80, InstFlags.RdRn), + new(0x7EE08C00, 0xFFE0FC00, InstName.CmeqAdvsimdRegS, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x2E208C00, 0xBF20FC00, qsizeConstraints, InstName.CmeqAdvsimdRegV, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x5EE09800, 0xFFFFFC00, InstName.CmeqAdvsimdZeroS, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x0E209800, 0xBF3FFC00, qsizeConstraints, InstName.CmeqAdvsimdZeroV, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x5EE03C00, 0xFFE0FC00, InstName.CmgeAdvsimdRegS, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x0E203C00, 0xBF20FC00, qsizeConstraints, InstName.CmgeAdvsimdRegV, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x7EE08800, 0xFFFFFC00, InstName.CmgeAdvsimdZeroS, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x2E208800, 0xBF3FFC00, qsizeConstraints, InstName.CmgeAdvsimdZeroV, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x5EE03400, 0xFFE0FC00, InstName.CmgtAdvsimdRegS, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x0E203400, 0xBF20FC00, qsizeConstraints, InstName.CmgtAdvsimdRegV, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x5EE08800, 0xFFFFFC00, InstName.CmgtAdvsimdZeroS, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x0E208800, 0xBF3FFC00, qsizeConstraints, InstName.CmgtAdvsimdZeroV, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x7EE03400, 0xFFE0FC00, InstName.CmhiAdvsimdS, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x2E203400, 0xBF20FC00, qsizeConstraints, InstName.CmhiAdvsimdV, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x7EE03C00, 0xFFE0FC00, InstName.CmhsAdvsimdS, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x2E203C00, 0xBF20FC00, qsizeConstraints, InstName.CmhsAdvsimdV, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x7EE09800, 0xFFFFFC00, InstName.CmleAdvsimdS, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x2E209800, 0xBF3FFC00, qsizeConstraints, InstName.CmleAdvsimdV, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x5EE0A800, 0xFFFFFC00, InstName.CmltAdvsimdS, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x0E20A800, 0xBF3FFC00, qsizeConstraints, InstName.CmltAdvsimdV, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x5EE08C00, 0xFFE0FC00, InstName.CmtstAdvsimdS, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x0E208C00, 0xBF20FC00, qsizeConstraints, InstName.CmtstAdvsimdV, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x5AC01C00, 0x7FFFFC00, InstName.Cnt, IsaVersion.v89, InstFlags.RdRn), + new(0x0E205800, 0xBFFFFC00, InstName.CntAdvsimd, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x19000400, 0x3F20FC00, InstName.Cpyfp, IsaVersion.v88, InstFlags.RdRnRsS), + new(0x1900C400, 0x3F20FC00, InstName.Cpyfpn, IsaVersion.v88, InstFlags.RdRnRsS), + new(0x19008400, 0x3F20FC00, InstName.Cpyfprn, IsaVersion.v88, InstFlags.RdRnRsS), + new(0x19002400, 0x3F20FC00, InstName.Cpyfprt, IsaVersion.v88, InstFlags.RdRnRsS), + new(0x1900E400, 0x3F20FC00, InstName.Cpyfprtn, IsaVersion.v88, InstFlags.RdRnRsS), + new(0x1900A400, 0x3F20FC00, InstName.Cpyfprtrn, IsaVersion.v88, InstFlags.RdRnRsS), + new(0x19006400, 0x3F20FC00, InstName.Cpyfprtwn, IsaVersion.v88, InstFlags.RdRnRsS), + new(0x19003400, 0x3F20FC00, InstName.Cpyfpt, IsaVersion.v88, InstFlags.RdRnRsS), + new(0x1900F400, 0x3F20FC00, InstName.Cpyfptn, IsaVersion.v88, InstFlags.RdRnRsS), + new(0x1900B400, 0x3F20FC00, InstName.Cpyfptrn, IsaVersion.v88, InstFlags.RdRnRsS), + new(0x19007400, 0x3F20FC00, InstName.Cpyfptwn, IsaVersion.v88, InstFlags.RdRnRsS), + new(0x19004400, 0x3F20FC00, InstName.Cpyfpwn, IsaVersion.v88, InstFlags.RdRnRsS), + new(0x19001400, 0x3F20FC00, InstName.Cpyfpwt, IsaVersion.v88, InstFlags.RdRnRsS), + new(0x1900D400, 0x3F20FC00, InstName.Cpyfpwtn, IsaVersion.v88, InstFlags.RdRnRsS), + new(0x19009400, 0x3F20FC00, InstName.Cpyfpwtrn, IsaVersion.v88, InstFlags.RdRnRsS), + new(0x19005400, 0x3F20FC00, InstName.Cpyfpwtwn, IsaVersion.v88, InstFlags.RdRnRsS), + new(0x1D000400, 0x3F20FC00, InstName.Cpyp, IsaVersion.v88, InstFlags.RdRnRsS), + new(0x1D00C400, 0x3F20FC00, InstName.Cpypn, IsaVersion.v88, InstFlags.RdRnRsS), + new(0x1D008400, 0x3F20FC00, InstName.Cpyprn, IsaVersion.v88, InstFlags.RdRnRsS), + new(0x1D002400, 0x3F20FC00, InstName.Cpyprt, IsaVersion.v88, InstFlags.RdRnRsS), + new(0x1D00E400, 0x3F20FC00, InstName.Cpyprtn, IsaVersion.v88, InstFlags.RdRnRsS), + new(0x1D00A400, 0x3F20FC00, InstName.Cpyprtrn, IsaVersion.v88, InstFlags.RdRnRsS), + new(0x1D006400, 0x3F20FC00, InstName.Cpyprtwn, IsaVersion.v88, InstFlags.RdRnRsS), + new(0x1D003400, 0x3F20FC00, InstName.Cpypt, IsaVersion.v88, InstFlags.RdRnRsS), + new(0x1D00F400, 0x3F20FC00, InstName.Cpyptn, IsaVersion.v88, InstFlags.RdRnRsS), + new(0x1D00B400, 0x3F20FC00, InstName.Cpyptrn, IsaVersion.v88, InstFlags.RdRnRsS), + new(0x1D007400, 0x3F20FC00, InstName.Cpyptwn, IsaVersion.v88, InstFlags.RdRnRsS), + new(0x1D004400, 0x3F20FC00, InstName.Cpypwn, IsaVersion.v88, InstFlags.RdRnRsS), + new(0x1D001400, 0x3F20FC00, InstName.Cpypwt, IsaVersion.v88, InstFlags.RdRnRsS), + new(0x1D00D400, 0x3F20FC00, InstName.Cpypwtn, IsaVersion.v88, InstFlags.RdRnRsS), + new(0x1D009400, 0x3F20FC00, InstName.Cpypwtrn, IsaVersion.v88, InstFlags.RdRnRsS), + new(0x1D005400, 0x3F20FC00, InstName.Cpypwtwn, IsaVersion.v88, InstFlags.RdRnRsS), + new(0x1AC04000, 0x7FE0F000, sfszSfszSfszSfszConstraints, InstName.Crc32, IsaVersion.v80, InstFlags.RdRnRm), + new(0x1AC05000, 0x7FE0F000, sfszSfszSfszSfszConstraints, InstName.Crc32c, IsaVersion.v80, InstFlags.RdRnRm), + new(0xD503229F, 0xFFFFFFFF, InstName.Csdb, IsaVersion.v80, InstFlags.None), + new(0x1A800000, 0x7FE00C00, InstName.Csel, IsaVersion.v80, InstFlags.RdRnRmNzcv), + new(0x1A800400, 0x7FE00C00, InstName.Csinc, IsaVersion.v80, InstFlags.RdRnRmNzcv), + new(0x5A800000, 0x7FE00C00, InstName.Csinv, IsaVersion.v80, InstFlags.RdRnRmNzcv), + new(0x5A800400, 0x7FE00C00, InstName.Csneg, IsaVersion.v80, InstFlags.RdRnRmNzcv), + new(0x5AC01800, 0x7FFFFC00, InstName.Ctz, IsaVersion.v89, InstFlags.RdRn), + new(0xD4A00001, 0xFFE0001F, InstName.Dcps1, IsaVersion.v80, InstFlags.None), + new(0xD4A00002, 0xFFE0001F, InstName.Dcps2, IsaVersion.v80, InstFlags.None), + new(0xD4A00003, 0xFFE0001F, InstName.Dcps3, IsaVersion.v80, InstFlags.None), + new(0xD50320DF, 0xFFFFFFFF, InstName.Dgh, IsaVersion.v84, InstFlags.None), + new(0xD50330BF, 0xFFFFF0FF, InstName.Dmb, IsaVersion.v80, InstFlags.None), + new(0xD6BF03E0, 0xFFFFFFFF, InstName.Drps, IsaVersion.v80, InstFlags.None), + new(0xD503309F, 0xFFFFF0FF, InstName.DsbDsbMemory, IsaVersion.v80, InstFlags.None), + new(0xD503323F, 0xFFFFF3FF, InstName.DsbDsbNxs, IsaVersion.v87, InstFlags.None), + new(0x5E000400, 0xFFE0FC00, imm5Constraints, InstName.DupAdvsimdEltScalarFromElement, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x0E000400, 0xBFE0FC00, imm5Imm5qConstraints, InstName.DupAdvsimdEltVectorFromElement, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x0E000C00, 0xBFE0FC00, imm5Imm5qConstraints, InstName.DupAdvsimdGen, IsaVersion.v80, InstFlags.RdRnFpSimdFromGpr), + new(0x4A200000, 0x7F200000, sfimm6Constraints, InstName.Eon, IsaVersion.v80, InstFlags.RdRnRm), + new(0xCE000000, 0xFFE08000, InstName.Eor3Advsimd, IsaVersion.v82, InstFlags.RdRnRmRaFpSimd), + new(0x2E201C00, 0xBFE0FC00, InstName.EorAdvsimd, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x52000000, 0x7F800000, nimmsNimmsNimmsNimmsNimmsNimmsNimmsNimmsSfnConstraints, InstName.EorLogImm, IsaVersion.v80, InstFlags.RdSPRn), + new(0x4A000000, 0x7F200000, sfimm6Constraints, InstName.EorLogShift, IsaVersion.v80, InstFlags.RdRnRm), + new(0xD69F03E0, 0xFFFFFFFF, InstName.Eret, IsaVersion.v80, InstFlags.None), + new(0xD69F0BFF, 0xFFFFFBFF, InstName.Ereta, IsaVersion.v83, InstFlags.None), + new(0xD503221F, 0xFFFFFFFF, InstName.Esb, IsaVersion.v82, InstFlags.None), + new(0x13800000, 0x7FA00000, nsfNsfSfimmsConstraints, InstName.Extr, IsaVersion.v80, InstFlags.RdRnRm), + new(0x2E000000, 0xBFE08400, qimm4Constraints, InstName.ExtAdvsimd, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x7EC01400, 0xFFE0FC00, InstName.FabdAdvsimdSH, IsaVersion.v82, InstFlags.RdRnRmFpSimd), + new(0x7EA0D400, 0xFFA0FC00, InstName.FabdAdvsimdS, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x2EC01400, 0xBFE0FC00, InstName.FabdAdvsimdVH, IsaVersion.v82, InstFlags.RdRnRmFpSimd), + new(0x2EA0D400, 0xBFA0FC00, qszConstraints, InstName.FabdAdvsimdV, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x0EF8F800, 0xBFFFFC00, InstName.FabsAdvsimdHalf, IsaVersion.v82, InstFlags.RdRnFpSimd), + new(0x0EA0F800, 0xBFBFFC00, qszConstraints, InstName.FabsAdvsimdSingleAndDouble, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x1E20C000, 0xFFBFFC00, InstName.FabsFloat, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x1EE0C000, 0xFFFFFC00, InstName.FabsFloat, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x7E402C00, 0xFFE0FC00, euacEuacEuacConstraints, InstName.FacgeAdvsimdSH, IsaVersion.v82, InstFlags.RdRnRmFpSimd), + new(0x7E20EC00, 0xFFA0FC00, euacEuacEuacConstraints, InstName.FacgeAdvsimdS, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x2E402C00, 0xBFE0FC00, euacEuacEuacConstraints, InstName.FacgeAdvsimdVH, IsaVersion.v82, InstFlags.RdRnRmFpSimd), + new(0x2E20EC00, 0xBFA0FC00, qszEuacEuacEuacConstraints, InstName.FacgeAdvsimdV, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x7EC02C00, 0xFFE0FC00, euacEuacEuacConstraints, InstName.FacgtAdvsimdSH, IsaVersion.v82, InstFlags.RdRnRmFpSimd), + new(0x7EA0EC00, 0xFFA0FC00, euacEuacEuacConstraints, InstName.FacgtAdvsimdS, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x2EC02C00, 0xBFE0FC00, euacEuacEuacConstraints, InstName.FacgtAdvsimdVH, IsaVersion.v82, InstFlags.RdRnRmFpSimd), + new(0x2EA0EC00, 0xBFA0FC00, qszEuacEuacEuacConstraints, InstName.FacgtAdvsimdV, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x5E30D800, 0xFFBFFC00, szConstraints, InstName.FaddpAdvsimdPairHalf, IsaVersion.v82, InstFlags.RdRnFpSimd), + new(0x7E30D800, 0xFFBFFC00, InstName.FaddpAdvsimdPairSingleAndDouble, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x2E401400, 0xBFE0FC00, InstName.FaddpAdvsimdVecHalf, IsaVersion.v82, InstFlags.RdRnRmFpSimd), + new(0x2E20D400, 0xBFA0FC00, qszConstraints, InstName.FaddpAdvsimdVecSingleAndDouble, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x0E401400, 0xBFE0FC00, InstName.FaddAdvsimdHalf, IsaVersion.v82, InstFlags.RdRnRmFpSimd), + new(0x0E20D400, 0xBFA0FC00, qszConstraints, InstName.FaddAdvsimdSingleAndDouble, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x1E202800, 0xFFA0FC00, InstName.FaddFloat, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x1EE02800, 0xFFE0FC00, InstName.FaddFloat, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x2E80E400, 0xBFA0EC00, sizeQsizeConstraints, InstName.FcaddAdvsimdVec, IsaVersion.v83, InstFlags.RdRnRmFpSimd), + new(0x2E40E400, 0xBFE0EC00, sizeQsizeConstraints, InstName.FcaddAdvsimdVec, IsaVersion.v83, InstFlags.RdRnRmFpSimd), + new(0x1E200410, 0xFFA00C10, InstName.FccmpeFloat, IsaVersion.v80, InstFlags.RnRmNzcvSFpSimd), + new(0x1EE00410, 0xFFE00C10, InstName.FccmpeFloat, IsaVersion.v80, InstFlags.RnRmNzcvSFpSimd), + new(0x1E200400, 0xFFA00C10, InstName.FccmpFloat, IsaVersion.v80, InstFlags.RnRmNzcvSFpSimd), + new(0x1EE00400, 0xFFE00C10, InstName.FccmpFloat, IsaVersion.v80, InstFlags.RnRmNzcvSFpSimd), + new(0x5E402400, 0xFFE0FC00, euacEuacEuacConstraints, InstName.FcmeqAdvsimdRegSH, IsaVersion.v82, InstFlags.RdRnRmFpSimd), + new(0x5E20E400, 0xFFA0FC00, euacEuacEuacConstraints, InstName.FcmeqAdvsimdRegS, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x0E402400, 0xBFE0FC00, euacEuacEuacConstraints, InstName.FcmeqAdvsimdRegVH, IsaVersion.v82, InstFlags.RdRnRmFpSimd), + new(0x0E20E400, 0xBFA0FC00, qszEuacEuacEuacConstraints, InstName.FcmeqAdvsimdRegV, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x5EF8D800, 0xFFFFFC00, InstName.FcmeqAdvsimdZeroSH, IsaVersion.v82, InstFlags.RdRnFpSimd), + new(0x5EA0D800, 0xFFBFFC00, InstName.FcmeqAdvsimdZeroS, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x0EF8D800, 0xBFFFFC00, InstName.FcmeqAdvsimdZeroVH, IsaVersion.v82, InstFlags.RdRnFpSimd), + new(0x0EA0D800, 0xBFBFFC00, qszConstraints, InstName.FcmeqAdvsimdZeroV, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x7E402400, 0xFFE0FC00, euacEuacEuacConstraints, InstName.FcmgeAdvsimdRegSH, IsaVersion.v82, InstFlags.RdRnRmFpSimd), + new(0x7E20E400, 0xFFA0FC00, euacEuacEuacConstraints, InstName.FcmgeAdvsimdRegS, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x2E402400, 0xBFE0FC00, euacEuacEuacConstraints, InstName.FcmgeAdvsimdRegVH, IsaVersion.v82, InstFlags.RdRnRmFpSimd), + new(0x2E20E400, 0xBFA0FC00, qszEuacEuacEuacConstraints, InstName.FcmgeAdvsimdRegV, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x7EF8C800, 0xFFFFFC00, InstName.FcmgeAdvsimdZeroSH, IsaVersion.v82, InstFlags.RdRnFpSimd), + new(0x7EA0C800, 0xFFBFFC00, InstName.FcmgeAdvsimdZeroS, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x2EF8C800, 0xBFFFFC00, InstName.FcmgeAdvsimdZeroVH, IsaVersion.v82, InstFlags.RdRnFpSimd), + new(0x2EA0C800, 0xBFBFFC00, qszConstraints, InstName.FcmgeAdvsimdZeroV, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x7EC02400, 0xFFE0FC00, euacEuacEuacConstraints, InstName.FcmgtAdvsimdRegSH, IsaVersion.v82, InstFlags.RdRnRmFpSimd), + new(0x7EA0E400, 0xFFA0FC00, euacEuacEuacConstraints, InstName.FcmgtAdvsimdRegS, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x2EC02400, 0xBFE0FC00, euacEuacEuacConstraints, InstName.FcmgtAdvsimdRegVH, IsaVersion.v82, InstFlags.RdRnRmFpSimd), + new(0x2EA0E400, 0xBFA0FC00, qszEuacEuacEuacConstraints, InstName.FcmgtAdvsimdRegV, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x5EF8C800, 0xFFFFFC00, InstName.FcmgtAdvsimdZeroSH, IsaVersion.v82, InstFlags.RdRnFpSimd), + new(0x5EA0C800, 0xFFBFFC00, InstName.FcmgtAdvsimdZeroS, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x0EF8C800, 0xBFFFFC00, InstName.FcmgtAdvsimdZeroVH, IsaVersion.v82, InstFlags.RdRnFpSimd), + new(0x0EA0C800, 0xBFBFFC00, qszConstraints, InstName.FcmgtAdvsimdZeroV, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x2F801000, 0xBF809400, sizeSizeSizelSizeqSizehqConstraints, InstName.FcmlaAdvsimdElt, IsaVersion.v83, InstFlags.RdReadRdRnRmFpSimd), + new(0x2F401000, 0xBFC09400, sizeSizeSizelSizeqSizehqConstraints, InstName.FcmlaAdvsimdElt, IsaVersion.v83, InstFlags.RdReadRdRnRmFpSimd), + new(0x2E80C400, 0xBFA0E400, sizeQsizeConstraints, InstName.FcmlaAdvsimdVec, IsaVersion.v83, InstFlags.RdReadRdRnRmFpSimd), + new(0x2E40C400, 0xBFE0E400, sizeQsizeConstraints, InstName.FcmlaAdvsimdVec, IsaVersion.v83, InstFlags.RdReadRdRnRmFpSimd), + new(0x7EF8D800, 0xFFFFFC00, InstName.FcmleAdvsimdSH, IsaVersion.v82, InstFlags.RdRnFpSimd), + new(0x7EA0D800, 0xFFBFFC00, InstName.FcmleAdvsimdS, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x2EF8D800, 0xBFFFFC00, InstName.FcmleAdvsimdVH, IsaVersion.v82, InstFlags.RdRnFpSimd), + new(0x2EA0D800, 0xBFBFFC00, qszConstraints, InstName.FcmleAdvsimdV, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x5EF8E800, 0xFFFFFC00, InstName.FcmltAdvsimdSH, IsaVersion.v82, InstFlags.RdRnFpSimd), + new(0x5EA0E800, 0xFFBFFC00, InstName.FcmltAdvsimdS, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x0EF8E800, 0xBFFFFC00, InstName.FcmltAdvsimdVH, IsaVersion.v82, InstFlags.RdRnFpSimd), + new(0x0EA0E800, 0xBFBFFC00, qszConstraints, InstName.FcmltAdvsimdV, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x1E202010, 0xFFA0FC17, InstName.FcmpeFloat, IsaVersion.v80, InstFlags.RnRmSFpSimd), + new(0x1EE02010, 0xFFE0FC17, InstName.FcmpeFloat, IsaVersion.v80, InstFlags.RnRmSFpSimd), + new(0x1E202000, 0xFFA0FC17, InstName.FcmpFloat, IsaVersion.v80, InstFlags.RnRmSFpSimd), + new(0x1EE02000, 0xFFE0FC17, InstName.FcmpFloat, IsaVersion.v80, InstFlags.RnRmSFpSimd), + new(0x1E200C00, 0xFFA00C00, InstName.FcselFloat, IsaVersion.v80, InstFlags.RdRnRmNzcvFpSimd), + new(0x1EE00C00, 0xFFE00C00, InstName.FcselFloat, IsaVersion.v80, InstFlags.RdRnRmNzcvFpSimd), + new(0x5E79C800, 0xFFFFFC00, InstName.FcvtasAdvsimdSH, IsaVersion.v82, InstFlags.RdRnFpSimd), + new(0x5E21C800, 0xFFBFFC00, InstName.FcvtasAdvsimdS, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x0E79C800, 0xBFFFFC00, InstName.FcvtasAdvsimdVH, IsaVersion.v82, InstFlags.RdRnFpSimd), + new(0x0E21C800, 0xBFBFFC00, qszConstraints, InstName.FcvtasAdvsimdV, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x1E240000, 0x7FBFFC00, InstName.FcvtasFloat, IsaVersion.v80, InstFlags.RdRnFpSimdToGpr), + new(0x1EE40000, 0x7FFFFC00, InstName.FcvtasFloat, IsaVersion.v80, InstFlags.RdRnFpSimdToGpr), + new(0x7E79C800, 0xFFFFFC00, InstName.FcvtauAdvsimdSH, IsaVersion.v82, InstFlags.RdRnFpSimd), + new(0x7E21C800, 0xFFBFFC00, InstName.FcvtauAdvsimdS, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x2E79C800, 0xBFFFFC00, InstName.FcvtauAdvsimdVH, IsaVersion.v82, InstFlags.RdRnFpSimd), + new(0x2E21C800, 0xBFBFFC00, qszConstraints, InstName.FcvtauAdvsimdV, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x1E250000, 0x7FBFFC00, InstName.FcvtauFloat, IsaVersion.v80, InstFlags.RdRnFpSimdToGpr), + new(0x1EE50000, 0x7FFFFC00, InstName.FcvtauFloat, IsaVersion.v80, InstFlags.RdRnFpSimdToGpr), + new(0x0E217800, 0xBFBFFC00, InstName.FcvtlAdvsimd, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x5E79B800, 0xFFFFFC00, InstName.FcvtmsAdvsimdSH, IsaVersion.v82, InstFlags.RdRnFpSimd), + new(0x5E21B800, 0xFFBFFC00, InstName.FcvtmsAdvsimdS, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x0E79B800, 0xBFFFFC00, InstName.FcvtmsAdvsimdVH, IsaVersion.v82, InstFlags.RdRnFpSimd), + new(0x0E21B800, 0xBFBFFC00, qszConstraints, InstName.FcvtmsAdvsimdV, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x1E300000, 0x7FBFFC00, InstName.FcvtmsFloat, IsaVersion.v80, InstFlags.RdRnFpSimdToGpr), + new(0x1EF00000, 0x7FFFFC00, InstName.FcvtmsFloat, IsaVersion.v80, InstFlags.RdRnFpSimdToGpr), + new(0x7E79B800, 0xFFFFFC00, InstName.FcvtmuAdvsimdSH, IsaVersion.v82, InstFlags.RdRnFpSimd), + new(0x7E21B800, 0xFFBFFC00, InstName.FcvtmuAdvsimdS, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x2E79B800, 0xBFFFFC00, InstName.FcvtmuAdvsimdVH, IsaVersion.v82, InstFlags.RdRnFpSimd), + new(0x2E21B800, 0xBFBFFC00, qszConstraints, InstName.FcvtmuAdvsimdV, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x1E310000, 0x7FBFFC00, InstName.FcvtmuFloat, IsaVersion.v80, InstFlags.RdRnFpSimdToGpr), + new(0x1EF10000, 0x7FFFFC00, InstName.FcvtmuFloat, IsaVersion.v80, InstFlags.RdRnFpSimdToGpr), + new(0x5E79A800, 0xFFFFFC00, InstName.FcvtnsAdvsimdSH, IsaVersion.v82, InstFlags.RdRnFpSimd), + new(0x5E21A800, 0xFFBFFC00, InstName.FcvtnsAdvsimdS, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x0E79A800, 0xBFFFFC00, InstName.FcvtnsAdvsimdVH, IsaVersion.v82, InstFlags.RdRnFpSimd), + new(0x0E21A800, 0xBFBFFC00, qszConstraints, InstName.FcvtnsAdvsimdV, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x1E200000, 0x7FBFFC00, InstName.FcvtnsFloat, IsaVersion.v80, InstFlags.RdRnFpSimdToGpr), + new(0x1EE00000, 0x7FFFFC00, InstName.FcvtnsFloat, IsaVersion.v80, InstFlags.RdRnFpSimdToGpr), + new(0x7E79A800, 0xFFFFFC00, InstName.FcvtnuAdvsimdSH, IsaVersion.v82, InstFlags.RdRnFpSimd), + new(0x7E21A800, 0xFFBFFC00, InstName.FcvtnuAdvsimdS, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x2E79A800, 0xBFFFFC00, InstName.FcvtnuAdvsimdVH, IsaVersion.v82, InstFlags.RdRnFpSimd), + new(0x2E21A800, 0xBFBFFC00, qszConstraints, InstName.FcvtnuAdvsimdV, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x1E210000, 0x7FBFFC00, InstName.FcvtnuFloat, IsaVersion.v80, InstFlags.RdRnFpSimdToGpr), + new(0x1EE10000, 0x7FFFFC00, InstName.FcvtnuFloat, IsaVersion.v80, InstFlags.RdRnFpSimdToGpr), + new(0x0E216800, 0xBFBFFC00, InstName.FcvtnAdvsimd, IsaVersion.v80, InstFlags.RdReadRdRnFpSimd), + new(0x5EF9A800, 0xFFFFFC00, InstName.FcvtpsAdvsimdSH, IsaVersion.v82, InstFlags.RdRnFpSimd), + new(0x5EA1A800, 0xFFBFFC00, InstName.FcvtpsAdvsimdS, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x0EF9A800, 0xBFFFFC00, InstName.FcvtpsAdvsimdVH, IsaVersion.v82, InstFlags.RdRnFpSimd), + new(0x0EA1A800, 0xBFBFFC00, qszConstraints, InstName.FcvtpsAdvsimdV, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x1E280000, 0x7FBFFC00, InstName.FcvtpsFloat, IsaVersion.v80, InstFlags.RdRnFpSimdToGpr), + new(0x1EE80000, 0x7FFFFC00, InstName.FcvtpsFloat, IsaVersion.v80, InstFlags.RdRnFpSimdToGpr), + new(0x7EF9A800, 0xFFFFFC00, InstName.FcvtpuAdvsimdSH, IsaVersion.v82, InstFlags.RdRnFpSimd), + new(0x7EA1A800, 0xFFBFFC00, InstName.FcvtpuAdvsimdS, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x2EF9A800, 0xBFFFFC00, InstName.FcvtpuAdvsimdVH, IsaVersion.v82, InstFlags.RdRnFpSimd), + new(0x2EA1A800, 0xBFBFFC00, qszConstraints, InstName.FcvtpuAdvsimdV, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x1E290000, 0x7FBFFC00, InstName.FcvtpuFloat, IsaVersion.v80, InstFlags.RdRnFpSimdToGpr), + new(0x1EE90000, 0x7FFFFC00, InstName.FcvtpuFloat, IsaVersion.v80, InstFlags.RdRnFpSimdToGpr), + new(0x7E216800, 0xFFBFFC00, szConstraints2, InstName.FcvtxnAdvsimdS, IsaVersion.v80, InstFlags.RdReadRdRnFpSimd), + new(0x2E216800, 0xBFBFFC00, szConstraints2, InstName.FcvtxnAdvsimdV, IsaVersion.v80, InstFlags.RdReadRdRnFpSimd), + new(0x5F40FC00, 0xFFC0FC00, immhConstraints, InstName.FcvtzsAdvsimdFixS, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x5F10FC00, 0xFFF0FC00, immhConstraints, InstName.FcvtzsAdvsimdFixS, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x5F20FC00, 0xFFE0FC00, immhConstraints, InstName.FcvtzsAdvsimdFixS, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x0F40FC00, 0xBFC0FC00, immhQimmhConstraints, InstName.FcvtzsAdvsimdFixV, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x0F10FC00, 0xBFF0FC00, immhQimmhConstraints, InstName.FcvtzsAdvsimdFixV, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x0F20FC00, 0xBFE0FC00, immhQimmhConstraints, InstName.FcvtzsAdvsimdFixV, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x5EF9B800, 0xFFFFFC00, InstName.FcvtzsAdvsimdIntSH, IsaVersion.v82, InstFlags.RdRnFpSimd), + new(0x5EA1B800, 0xFFBFFC00, InstName.FcvtzsAdvsimdIntS, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x0EF9B800, 0xBFFFFC00, InstName.FcvtzsAdvsimdIntVH, IsaVersion.v82, InstFlags.RdRnFpSimd), + new(0x0EA1B800, 0xBFBFFC00, qszConstraints, InstName.FcvtzsAdvsimdIntV, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x1E180000, 0x7FBF0000, sfscaleConstraints, InstName.FcvtzsFloatFix, IsaVersion.v80, InstFlags.RdRnFpSimdToGpr), + new(0x1ED80000, 0x7FFF0000, sfscaleConstraints, InstName.FcvtzsFloatFix, IsaVersion.v80, InstFlags.RdRnFpSimdToGpr), + new(0x1E380000, 0x7FBFFC00, InstName.FcvtzsFloatInt, IsaVersion.v80, InstFlags.RdRnFpSimdToGpr), + new(0x1EF80000, 0x7FFFFC00, InstName.FcvtzsFloatInt, IsaVersion.v80, InstFlags.RdRnFpSimdToGpr), + new(0x7F40FC00, 0xFFC0FC00, immhConstraints, InstName.FcvtzuAdvsimdFixS, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x7F10FC00, 0xFFF0FC00, immhConstraints, InstName.FcvtzuAdvsimdFixS, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x7F20FC00, 0xFFE0FC00, immhConstraints, InstName.FcvtzuAdvsimdFixS, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x2F40FC00, 0xBFC0FC00, immhQimmhConstraints, InstName.FcvtzuAdvsimdFixV, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x2F10FC00, 0xBFF0FC00, immhQimmhConstraints, InstName.FcvtzuAdvsimdFixV, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x2F20FC00, 0xBFE0FC00, immhQimmhConstraints, InstName.FcvtzuAdvsimdFixV, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x7EF9B800, 0xFFFFFC00, InstName.FcvtzuAdvsimdIntSH, IsaVersion.v82, InstFlags.RdRnFpSimd), + new(0x7EA1B800, 0xFFBFFC00, InstName.FcvtzuAdvsimdIntS, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x2EF9B800, 0xBFFFFC00, InstName.FcvtzuAdvsimdIntVH, IsaVersion.v82, InstFlags.RdRnFpSimd), + new(0x2EA1B800, 0xBFBFFC00, qszConstraints, InstName.FcvtzuAdvsimdIntV, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x1E190000, 0x7FBF0000, sfscaleConstraints, InstName.FcvtzuFloatFix, IsaVersion.v80, InstFlags.RdRnFpSimdToGpr), + new(0x1ED90000, 0x7FFF0000, sfscaleConstraints, InstName.FcvtzuFloatFix, IsaVersion.v80, InstFlags.RdRnFpSimdToGpr), + new(0x1E390000, 0x7FBFFC00, InstName.FcvtzuFloatInt, IsaVersion.v80, InstFlags.RdRnFpSimdToGpr), + new(0x1EF90000, 0x7FFFFC00, InstName.FcvtzuFloatInt, IsaVersion.v80, InstFlags.RdRnFpSimdToGpr), + new(0x1E224000, 0xFF3E7C00, ftypeopcFtypeopcFtypeopcFtypeopcFtypeOpcConstraints, InstName.FcvtFloat, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x2E403C00, 0xBFE0FC00, InstName.FdivAdvsimdHalf, IsaVersion.v82, InstFlags.RdRnRmFpSimd), + new(0x2E20FC00, 0xBFA0FC00, qszConstraints, InstName.FdivAdvsimdSingleAndDouble, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x1E201800, 0xFFA0FC00, InstName.FdivFloat, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x1EE01800, 0xFFE0FC00, InstName.FdivFloat, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x1E7E0000, 0xFFFFFC00, InstName.Fjcvtzs, IsaVersion.v83, InstFlags.RdRnSFpSimd), + new(0x1F000000, 0xFFA08000, InstName.FmaddFloat, IsaVersion.v80, InstFlags.RdRnRmRaFpSimd), + new(0x1FC00000, 0xFFE08000, InstName.FmaddFloat, IsaVersion.v80, InstFlags.RdRnRmRaFpSimd), + new(0x5E30C800, 0xFFBFFC00, szConstraints, InstName.FmaxnmpAdvsimdPairHalf, IsaVersion.v82, InstFlags.RdRnFpSimd), + new(0x7E30C800, 0xFFBFFC00, InstName.FmaxnmpAdvsimdPairSingleAndDouble, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x2E400400, 0xBFE0FC00, InstName.FmaxnmpAdvsimdVecHalf, IsaVersion.v82, InstFlags.RdRnRmFpSimd), + new(0x2E20C400, 0xBFA0FC00, qszConstraints, InstName.FmaxnmpAdvsimdVecSingleAndDouble, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x0E30C800, 0xBFFFFC00, InstName.FmaxnmvAdvsimdHalf, IsaVersion.v82, InstFlags.RdRnFpSimd), + new(0x6E30C800, 0xFFFFFC00, InstName.FmaxnmvAdvsimdSingleAndDouble, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x0E400400, 0xBFE0FC00, InstName.FmaxnmAdvsimdHalf, IsaVersion.v82, InstFlags.RdRnRmFpSimd), + new(0x0E20C400, 0xBFA0FC00, qszConstraints, InstName.FmaxnmAdvsimdSingleAndDouble, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x1E206800, 0xFFA0FC00, InstName.FmaxnmFloat, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x1EE06800, 0xFFE0FC00, InstName.FmaxnmFloat, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x5E30F800, 0xFFBFFC00, szConstraints, InstName.FmaxpAdvsimdPairHalf, IsaVersion.v82, InstFlags.RdRnFpSimd), + new(0x7E30F800, 0xFFBFFC00, InstName.FmaxpAdvsimdPairSingleAndDouble, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x2E403400, 0xBFE0FC00, InstName.FmaxpAdvsimdVecHalf, IsaVersion.v82, InstFlags.RdRnRmFpSimd), + new(0x2E20F400, 0xBFA0FC00, qszConstraints, InstName.FmaxpAdvsimdVecSingleAndDouble, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x0E30F800, 0xBFFFFC00, InstName.FmaxvAdvsimdHalf, IsaVersion.v82, InstFlags.RdRnFpSimd), + new(0x6E30F800, 0xFFFFFC00, InstName.FmaxvAdvsimdSingleAndDouble, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x0E403400, 0xBFE0FC00, InstName.FmaxAdvsimdHalf, IsaVersion.v82, InstFlags.RdRnRmFpSimd), + new(0x0E20F400, 0xBFA0FC00, qszConstraints, InstName.FmaxAdvsimdSingleAndDouble, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x1E204800, 0xFFA0FC00, InstName.FmaxFloat, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x1EE04800, 0xFFE0FC00, InstName.FmaxFloat, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x5EB0C800, 0xFFBFFC00, szConstraints, InstName.FminnmpAdvsimdPairHalf, IsaVersion.v82, InstFlags.RdRnFpSimd), + new(0x7EB0C800, 0xFFBFFC00, InstName.FminnmpAdvsimdPairSingleAndDouble, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x2EC00400, 0xBFE0FC00, InstName.FminnmpAdvsimdVecHalf, IsaVersion.v82, InstFlags.RdRnRmFpSimd), + new(0x2EA0C400, 0xBFA0FC00, qszConstraints, InstName.FminnmpAdvsimdVecSingleAndDouble, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x0EB0C800, 0xBFFFFC00, InstName.FminnmvAdvsimdHalf, IsaVersion.v82, InstFlags.RdRnFpSimd), + new(0x6EB0C800, 0xFFFFFC00, InstName.FminnmvAdvsimdSingleAndDouble, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x0EC00400, 0xBFE0FC00, InstName.FminnmAdvsimdHalf, IsaVersion.v82, InstFlags.RdRnRmFpSimd), + new(0x0EA0C400, 0xBFA0FC00, qszConstraints, InstName.FminnmAdvsimdSingleAndDouble, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x1E207800, 0xFFA0FC00, InstName.FminnmFloat, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x1EE07800, 0xFFE0FC00, InstName.FminnmFloat, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x5EB0F800, 0xFFBFFC00, szConstraints, InstName.FminpAdvsimdPairHalf, IsaVersion.v82, InstFlags.RdRnFpSimd), + new(0x7EB0F800, 0xFFBFFC00, InstName.FminpAdvsimdPairSingleAndDouble, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x2EC03400, 0xBFE0FC00, InstName.FminpAdvsimdVecHalf, IsaVersion.v82, InstFlags.RdRnRmFpSimd), + new(0x2EA0F400, 0xBFA0FC00, qszConstraints, InstName.FminpAdvsimdVecSingleAndDouble, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x0EB0F800, 0xBFFFFC00, InstName.FminvAdvsimdHalf, IsaVersion.v82, InstFlags.RdRnFpSimd), + new(0x6EB0F800, 0xFFFFFC00, InstName.FminvAdvsimdSingleAndDouble, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x0EC03400, 0xBFE0FC00, InstName.FminAdvsimdHalf, IsaVersion.v82, InstFlags.RdRnRmFpSimd), + new(0x0EA0F400, 0xBFA0FC00, qszConstraints, InstName.FminAdvsimdSingleAndDouble, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x1E205800, 0xFFA0FC00, InstName.FminFloat, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x1EE05800, 0xFFE0FC00, InstName.FminFloat, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x0F800000, 0xBFC0F400, szConstraints, InstName.FmlalAdvsimdEltFmlal, IsaVersion.v82, InstFlags.RdReadRdRnRmFpSimd), + new(0x2F808000, 0xBFC0F400, szConstraints, InstName.FmlalAdvsimdEltFmlal2, IsaVersion.v82, InstFlags.RdReadRdRnRmFpSimd), + new(0x0E20EC00, 0xBFE0FC00, szConstraints, InstName.FmlalAdvsimdVecFmlal, IsaVersion.v82, InstFlags.RdReadRdRnRmFpSimd), + new(0x2E20CC00, 0xBFE0FC00, szConstraints, InstName.FmlalAdvsimdVecFmlal2, IsaVersion.v82, InstFlags.RdReadRdRnRmFpSimd), + new(0x5F001000, 0xFFC0F400, InstName.FmlaAdvsimdElt2regScalarHalf, IsaVersion.v82, InstFlags.RdReadRdRnRmFpSimd), + new(0x5F801000, 0xFF80F400, szlConstraints, InstName.FmlaAdvsimdElt2regScalarSingleAndDouble, IsaVersion.v80, InstFlags.RdReadRdRnRmFpSimd), + new(0x0F001000, 0xBFC0F400, InstName.FmlaAdvsimdElt2regElementHalf, IsaVersion.v82, InstFlags.RdReadRdRnRmFpSimd), + new(0x0F801000, 0xBF80F400, szlQszConstraints, InstName.FmlaAdvsimdElt2regElementSingleAndDouble, IsaVersion.v80, InstFlags.RdReadRdRnRmFpSimd), + new(0x0E400C00, 0xBFE0FC00, InstName.FmlaAdvsimdVecHalf, IsaVersion.v82, InstFlags.RdReadRdRnRmFpSimd), + new(0x0E20CC00, 0xBFA0FC00, qszConstraints, InstName.FmlaAdvsimdVecSingleAndDouble, IsaVersion.v80, InstFlags.RdReadRdRnRmFpSimd), + new(0x0F804000, 0xBFC0F400, szConstraints, InstName.FmlslAdvsimdEltFmlsl, IsaVersion.v82, InstFlags.RdReadRdRnRmFpSimd), + new(0x2F80C000, 0xBFC0F400, szConstraints, InstName.FmlslAdvsimdEltFmlsl2, IsaVersion.v82, InstFlags.RdReadRdRnRmFpSimd), + new(0x0EA0EC00, 0xBFE0FC00, szConstraints, InstName.FmlslAdvsimdVecFmlsl, IsaVersion.v82, InstFlags.RdReadRdRnRmFpSimd), + new(0x2EA0CC00, 0xBFE0FC00, szConstraints, InstName.FmlslAdvsimdVecFmlsl2, IsaVersion.v82, InstFlags.RdReadRdRnRmFpSimd), + new(0x5F005000, 0xFFC0F400, InstName.FmlsAdvsimdElt2regScalarHalf, IsaVersion.v82, InstFlags.RdReadRdRnRmFpSimd), + new(0x5F805000, 0xFF80F400, szlConstraints, InstName.FmlsAdvsimdElt2regScalarSingleAndDouble, IsaVersion.v80, InstFlags.RdReadRdRnRmFpSimd), + new(0x0F005000, 0xBFC0F400, InstName.FmlsAdvsimdElt2regElementHalf, IsaVersion.v82, InstFlags.RdReadRdRnRmFpSimd), + new(0x0F805000, 0xBF80F400, szlQszConstraints, InstName.FmlsAdvsimdElt2regElementSingleAndDouble, IsaVersion.v80, InstFlags.RdReadRdRnRmFpSimd), + new(0x0EC00C00, 0xBFE0FC00, InstName.FmlsAdvsimdVecHalf, IsaVersion.v82, InstFlags.RdReadRdRnRmFpSimd), + new(0x0EA0CC00, 0xBFA0FC00, qszConstraints, InstName.FmlsAdvsimdVecSingleAndDouble, IsaVersion.v80, InstFlags.RdReadRdRnRmFpSimd), + new(0x0F00FC00, 0xBFF8FC00, InstName.FmovAdvsimdPerHalf, IsaVersion.v82, InstFlags.RdFpSimd), + new(0x0F00F400, 0x9FF8FC00, qConstraints, InstName.FmovAdvsimdSingleAndDouble, IsaVersion.v80, InstFlags.RdFpSimd), + new(0x1E204000, 0xFFBFFC00, InstName.FmovFloat, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x1EE04000, 0xFFFFFC00, InstName.FmovFloat, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x1E260000, 0xFFFEFC00, sfftypermodeSfftypermodeConstraints, InstName.FmovFloatGen, IsaVersion.v80, InstFlags.RdRnSFpSimdFromToGpr), + new(0x9E660000, 0xFFFEFC00, sfftypermodeSfftypermodeConstraints, InstName.FmovFloatGen, IsaVersion.v80, InstFlags.RdRnSFpSimdFromToGpr), + new(0x9EAE0000, 0xFFFEFC00, sfftypermodeSfftypermodeConstraints, InstName.FmovFloatGen, IsaVersion.v80, InstFlags.RdRnSFpSimdFromToGpr), + new(0x1EE60000, 0x7FFEFC00, sfftypermodeSfftypermodeConstraints, InstName.FmovFloatGen, IsaVersion.v80, InstFlags.RdRnSFpSimdFromToGpr), + new(0x1E201000, 0xFFA01FE0, InstName.FmovFloatImm, IsaVersion.v80, InstFlags.RdFpSimd), + new(0x1EE01000, 0xFFE01FE0, InstName.FmovFloatImm, IsaVersion.v80, InstFlags.RdFpSimd), + new(0x1F008000, 0xFFA08000, InstName.FmsubFloat, IsaVersion.v80, InstFlags.RdRnRmRaFpSimd), + new(0x1FC08000, 0xFFE08000, InstName.FmsubFloat, IsaVersion.v80, InstFlags.RdRnRmRaFpSimd), + new(0x7F009000, 0xFFC0F400, InstName.FmulxAdvsimdElt2regScalarHalf, IsaVersion.v82, InstFlags.RdRnRmFpSimd), + new(0x7F809000, 0xFF80F400, szlConstraints, InstName.FmulxAdvsimdElt2regScalarSingleAndDouble, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x2F009000, 0xBFC0F400, InstName.FmulxAdvsimdElt2regElementHalf, IsaVersion.v82, InstFlags.RdRnRmFpSimd), + new(0x2F809000, 0xBF80F400, szlQszConstraints, InstName.FmulxAdvsimdElt2regElementSingleAndDouble, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x5E401C00, 0xFFE0FC00, InstName.FmulxAdvsimdVecSH, IsaVersion.v82, InstFlags.RdRnRmFpSimd), + new(0x5E20DC00, 0xFFA0FC00, InstName.FmulxAdvsimdVecS, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x0E401C00, 0xBFE0FC00, InstName.FmulxAdvsimdVecVH, IsaVersion.v82, InstFlags.RdRnRmFpSimd), + new(0x0E20DC00, 0xBFA0FC00, qszConstraints, InstName.FmulxAdvsimdVecV, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x5F009000, 0xFFC0F400, InstName.FmulAdvsimdElt2regScalarHalf, IsaVersion.v82, InstFlags.RdRnRmFpSimd), + new(0x5F809000, 0xFF80F400, szlConstraints, InstName.FmulAdvsimdElt2regScalarSingleAndDouble, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x0F009000, 0xBFC0F400, InstName.FmulAdvsimdElt2regElementHalf, IsaVersion.v82, InstFlags.RdRnRmFpSimd), + new(0x0F809000, 0xBF80F400, szlQszConstraints, InstName.FmulAdvsimdElt2regElementSingleAndDouble, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x2E401C00, 0xBFE0FC00, InstName.FmulAdvsimdVecHalf, IsaVersion.v82, InstFlags.RdRnRmFpSimd), + new(0x2E20DC00, 0xBFA0FC00, qszConstraints, InstName.FmulAdvsimdVecSingleAndDouble, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x1E200800, 0xFFA0FC00, InstName.FmulFloat, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x1EE00800, 0xFFE0FC00, InstName.FmulFloat, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x2EF8F800, 0xBFFFFC00, InstName.FnegAdvsimdHalf, IsaVersion.v82, InstFlags.RdRnFpSimd), + new(0x2EA0F800, 0xBFBFFC00, qszConstraints, InstName.FnegAdvsimdSingleAndDouble, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x1E214000, 0xFFBFFC00, InstName.FnegFloat, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x1EE14000, 0xFFFFFC00, InstName.FnegFloat, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x1F200000, 0xFFA08000, InstName.FnmaddFloat, IsaVersion.v80, InstFlags.RdRnRmRaFpSimd), + new(0x1FE00000, 0xFFE08000, InstName.FnmaddFloat, IsaVersion.v80, InstFlags.RdRnRmRaFpSimd), + new(0x1F208000, 0xFFA08000, InstName.FnmsubFloat, IsaVersion.v80, InstFlags.RdRnRmRaFpSimd), + new(0x1FE08000, 0xFFE08000, InstName.FnmsubFloat, IsaVersion.v80, InstFlags.RdRnRmRaFpSimd), + new(0x1E208800, 0xFFA0FC00, InstName.FnmulFloat, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x1EE08800, 0xFFE0FC00, InstName.FnmulFloat, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x5EF9D800, 0xFFFFFC00, InstName.FrecpeAdvsimdSH, IsaVersion.v82, InstFlags.RdRnFpSimd), + new(0x5EA1D800, 0xFFBFFC00, InstName.FrecpeAdvsimdS, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x0EF9D800, 0xBFFFFC00, InstName.FrecpeAdvsimdVH, IsaVersion.v82, InstFlags.RdRnFpSimd), + new(0x0EA1D800, 0xBFBFFC00, qszConstraints, InstName.FrecpeAdvsimdV, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x5E403C00, 0xFFE0FC00, InstName.FrecpsAdvsimdSH, IsaVersion.v82, InstFlags.RdRnRmFpSimd), + new(0x5E20FC00, 0xFFA0FC00, InstName.FrecpsAdvsimdS, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x0E403C00, 0xBFE0FC00, InstName.FrecpsAdvsimdVH, IsaVersion.v82, InstFlags.RdRnRmFpSimd), + new(0x0E20FC00, 0xBFA0FC00, qszConstraints, InstName.FrecpsAdvsimdV, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x5EF9F800, 0xFFFFFC00, InstName.FrecpxAdvsimdHalf, IsaVersion.v82, InstFlags.RdRnFpSimd), + new(0x5EA1F800, 0xFFBFFC00, InstName.FrecpxAdvsimdSingleAndDouble, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x2E21E800, 0xBFBFFC00, qszConstraints, InstName.Frint32xAdvsimd, IsaVersion.v85, InstFlags.RdRnFpSimd), + new(0x1E28C000, 0xFFBFFC00, InstName.Frint32xFloat, IsaVersion.v85, InstFlags.RdRnFpSimd), + new(0x0E21E800, 0xBFBFFC00, qszConstraints, InstName.Frint32zAdvsimd, IsaVersion.v85, InstFlags.RdRnFpSimd), + new(0x1E284000, 0xFFBFFC00, InstName.Frint32zFloat, IsaVersion.v85, InstFlags.RdRnFpSimd), + new(0x2E21F800, 0xBFBFFC00, qszConstraints, InstName.Frint64xAdvsimd, IsaVersion.v85, InstFlags.RdRnFpSimd), + new(0x1E29C000, 0xFFBFFC00, InstName.Frint64xFloat, IsaVersion.v85, InstFlags.RdRnFpSimd), + new(0x0E21F800, 0xBFBFFC00, qszConstraints, InstName.Frint64zAdvsimd, IsaVersion.v85, InstFlags.RdRnFpSimd), + new(0x1E294000, 0xFFBFFC00, InstName.Frint64zFloat, IsaVersion.v85, InstFlags.RdRnFpSimd), + new(0x2E798800, 0xBFFFFC00, uo1o2Constraints, InstName.FrintaAdvsimdHalf, IsaVersion.v82, InstFlags.RdRnFpSimd), + new(0x2E218800, 0xBFBFFC00, qszUo1o2Constraints, InstName.FrintaAdvsimdSingleAndDouble, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x1E264000, 0xFFBFFC00, InstName.FrintaFloat, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x1EE64000, 0xFFFFFC00, InstName.FrintaFloat, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x2EF99800, 0xBFFFFC00, uo1o2Constraints, InstName.FrintiAdvsimdHalf, IsaVersion.v82, InstFlags.RdRnFpSimd), + new(0x2EA19800, 0xBFBFFC00, qszUo1o2Constraints, InstName.FrintiAdvsimdSingleAndDouble, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x1E27C000, 0xFFBFFC00, InstName.FrintiFloat, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x1EE7C000, 0xFFFFFC00, InstName.FrintiFloat, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x0E799800, 0xBFFFFC00, uo1o2Constraints, InstName.FrintmAdvsimdHalf, IsaVersion.v82, InstFlags.RdRnFpSimd), + new(0x0E219800, 0xBFBFFC00, qszUo1o2Constraints, InstName.FrintmAdvsimdSingleAndDouble, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x1E254000, 0xFFBFFC00, InstName.FrintmFloat, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x1EE54000, 0xFFFFFC00, InstName.FrintmFloat, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x0E798800, 0xBFFFFC00, uo1o2Constraints, InstName.FrintnAdvsimdHalf, IsaVersion.v82, InstFlags.RdRnFpSimd), + new(0x0E218800, 0xBFBFFC00, qszUo1o2Constraints, InstName.FrintnAdvsimdSingleAndDouble, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x1E244000, 0xFFBFFC00, InstName.FrintnFloat, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x1EE44000, 0xFFFFFC00, InstName.FrintnFloat, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x0EF98800, 0xBFFFFC00, uo1o2Constraints, InstName.FrintpAdvsimdHalf, IsaVersion.v82, InstFlags.RdRnFpSimd), + new(0x0EA18800, 0xBFBFFC00, qszUo1o2Constraints, InstName.FrintpAdvsimdSingleAndDouble, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x1E24C000, 0xFFBFFC00, InstName.FrintpFloat, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x1EE4C000, 0xFFFFFC00, InstName.FrintpFloat, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x2E799800, 0xBFFFFC00, uo1o2Constraints, InstName.FrintxAdvsimdHalf, IsaVersion.v82, InstFlags.RdRnFpSimd), + new(0x2E219800, 0xBFBFFC00, qszUo1o2Constraints, InstName.FrintxAdvsimdSingleAndDouble, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x1E274000, 0xFFBFFC00, InstName.FrintxFloat, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x1EE74000, 0xFFFFFC00, InstName.FrintxFloat, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x0EF99800, 0xBFFFFC00, uo1o2Constraints, InstName.FrintzAdvsimdHalf, IsaVersion.v82, InstFlags.RdRnFpSimd), + new(0x0EA19800, 0xBFBFFC00, qszUo1o2Constraints, InstName.FrintzAdvsimdSingleAndDouble, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x1E25C000, 0xFFBFFC00, InstName.FrintzFloat, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x1EE5C000, 0xFFFFFC00, InstName.FrintzFloat, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x7EF9D800, 0xFFFFFC00, InstName.FrsqrteAdvsimdSH, IsaVersion.v82, InstFlags.RdRnFpSimd), + new(0x7EA1D800, 0xFFBFFC00, InstName.FrsqrteAdvsimdS, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x2EF9D800, 0xBFFFFC00, InstName.FrsqrteAdvsimdVH, IsaVersion.v82, InstFlags.RdRnFpSimd), + new(0x2EA1D800, 0xBFBFFC00, qszConstraints, InstName.FrsqrteAdvsimdV, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x5EC03C00, 0xFFE0FC00, InstName.FrsqrtsAdvsimdSH, IsaVersion.v82, InstFlags.RdRnRmFpSimd), + new(0x5EA0FC00, 0xFFA0FC00, InstName.FrsqrtsAdvsimdS, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x0EC03C00, 0xBFE0FC00, InstName.FrsqrtsAdvsimdVH, IsaVersion.v82, InstFlags.RdRnRmFpSimd), + new(0x0EA0FC00, 0xBFA0FC00, qszConstraints, InstName.FrsqrtsAdvsimdV, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x2EF9F800, 0xBFFFFC00, InstName.FsqrtAdvsimdHalf, IsaVersion.v82, InstFlags.RdRnFpSimd), + new(0x2EA1F800, 0xBFBFFC00, qszConstraints, InstName.FsqrtAdvsimdSingleAndDouble, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x1E21C000, 0xFFBFFC00, InstName.FsqrtFloat, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x1EE1C000, 0xFFFFFC00, InstName.FsqrtFloat, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x0EC01400, 0xBFE0FC00, InstName.FsubAdvsimdHalf, IsaVersion.v82, InstFlags.RdRnRmFpSimd), + new(0x0EA0D400, 0xBFA0FC00, qszConstraints, InstName.FsubAdvsimdSingleAndDouble, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x1E203800, 0xFFA0FC00, InstName.FsubFloat, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x1EE03800, 0xFFE0FC00, InstName.FsubFloat, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0xD503227F, 0xFFFFFFFF, InstName.Gcsb, IsaVersion.None, InstFlags.None), + new(0xD91F0C00, 0xFFFFFC00, InstName.Gcsstr, IsaVersion.None, InstFlags.RtReadRtRnSP), + new(0xD91F1C00, 0xFFFFFC00, InstName.Gcssttr, IsaVersion.None, InstFlags.RtReadRtRnSP), + new(0x9AC01400, 0xFFE0FC00, InstName.Gmi, IsaVersion.v85, InstFlags.None), + new(0xD503201F, 0xFFFFF01F, InstName.Hint, IsaVersion.v80, InstFlags.None), + new(0xD4400000, 0xFFE0001F, InstName.Hlt, IsaVersion.v80, InstFlags.None), + new(0xD4000002, 0xFFE0001F, InstName.Hvc, IsaVersion.v80, InstFlags.None), + new(0x6E000400, 0xFFE08400, imm5Constraints, InstName.InsAdvsimdElt, IsaVersion.v80, InstFlags.RdReadRdRnFpSimd), + new(0x4E001C00, 0xFFE0FC00, imm5Constraints, InstName.InsAdvsimdGen, IsaVersion.v80, InstFlags.RdReadRdRnFpSimdFromGpr), + new(0x9AC01000, 0xFFE0FC00, InstName.Irg, IsaVersion.v85, InstFlags.None), + new(0xD50330DF, 0xFFFFF0FF, InstName.Isb, IsaVersion.v80, InstFlags.None), + new(0x0D40C000, 0xBFFFF000, sConstraints, InstName.Ld1rAdvsimdAsNoPostIndex, IsaVersion.v80, InstFlags.RtRnSPFpSimd, AddressForm.StructNoOffset), + new(0x0DC0C000, 0xBFE0F000, sConstraints, InstName.Ld1rAdvsimdAsPostIndex, IsaVersion.v80, InstFlags.RtRnSPRmFpSimdMemWBack, AddressForm.StructPostIndexedReg), + new(0x0C402000, 0xBFFFF000, InstName.Ld1AdvsimdMultAsNoPostIndex, IsaVersion.v80, InstFlags.RtSeqRnSPFpSimd, AddressForm.StructNoOffset), + new(0x0C406000, 0xBFFFF000, InstName.Ld1AdvsimdMultAsNoPostIndex, IsaVersion.v80, InstFlags.RtSeqRnSPFpSimd, AddressForm.StructNoOffset), + new(0x0C407000, 0xBFFFF000, InstName.Ld1AdvsimdMultAsNoPostIndex, IsaVersion.v80, InstFlags.RtSeqRnSPFpSimd, AddressForm.StructNoOffset), + new(0x0C40A000, 0xBFFFF000, InstName.Ld1AdvsimdMultAsNoPostIndex, IsaVersion.v80, InstFlags.RtSeqRnSPFpSimd, AddressForm.StructNoOffset), + new(0x0C406000, 0xBFFFF000, InstName.Ld1AdvsimdMultAsNoPostIndex, IsaVersion.v80, InstFlags.RtSeqRnSPFpSimd, AddressForm.StructNoOffset), + new(0x0C407000, 0xBFFFF000, InstName.Ld1AdvsimdMultAsNoPostIndex, IsaVersion.v80, InstFlags.RtSeqRnSPFpSimd, AddressForm.StructNoOffset), + new(0x0C40A000, 0xBFFFF000, InstName.Ld1AdvsimdMultAsNoPostIndex, IsaVersion.v80, InstFlags.RtSeqRnSPFpSimd, AddressForm.StructNoOffset), + new(0x0CC02000, 0xBFE0F000, InstName.Ld1AdvsimdMultAsPostIndex, IsaVersion.v80, InstFlags.RtSeqRnSPRmFpSimdMemWBack, AddressForm.StructPostIndexedReg), + new(0x0CC06000, 0xBFE0F000, InstName.Ld1AdvsimdMultAsPostIndex, IsaVersion.v80, InstFlags.RtSeqRnSPRmFpSimdMemWBack, AddressForm.StructPostIndexedReg), + new(0x0CC07000, 0xBFE0F000, InstName.Ld1AdvsimdMultAsPostIndex, IsaVersion.v80, InstFlags.RtSeqRnSPRmFpSimdMemWBack, AddressForm.StructPostIndexedReg), + new(0x0CC0A000, 0xBFE0F000, InstName.Ld1AdvsimdMultAsPostIndex, IsaVersion.v80, InstFlags.RtSeqRnSPRmFpSimdMemWBack, AddressForm.StructPostIndexedReg), + new(0x0CC06000, 0xBFE0F000, InstName.Ld1AdvsimdMultAsPostIndex, IsaVersion.v80, InstFlags.RtSeqRnSPRmFpSimdMemWBack, AddressForm.StructPostIndexedReg), + new(0x0CC07000, 0xBFE0F000, InstName.Ld1AdvsimdMultAsPostIndex, IsaVersion.v80, InstFlags.RtSeqRnSPRmFpSimdMemWBack, AddressForm.StructPostIndexedReg), + new(0x0CC0A000, 0xBFE0F000, InstName.Ld1AdvsimdMultAsPostIndex, IsaVersion.v80, InstFlags.RtSeqRnSPRmFpSimdMemWBack, AddressForm.StructPostIndexedReg), + new(0x0D400000, 0xBFFF2000, opcodesizeOpcodesizeOpcodesizesOpcodesizeConstraints, InstName.Ld1AdvsimdSnglAsNoPostIndex, IsaVersion.v80, InstFlags.RtReadRtRnSPFpSimd, AddressForm.StructNoOffset), + new(0x0DC00000, 0xBFE02000, opcodesizeOpcodesizeOpcodesizesOpcodesizeConstraints, InstName.Ld1AdvsimdSnglAsPostIndex, IsaVersion.v80, InstFlags.RtReadRtRnSPRmFpSimdMemWBack, AddressForm.StructPostIndexedReg), + new(0x0D60C000, 0xBFFFF000, sConstraints, InstName.Ld2rAdvsimdAsNoPostIndex, IsaVersion.v80, InstFlags.RtSeqRnSPFpSimd, AddressForm.StructNoOffset), + new(0x0DE0C000, 0xBFE0F000, sConstraints, InstName.Ld2rAdvsimdAsPostIndex, IsaVersion.v80, InstFlags.RtSeqRnSPRmFpSimdMemWBack, AddressForm.StructPostIndexedReg), + new(0x0C408000, 0xBFFFF000, qsizeConstraints2, InstName.Ld2AdvsimdMultAsNoPostIndex, IsaVersion.v80, InstFlags.RtSeqRnSPFpSimd, AddressForm.StructNoOffset), + new(0x0CC08000, 0xBFE0F000, qsizeConstraints2, InstName.Ld2AdvsimdMultAsPostIndex, IsaVersion.v80, InstFlags.RtSeqRnSPRmFpSimdMemWBack, AddressForm.StructPostIndexedReg), + new(0x0D600000, 0xBFFF2000, opcodesizeOpcodesizeOpcodesizesOpcodesizeConstraints, InstName.Ld2AdvsimdSnglAsNoPostIndex, IsaVersion.v80, InstFlags.RtSeqReadRtRnSPFpSimd, AddressForm.StructNoOffset), + new(0x0DE00000, 0xBFE02000, opcodesizeOpcodesizeOpcodesizesOpcodesizeConstraints, InstName.Ld2AdvsimdSnglAsPostIndex, IsaVersion.v80, InstFlags.RtSeqReadRtRnSPRmFpSimdMemWBack, AddressForm.StructPostIndexedReg), + new(0x0D40E000, 0xBFFFF000, sConstraints, InstName.Ld3rAdvsimdAsNoPostIndex, IsaVersion.v80, InstFlags.RtSeqRnSPFpSimd, AddressForm.StructNoOffset), + new(0x0DC0E000, 0xBFE0F000, sConstraints, InstName.Ld3rAdvsimdAsPostIndex, IsaVersion.v80, InstFlags.RtSeqRnSPRmFpSimdMemWBack, AddressForm.StructPostIndexedReg), + new(0x0C404000, 0xBFFFF000, qsizeConstraints2, InstName.Ld3AdvsimdMultAsNoPostIndex, IsaVersion.v80, InstFlags.RtSeqRnSPFpSimd, AddressForm.StructNoOffset), + new(0x0CC04000, 0xBFE0F000, qsizeConstraints2, InstName.Ld3AdvsimdMultAsPostIndex, IsaVersion.v80, InstFlags.RtSeqRnSPRmFpSimdMemWBack, AddressForm.StructPostIndexedReg), + new(0x0D402000, 0xBFFF2000, opcodesizeOpcodesizeOpcodesizesOpcodesizeConstraints, InstName.Ld3AdvsimdSnglAsNoPostIndex, IsaVersion.v80, InstFlags.RtSeqReadRtRnSPFpSimd, AddressForm.StructNoOffset), + new(0x0DC02000, 0xBFE02000, opcodesizeOpcodesizeOpcodesizesOpcodesizeConstraints, InstName.Ld3AdvsimdSnglAsPostIndex, IsaVersion.v80, InstFlags.RtSeqReadRtRnSPRmFpSimdMemWBack, AddressForm.StructPostIndexedReg), + new(0x0D60E000, 0xBFFFF000, sConstraints, InstName.Ld4rAdvsimdAsNoPostIndex, IsaVersion.v80, InstFlags.RtSeqRnSPFpSimd, AddressForm.StructNoOffset), + new(0x0DE0E000, 0xBFE0F000, sConstraints, InstName.Ld4rAdvsimdAsPostIndex, IsaVersion.v80, InstFlags.RtSeqRnSPRmFpSimdMemWBack, AddressForm.StructPostIndexedReg), + new(0x0C400000, 0xBFFFF000, qsizeConstraints2, InstName.Ld4AdvsimdMultAsNoPostIndex, IsaVersion.v80, InstFlags.RtSeqRnSPFpSimd, AddressForm.StructNoOffset), + new(0x0CC00000, 0xBFE0F000, qsizeConstraints2, InstName.Ld4AdvsimdMultAsPostIndex, IsaVersion.v80, InstFlags.RtSeqRnSPRmFpSimdMemWBack, AddressForm.StructPostIndexedReg), + new(0x0D602000, 0xBFFF2000, opcodesizeOpcodesizeOpcodesizesOpcodesizeConstraints, InstName.Ld4AdvsimdSnglAsNoPostIndex, IsaVersion.v80, InstFlags.RtSeqReadRtRnSPFpSimd, AddressForm.StructNoOffset), + new(0x0DE02000, 0xBFE02000, opcodesizeOpcodesizeOpcodesizesOpcodesizeConstraints, InstName.Ld4AdvsimdSnglAsPostIndex, IsaVersion.v80, InstFlags.RtSeqReadRtRnSPRmFpSimdMemWBack, AddressForm.StructPostIndexedReg), + new(0xF83FD000, 0xFFFFFC00, rtRtConstraints, InstName.Ld64b, IsaVersion.v87, InstFlags.RtRnSP), + new(0xB8200000, 0xBF20FC00, InstName.Ldadd, IsaVersion.v81, InstFlags.RtRnSPRs), + new(0x38200000, 0xFF20FC00, InstName.Ldaddb, IsaVersion.v81, InstFlags.RtRnSPRs), + new(0x78200000, 0xFF20FC00, InstName.Ldaddh, IsaVersion.v81, InstFlags.RtRnSPRs), + new(0x0D418400, 0xBFFFFC00, opcodesizeOpcodesizeOpcodesizesOpcodesizeConstraints, InstName.Ldap1AdvsimdSngl, IsaVersion.v82, InstFlags.RtReadRtRnSPFpSimd, AddressForm.StructNoOffset), + new(0xB8BFC000, 0xBFFFFC00, InstName.LdaprBaseRegister, IsaVersion.v83, InstFlags.RtRnSP, AddressForm.BaseRegister), + new(0x99C00800, 0xBFFFFC00, InstName.LdaprPostIndexed, IsaVersion.v82, InstFlags.RtRnSPMemWBack, AddressForm.PostIndexed), + new(0x38BFC000, 0xFFFFFC00, InstName.Ldaprb, IsaVersion.v83, InstFlags.RtRnSP), + new(0x78BFC000, 0xFFFFFC00, InstName.Ldaprh, IsaVersion.v83, InstFlags.RtRnSP), + new(0x19400000, 0xFFE00C00, InstName.Ldapurb, IsaVersion.v84, InstFlags.RtRnSP, AddressForm.BasePlusOffset), + new(0x59400000, 0xFFE00C00, InstName.Ldapurh, IsaVersion.v84, InstFlags.RtRnSP, AddressForm.BasePlusOffset), + new(0x19800000, 0xFFA00C00, InstName.Ldapursb, IsaVersion.v84, InstFlags.RtRnSP, AddressForm.BasePlusOffset), + new(0x59800000, 0xFFA00C00, InstName.Ldapursh, IsaVersion.v84, InstFlags.RtRnSP, AddressForm.BasePlusOffset), + new(0x99800000, 0xFFE00C00, InstName.Ldapursw, IsaVersion.v84, InstFlags.RtRnSP, AddressForm.BasePlusOffset), + new(0x1D400800, 0x3F600C00, opc1sizeOpc1sizeOpc1sizeConstraints, InstName.LdapurFpsimd, IsaVersion.v82, InstFlags.RtRnSPFpSimd, AddressForm.BasePlusOffset), + new(0x99400000, 0xBFE00C00, InstName.LdapurGen, IsaVersion.v84, InstFlags.RtRnSP, AddressForm.BasePlusOffset), + new(0x88DFFC00, 0xBFFFFC00, InstName.Ldar, IsaVersion.v80, InstFlags.RtRnSP, AddressForm.BaseRegister), + new(0x08DFFC00, 0xFFFFFC00, InstName.Ldarb, IsaVersion.v80, InstFlags.RtRnSP, AddressForm.BaseRegister), + new(0x48DFFC00, 0xFFFFFC00, InstName.Ldarh, IsaVersion.v80, InstFlags.RtRnSP, AddressForm.BaseRegister), + new(0x887F8000, 0xBFFF8000, InstName.Ldaxp, IsaVersion.v80, InstFlags.RtRt2RnSP, AddressForm.BaseRegister), + new(0x885FFC00, 0xBFFFFC00, InstName.Ldaxr, IsaVersion.v80, InstFlags.RtRnSP, AddressForm.BaseRegister), + new(0x085FFC00, 0xFFFFFC00, InstName.Ldaxrb, IsaVersion.v80, InstFlags.RtRnSP, AddressForm.BaseRegister), + new(0x485FFC00, 0xFFFFFC00, InstName.Ldaxrh, IsaVersion.v80, InstFlags.RtRnSP, AddressForm.BaseRegister), + new(0xB8201000, 0xBF20FC00, InstName.Ldclr, IsaVersion.v81, InstFlags.RtRnSPRs), + new(0x38201000, 0xFF20FC00, InstName.Ldclrb, IsaVersion.v81, InstFlags.RtRnSPRs), + new(0x78201000, 0xFF20FC00, InstName.Ldclrh, IsaVersion.v81, InstFlags.RtRnSPRs), + new(0x19201000, 0xFF20FC00, rtRt2Constraints, InstName.Ldclrp, IsaVersion.None, InstFlags.RtRt2RnSP), + new(0xB8202000, 0xBF20FC00, InstName.Ldeor, IsaVersion.v81, InstFlags.RtRnSPRs), + new(0x38202000, 0xFF20FC00, InstName.Ldeorb, IsaVersion.v81, InstFlags.RtRnSPRs), + new(0x78202000, 0xFF20FC00, InstName.Ldeorh, IsaVersion.v81, InstFlags.RtRnSPRs), + new(0xD9600000, 0xFFE00C00, InstName.Ldg, IsaVersion.v85, InstFlags.None), + new(0xD9E00000, 0xFFFFFC00, InstName.Ldgm, IsaVersion.v85, InstFlags.None), + new(0x99400800, 0xBFE0EC00, InstName.Ldiapp, IsaVersion.v82, InstFlags.RtRt2RnSP), + new(0x88DF7C00, 0xBFFFFC00, InstName.Ldlar, IsaVersion.v81, InstFlags.RtRnSP, AddressForm.BaseRegister), + new(0x08DF7C00, 0xFFFFFC00, InstName.Ldlarb, IsaVersion.v81, InstFlags.RtRnSP, AddressForm.BaseRegister), + new(0x48DF7C00, 0xFFFFFC00, InstName.Ldlarh, IsaVersion.v81, InstFlags.RtRnSP, AddressForm.BaseRegister), + new(0x2C400000, 0x3FC00000, opcConstraints, InstName.LdnpFpsimd, IsaVersion.v80, InstFlags.RtRt2RnSPFpSimd, AddressForm.SignedScaled), + new(0x28400000, 0x7FC00000, opcConstraints2, InstName.LdnpGen, IsaVersion.v80, InstFlags.RtRt2RnSP, AddressForm.SignedScaled), + new(0x68C00000, 0xFFC00000, InstName.LdpswPostIndexed, IsaVersion.v80, InstFlags.RtRt2RnSPMemWBack, AddressForm.PostIndexed), + new(0x69C00000, 0xFFC00000, InstName.LdpswPreIndexed, IsaVersion.v80, InstFlags.RtRt2RnSPMemWBack, AddressForm.PreIndexed), + new(0x69400000, 0xFFC00000, InstName.LdpswSignedScaledOffset, IsaVersion.v80, InstFlags.RtRt2RnSP, AddressForm.SignedScaled), + new(0x2CC00000, 0x3FC00000, opcConstraints, InstName.LdpFpsimdPostIndexed, IsaVersion.v80, InstFlags.RtRt2RnSPFpSimdMemWBack, AddressForm.PostIndexed), + new(0x2DC00000, 0x3FC00000, opcConstraints, InstName.LdpFpsimdPreIndexed, IsaVersion.v80, InstFlags.RtRt2RnSPFpSimdMemWBack, AddressForm.PreIndexed), + new(0x2D400000, 0x3FC00000, opcConstraints, InstName.LdpFpsimdSignedScaledOffset, IsaVersion.v80, InstFlags.RtRt2RnSPFpSimd, AddressForm.SignedScaled), + new(0x28C00000, 0x7FC00000, opclOpcConstraints, InstName.LdpGenPostIndexed, IsaVersion.v80, InstFlags.RtRt2RnSPMemWBack, AddressForm.PostIndexed), + new(0x29C00000, 0x7FC00000, opclOpcConstraints, InstName.LdpGenPreIndexed, IsaVersion.v80, InstFlags.RtRt2RnSPMemWBack, AddressForm.PreIndexed), + new(0x29400000, 0x7FC00000, opclOpcConstraints, InstName.LdpGenSignedScaledOffset, IsaVersion.v80, InstFlags.RtRt2RnSP, AddressForm.SignedScaled), + new(0xF8200400, 0xFF200400, InstName.Ldra, IsaVersion.v83, InstFlags.RtRnSP, AddressForm.BasePlusOffset), + new(0x38400400, 0xFFE00C00, InstName.LdrbImmPostIndexed, IsaVersion.v80, InstFlags.RtRnSPMemWBack, AddressForm.PostIndexed), + new(0x38400C00, 0xFFE00C00, InstName.LdrbImmPreIndexed, IsaVersion.v80, InstFlags.RtRnSPMemWBack, AddressForm.PreIndexed), + new(0x39400000, 0xFFC00000, InstName.LdrbImmUnsignedScaledOffset, IsaVersion.v80, InstFlags.RtRnSP, AddressForm.UnsignedScaled), + new(0x38600800, 0xFFE00C00, optionConstraints, InstName.LdrbReg, IsaVersion.v80, InstFlags.RtRnSPRm, AddressForm.OffsetReg), + new(0x78400400, 0xFFE00C00, InstName.LdrhImmPostIndexed, IsaVersion.v80, InstFlags.RtRnSPMemWBack, AddressForm.PostIndexed), + new(0x78400C00, 0xFFE00C00, InstName.LdrhImmPreIndexed, IsaVersion.v80, InstFlags.RtRnSPMemWBack, AddressForm.PreIndexed), + new(0x79400000, 0xFFC00000, InstName.LdrhImmUnsignedScaledOffset, IsaVersion.v80, InstFlags.RtRnSP, AddressForm.UnsignedScaled), + new(0x78600800, 0xFFE00C00, optionConstraints, InstName.LdrhReg, IsaVersion.v80, InstFlags.RtRnSPRm, AddressForm.OffsetReg), + new(0x38800400, 0xFFA00C00, InstName.LdrsbImmPostIndexed, IsaVersion.v80, InstFlags.RtRnSPMemWBack, AddressForm.PostIndexed), + new(0x38800C00, 0xFFA00C00, InstName.LdrsbImmPreIndexed, IsaVersion.v80, InstFlags.RtRnSPMemWBack, AddressForm.PreIndexed), + new(0x39800000, 0xFF800000, InstName.LdrsbImmUnsignedScaledOffset, IsaVersion.v80, InstFlags.RtRnSP, AddressForm.UnsignedScaled), + new(0x38A00800, 0xFFA00C00, optionConstraints, InstName.LdrsbReg, IsaVersion.v80, InstFlags.RtRnSPRm, AddressForm.OffsetReg), + new(0x78800400, 0xFFA00C00, InstName.LdrshImmPostIndexed, IsaVersion.v80, InstFlags.RtRnSPMemWBack, AddressForm.PostIndexed), + new(0x78800C00, 0xFFA00C00, InstName.LdrshImmPreIndexed, IsaVersion.v80, InstFlags.RtRnSPMemWBack, AddressForm.PreIndexed), + new(0x79800000, 0xFF800000, InstName.LdrshImmUnsignedScaledOffset, IsaVersion.v80, InstFlags.RtRnSP, AddressForm.UnsignedScaled), + new(0x78A00800, 0xFFA00C00, optionConstraints, InstName.LdrshReg, IsaVersion.v80, InstFlags.RtRnSPRm, AddressForm.OffsetReg), + new(0xB8800400, 0xFFE00C00, InstName.LdrswImmPostIndexed, IsaVersion.v80, InstFlags.RtRnSPMemWBack, AddressForm.PostIndexed), + new(0xB8800C00, 0xFFE00C00, InstName.LdrswImmPreIndexed, IsaVersion.v80, InstFlags.RtRnSPMemWBack, AddressForm.PreIndexed), + new(0xB9800000, 0xFFC00000, InstName.LdrswImmUnsignedScaledOffset, IsaVersion.v80, InstFlags.RtRnSP, AddressForm.UnsignedScaled), + new(0x98000000, 0xFF000000, InstName.LdrswLit, IsaVersion.v80, InstFlags.Rt, AddressForm.Literal), + new(0xB8A00800, 0xFFE00C00, optionConstraints, InstName.LdrswReg, IsaVersion.v80, InstFlags.RtRnSPRm, AddressForm.OffsetReg), + new(0x3C400400, 0x3F600C00, opc1sizeOpc1sizeOpc1sizeConstraints, InstName.LdrImmFpsimdPostIndexed, IsaVersion.v80, InstFlags.RtRnSPFpSimdMemWBack, AddressForm.PostIndexed), + new(0x3C400C00, 0x3F600C00, opc1sizeOpc1sizeOpc1sizeConstraints, InstName.LdrImmFpsimdPreIndexed, IsaVersion.v80, InstFlags.RtRnSPFpSimdMemWBack, AddressForm.PreIndexed), + new(0x3D400000, 0x3F400000, opc1sizeOpc1sizeOpc1sizeConstraints, InstName.LdrImmFpsimdUnsignedScaledOffset, IsaVersion.v80, InstFlags.RtRnSPFpSimd, AddressForm.UnsignedScaled), + new(0xB8400400, 0xBFE00C00, InstName.LdrImmGenPostIndexed, IsaVersion.v80, InstFlags.RtRnSPMemWBack, AddressForm.PostIndexed), + new(0xB8400C00, 0xBFE00C00, InstName.LdrImmGenPreIndexed, IsaVersion.v80, InstFlags.RtRnSPMemWBack, AddressForm.PreIndexed), + new(0xB9400000, 0xBFC00000, InstName.LdrImmGenUnsignedScaledOffset, IsaVersion.v80, InstFlags.RtRnSP, AddressForm.UnsignedScaled), + new(0x1C000000, 0x3F000000, opcConstraints, InstName.LdrLitFpsimd, IsaVersion.v80, InstFlags.RtFpSimd, AddressForm.Literal), + new(0x18000000, 0xBF000000, InstName.LdrLitGen, IsaVersion.v80, InstFlags.Rt, AddressForm.Literal), + new(0x3C600800, 0x3F600C00, opc1sizeOpc1sizeOpc1sizeOptionConstraints, InstName.LdrRegFpsimd, IsaVersion.v80, InstFlags.RtRnSPRmFpSimd, AddressForm.OffsetReg), + new(0xB8600800, 0xBFE00C00, optionConstraints, InstName.LdrRegGen, IsaVersion.v80, InstFlags.RtRnSPRm, AddressForm.OffsetReg), + new(0xB8203000, 0xBF20FC00, InstName.Ldset, IsaVersion.v81, InstFlags.RtRnSPRs), + new(0x38203000, 0xFF20FC00, InstName.Ldsetb, IsaVersion.v81, InstFlags.RtRnSPRs), + new(0x78203000, 0xFF20FC00, InstName.Ldseth, IsaVersion.v81, InstFlags.RtRnSPRs), + new(0x19203000, 0xFF20FC00, rtRt2Constraints, InstName.Ldsetp, IsaVersion.None, InstFlags.RtRt2RnSP), + new(0xB8204000, 0xBF20FC00, InstName.Ldsmax, IsaVersion.v81, InstFlags.RtRnSPRs), + new(0x38204000, 0xFF20FC00, InstName.Ldsmaxb, IsaVersion.v81, InstFlags.RtRnSPRs), + new(0x78204000, 0xFF20FC00, InstName.Ldsmaxh, IsaVersion.v81, InstFlags.RtRnSPRs), + new(0xB8205000, 0xBF20FC00, InstName.Ldsmin, IsaVersion.v81, InstFlags.RtRnSPRs), + new(0x38205000, 0xFF20FC00, InstName.Ldsminb, IsaVersion.v81, InstFlags.RtRnSPRs), + new(0x78205000, 0xFF20FC00, InstName.Ldsminh, IsaVersion.v81, InstFlags.RtRnSPRs), + new(0xB8400800, 0xBFE00C00, InstName.Ldtr, IsaVersion.v80, InstFlags.RtRnSP, AddressForm.BasePlusOffset), + new(0x38400800, 0xFFE00C00, InstName.Ldtrb, IsaVersion.v80, InstFlags.RtRnSP, AddressForm.BasePlusOffset), + new(0x78400800, 0xFFE00C00, InstName.Ldtrh, IsaVersion.v80, InstFlags.RtRnSP, AddressForm.BasePlusOffset), + new(0x38800800, 0xFFA00C00, InstName.Ldtrsb, IsaVersion.v80, InstFlags.RtRnSP, AddressForm.BasePlusOffset), + new(0x78800800, 0xFFA00C00, InstName.Ldtrsh, IsaVersion.v80, InstFlags.RtRnSP, AddressForm.BasePlusOffset), + new(0xB8800800, 0xFFE00C00, InstName.Ldtrsw, IsaVersion.v80, InstFlags.RtRnSP, AddressForm.BasePlusOffset), + new(0xB8206000, 0xBF20FC00, InstName.Ldumax, IsaVersion.v81, InstFlags.RtRnSPRs), + new(0x38206000, 0xFF20FC00, InstName.Ldumaxb, IsaVersion.v81, InstFlags.RtRnSPRs), + new(0x78206000, 0xFF20FC00, InstName.Ldumaxh, IsaVersion.v81, InstFlags.RtRnSPRs), + new(0xB8207000, 0xBF20FC00, InstName.Ldumin, IsaVersion.v81, InstFlags.RtRnSPRs), + new(0x38207000, 0xFF20FC00, InstName.Lduminb, IsaVersion.v81, InstFlags.RtRnSPRs), + new(0x78207000, 0xFF20FC00, InstName.Lduminh, IsaVersion.v81, InstFlags.RtRnSPRs), + new(0x38400000, 0xFFE00C00, InstName.Ldurb, IsaVersion.v80, InstFlags.RtRnSP, AddressForm.BasePlusOffset), + new(0x78400000, 0xFFE00C00, InstName.Ldurh, IsaVersion.v80, InstFlags.RtRnSP, AddressForm.BasePlusOffset), + new(0x38800000, 0xFFA00C00, InstName.Ldursb, IsaVersion.v80, InstFlags.RtRnSP, AddressForm.BasePlusOffset), + new(0x78800000, 0xFFA00C00, InstName.Ldursh, IsaVersion.v80, InstFlags.RtRnSP, AddressForm.BasePlusOffset), + new(0xB8800000, 0xFFE00C00, InstName.Ldursw, IsaVersion.v80, InstFlags.RtRnSP, AddressForm.BasePlusOffset), + new(0x3C400000, 0x3F600C00, opc1sizeOpc1sizeOpc1sizeConstraints, InstName.LdurFpsimd, IsaVersion.v80, InstFlags.RtRnSPFpSimd, AddressForm.BasePlusOffset), + new(0xB8400000, 0xBFE00C00, InstName.LdurGen, IsaVersion.v80, InstFlags.RtRnSP, AddressForm.BasePlusOffset), + new(0x887F0000, 0xBFFF8000, InstName.Ldxp, IsaVersion.v80, InstFlags.RtRt2RnSP, AddressForm.BaseRegister), + new(0x885F7C00, 0xBFFFFC00, InstName.Ldxr, IsaVersion.v80, InstFlags.RtRnSP, AddressForm.BaseRegister), + new(0x085F7C00, 0xFFFFFC00, InstName.Ldxrb, IsaVersion.v80, InstFlags.RtRnSP, AddressForm.BaseRegister), + new(0x485F7C00, 0xFFFFFC00, InstName.Ldxrh, IsaVersion.v80, InstFlags.RtRnSP, AddressForm.BaseRegister), + new(0x1AC02000, 0x7FE0FC00, InstName.Lslv, IsaVersion.v80, InstFlags.RdRnRm), + new(0x1AC02400, 0x7FE0FC00, InstName.Lsrv, IsaVersion.v80, InstFlags.RdRnRm), + new(0x1B000000, 0x7FE08000, InstName.Madd, IsaVersion.v80, InstFlags.RdRnRmRa), + new(0x2F000000, 0xBF00F400, sizeSizeConstraints, InstName.MlaAdvsimdElt, IsaVersion.v80, InstFlags.RdReadRdRnRmFpSimd), + new(0x0E209400, 0xBF20FC00, sizeConstraints, InstName.MlaAdvsimdVec, IsaVersion.v80, InstFlags.RdReadRdRnRmFpSimd), + new(0x2F004000, 0xBF00F400, sizeSizeConstraints, InstName.MlsAdvsimdElt, IsaVersion.v80, InstFlags.RdReadRdRnRmFpSimd), + new(0x2E209400, 0xBF20FC00, sizeConstraints, InstName.MlsAdvsimdVec, IsaVersion.v80, InstFlags.RdReadRdRnRmFpSimd), + new(0x0F000400, 0x9FF80C00, cmodeopqConstraints, InstName.MoviAdvsimd, IsaVersion.v80, InstFlags.RdFpSimd), + new(0x72800000, 0x7F800000, sfhwConstraints, InstName.Movk, IsaVersion.v80, InstFlags.RdReadRd), + new(0x12800000, 0x7F800000, sfhwConstraints, InstName.Movn, IsaVersion.v80, InstFlags.Rd), + new(0x52800000, 0x7F800000, sfhwConstraints, InstName.Movz, IsaVersion.v80, InstFlags.Rd), + new(0xD5700000, 0xFFF00000, rtConstraints, InstName.Mrrs, IsaVersion.None, InstFlags.RtReadRt), + new(0xD5300000, 0xFFF00000, InstName.Mrs, IsaVersion.v80, InstFlags.Rt), + new(0xD5500000, 0xFFF00000, rtConstraints, InstName.Msrr, IsaVersion.None, InstFlags.RtReadRt), + new(0xD500401F, 0xFFF8F01F, InstName.MsrImm, IsaVersion.v80, InstFlags.None), + new(0xD5100000, 0xFFF00000, InstName.MsrReg, IsaVersion.v80, InstFlags.RtReadRt), + new(0x1B008000, 0x7FE08000, InstName.Msub, IsaVersion.v80, InstFlags.RdRnRmRa), + new(0x0F008000, 0xBF00F400, sizeSizeConstraints, InstName.MulAdvsimdElt, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x0E209C00, 0xBF20FC00, usizeUsizeUsizeSizeConstraints, InstName.MulAdvsimdVec, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x2F000400, 0xBFF80C00, cmodeopqConstraints, InstName.MvniAdvsimd, IsaVersion.v80, InstFlags.RdFpSimd), + new(0x7EE0B800, 0xFFFFFC00, InstName.NegAdvsimdS, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x2E20B800, 0xBF3FFC00, qsizeConstraints, InstName.NegAdvsimdV, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0xD503201F, 0xFFFFFFFF, InstName.Nop, IsaVersion.v80, InstFlags.None), + new(0x2E205800, 0xBFFFFC00, InstName.NotAdvsimd, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x0EE01C00, 0xBFE0FC00, InstName.OrnAdvsimd, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x2A200000, 0x7F200000, sfimm6Constraints, InstName.OrnLogShift, IsaVersion.v80, InstFlags.RdRnRm), + new(0x0F001400, 0xBFF81C00, InstName.OrrAdvsimdImm, IsaVersion.v80, InstFlags.RdFpSimd), + new(0x0EA01C00, 0xBFE0FC00, InstName.OrrAdvsimdReg, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x32000000, 0x7F800000, nimmsNimmsNimmsNimmsNimmsNimmsNimmsNimmsSfnConstraints, InstName.OrrLogImm, IsaVersion.v80, InstFlags.RdSPRn), + new(0x2A000000, 0x7F200000, sfimm6Constraints, InstName.OrrLogShift, IsaVersion.v80, InstFlags.RdRnRm), + new(0xDAC10800, 0xFFFFDC00, InstName.Pacda, IsaVersion.v83, InstFlags.RdRnSP), + new(0xDAC10C00, 0xFFFFDC00, InstName.Pacdb, IsaVersion.v83, InstFlags.RdRnSP), + new(0x9AC03000, 0xFFE0FC00, InstName.Pacga, IsaVersion.v83, InstFlags.RdRnRm), + new(0xDAC10000, 0xFFFFDC00, InstName.PaciaGeneral, IsaVersion.v83, InstFlags.RdRnSP), + new(0xD503211F, 0xFFFFFDDF, InstName.PaciaSystem, IsaVersion.v83, InstFlags.None), + new(0xDAC10400, 0xFFFFDC00, InstName.PacibGeneral, IsaVersion.v83, InstFlags.RdRnSP), + new(0xD503215F, 0xFFFFFDDF, InstName.PacibSystem, IsaVersion.v83, InstFlags.None), + new(0x0E20E000, 0xBFE0FC00, sizeSizeConstraints2, InstName.PmullAdvsimd, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x0EE0E000, 0xBFE0FC00, sizeSizeConstraints2, InstName.PmullAdvsimd, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x2E209C00, 0xBF20FC00, usizeUsizeUsizeSizeConstraints, InstName.PmulAdvsimd, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0xF9800000, 0xFFC00000, InstName.PrfmImm, IsaVersion.v80, InstFlags.RnSP, AddressForm.UnsignedScaled), + new(0xD8000000, 0xFF000000, InstName.PrfmLit, IsaVersion.v80, InstFlags.None, AddressForm.Literal), + new(0xF8A04800, 0xFFE04C00, rtConstraints2, InstName.PrfmReg, IsaVersion.v80, InstFlags.RnSPRm, AddressForm.OffsetReg), + new(0xF8800000, 0xFFE00C00, InstName.Prfum, IsaVersion.v80, InstFlags.RnSP, AddressForm.BasePlusOffset), + new(0xD503223F, 0xFFFFFFFF, InstName.Psb, IsaVersion.v82, InstFlags.None), + new(0x2E204000, 0xBF20FC00, sizeConstraints, InstName.RaddhnAdvsimd, IsaVersion.v80, InstFlags.RdReadRdRnRmFpSimd), + new(0xCE608C00, 0xFFE0FC00, InstName.Rax1Advsimd, IsaVersion.v82, InstFlags.RdRnRmFpSimd), + new(0x2E605800, 0xBFFFFC00, InstName.RbitAdvsimd, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x5AC00000, 0x7FFFFC00, InstName.RbitInt, IsaVersion.v80, InstFlags.RdRn), + new(0x19200800, 0xFF20FC00, InstName.Rcwcas, IsaVersion.v89, InstFlags.RtReadRtRnSPRsS), + new(0x19200C00, 0xFF20FC00, rsRtConstraints, InstName.Rcwcasp, IsaVersion.None, InstFlags.RtReadRtRnSPRsS), + new(0x38209000, 0xFF20FC00, InstName.Rcwclr, IsaVersion.v89, InstFlags.RtReadRtRnSPRsS), + new(0x19209000, 0xFF20FC00, rtRt2Constraints, InstName.Rcwclrp, IsaVersion.None, InstFlags.RtReadRtRt2RnSPS), + new(0x59200800, 0xFF20FC00, InstName.Rcwscas, IsaVersion.v89, InstFlags.RtReadRtRnSPRsS), + new(0x59200C00, 0xFF20FC00, rsRtConstraints, InstName.Rcwscasp, IsaVersion.None, InstFlags.RtReadRtRnSPRsS), + new(0x78209000, 0xFF20FC00, InstName.Rcwsclr, IsaVersion.v89, InstFlags.RtReadRtRnSPRsS), + new(0x59209000, 0xFF20FC00, rtRt2Constraints, InstName.Rcwsclrp, IsaVersion.None, InstFlags.RtReadRtRt2RnSPS), + new(0x3820B000, 0xFF20FC00, InstName.Rcwset, IsaVersion.v89, InstFlags.RtReadRtRnSPRsS), + new(0x1920B000, 0xFF20FC00, rtRt2Constraints, InstName.Rcwsetp, IsaVersion.None, InstFlags.RtReadRtRt2RnSPS), + new(0x7820B000, 0xFF20FC00, InstName.Rcwsset, IsaVersion.v89, InstFlags.RtReadRtRnSPRsS), + new(0x5920B000, 0xFF20FC00, rtRt2Constraints, InstName.Rcwssetp, IsaVersion.None, InstFlags.RtReadRtRt2RnSPS), + new(0x7820A000, 0xFF20FC00, InstName.Rcwsswp, IsaVersion.v89, InstFlags.RtReadRtRnSPRsS), + new(0x5920A000, 0xFF20FC00, rtRt2Constraints, InstName.Rcwsswpp, IsaVersion.None, InstFlags.RtReadRtRt2RnSPS), + new(0x3820A000, 0xFF20FC00, InstName.Rcwswp, IsaVersion.v89, InstFlags.RtReadRtRnSPRsS), + new(0x1920A000, 0xFF20FC00, rtRt2Constraints, InstName.Rcwswpp, IsaVersion.None, InstFlags.RtReadRtRt2RnSPS), + new(0xD65F0000, 0xFFFFFC1F, InstName.Ret, IsaVersion.v80, InstFlags.Rn), + new(0xD65F0BFF, 0xFFFFFBFF, InstName.Reta, IsaVersion.v83, InstFlags.None), + new(0x5AC00800, 0x7FFFF800, sfopcConstraints, InstName.Rev, IsaVersion.v80, InstFlags.RdRn), + new(0x0E201800, 0xBF3FFC00, sizeSizeSizeConstraints, InstName.Rev16Advsimd, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x5AC00400, 0x7FFFFC00, InstName.Rev16Int, IsaVersion.v80, InstFlags.RdRn), + new(0x2E200800, 0xBF3FFC00, sizeSizeConstraints3, InstName.Rev32Advsimd, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0xDAC00800, 0xFFFFFC00, sfConstraints, InstName.Rev32Int, IsaVersion.v80, InstFlags.RdRn), + new(0x0E200800, 0xBF3FFC00, sizeConstraints, InstName.Rev64Advsimd, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0xBA000400, 0xFFE07C10, InstName.Rmif, IsaVersion.v84, InstFlags.RnC), + new(0x1AC02C00, 0x7FE0FC00, InstName.Rorv, IsaVersion.v80, InstFlags.RdRnRm), + new(0xF8A04818, 0xFFE04C18, InstName.RprfmReg, IsaVersion.v80, InstFlags.RnSPRm, AddressForm.OffsetReg), + new(0x0F008C00, 0xBF80FC00, immhImmhConstraints, InstName.RshrnAdvsimd, IsaVersion.v80, InstFlags.RdReadRdRnFpSimd), + new(0x2E206000, 0xBF20FC00, sizeConstraints, InstName.RsubhnAdvsimd, IsaVersion.v80, InstFlags.RdReadRdRnRmFpSimd), + new(0x0E205000, 0xBF20FC00, sizeConstraints, InstName.SabalAdvsimd, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x0E207C00, 0xBF20FC00, sizeConstraints, InstName.SabaAdvsimd, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x0E207000, 0xBF20FC00, sizeConstraints, InstName.SabdlAdvsimd, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x0E207400, 0xBF20FC00, sizeConstraints, InstName.SabdAdvsimd, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x0E206800, 0xBF3FFC00, sizeConstraints, InstName.SadalpAdvsimd, IsaVersion.v80, InstFlags.RdReadRdRnFpSimd), + new(0x0E202800, 0xBF3FFC00, sizeConstraints, InstName.SaddlpAdvsimd, IsaVersion.v80, InstFlags.RdReadRdRnFpSimd), + new(0x0E303800, 0xBF3FFC00, qsizeSizeConstraints, InstName.SaddlvAdvsimd, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x0E200000, 0xBF20FC00, sizeConstraints, InstName.SaddlAdvsimd, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x0E201000, 0xBF20FC00, sizeConstraints, InstName.SaddwAdvsimd, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0xD50330FF, 0xFFFFFFFF, InstName.Sb, IsaVersion.v85, InstFlags.None), + new(0x5A000000, 0x7FE0FC00, InstName.Sbc, IsaVersion.v80, InstFlags.RdRnRmC), + new(0x7A000000, 0x7FE0FC00, InstName.Sbcs, IsaVersion.v80, InstFlags.RdRnRmCS), + new(0x13000000, 0x7F800000, sfnSfnSfimmr5Sfimms5Constraints, InstName.Sbfm, IsaVersion.v80, InstFlags.RdRn), + new(0x5F40E400, 0xFFC0FC00, immhConstraints, InstName.ScvtfAdvsimdFixS, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x5F10E400, 0xFFF0FC00, immhConstraints, InstName.ScvtfAdvsimdFixS, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x5F20E400, 0xFFE0FC00, immhConstraints, InstName.ScvtfAdvsimdFixS, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x0F40E400, 0xBFC0FC00, immhQimmhConstraints, InstName.ScvtfAdvsimdFixV, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x0F10E400, 0xBFF0FC00, immhQimmhConstraints, InstName.ScvtfAdvsimdFixV, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x0F20E400, 0xBFE0FC00, immhQimmhConstraints, InstName.ScvtfAdvsimdFixV, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x5E79D800, 0xFFFFFC00, InstName.ScvtfAdvsimdIntSH, IsaVersion.v82, InstFlags.RdRnFpSimd), + new(0x5E21D800, 0xFFBFFC00, InstName.ScvtfAdvsimdIntS, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x0E79D800, 0xBFFFFC00, InstName.ScvtfAdvsimdIntVH, IsaVersion.v82, InstFlags.RdRnFpSimd), + new(0x0E21D800, 0xBFBFFC00, qszConstraints, InstName.ScvtfAdvsimdIntV, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x1E020000, 0x7FBF0000, sfscaleConstraints, InstName.ScvtfFloatFix, IsaVersion.v80, InstFlags.RdRnFpSimdFromGpr), + new(0x1EC20000, 0x7FFF0000, sfscaleConstraints, InstName.ScvtfFloatFix, IsaVersion.v80, InstFlags.RdRnFpSimdFromGpr), + new(0x1E220000, 0x7FBFFC00, InstName.ScvtfFloatInt, IsaVersion.v80, InstFlags.RdRnFpSimdFromGpr), + new(0x1EE20000, 0x7FFFFC00, InstName.ScvtfFloatInt, IsaVersion.v80, InstFlags.RdRnFpSimdFromGpr), + new(0x1AC00C00, 0x7FE0FC00, InstName.Sdiv, IsaVersion.v80, InstFlags.RdRnRm), + new(0x0F80E000, 0xBFC0F400, InstName.SdotAdvsimdElt, IsaVersion.v82, InstFlags.RdReadRdRnRmFpSimd), + new(0x0E809400, 0xBFE0FC00, InstName.SdotAdvsimdVec, IsaVersion.v82, InstFlags.RdReadRdRnRmFpSimd), + new(0x3A00080D, 0xFFFFBC1F, InstName.Setf, IsaVersion.v84, InstFlags.RnC), + new(0x1DC00400, 0x3FE03C00, InstName.Setgp, IsaVersion.v88, InstFlags.RdRnRsS), + new(0x1DC02400, 0x3FE03C00, InstName.Setgpn, IsaVersion.v88, InstFlags.RdRnRsS), + new(0x1DC01400, 0x3FE03C00, InstName.Setgpt, IsaVersion.v88, InstFlags.RdRnRsS), + new(0x1DC03400, 0x3FE03C00, InstName.Setgptn, IsaVersion.v88, InstFlags.RdRnRsS), + new(0x19C00400, 0x3FE03C00, InstName.Setp, IsaVersion.v88, InstFlags.RdRnRsS), + new(0x19C02400, 0x3FE03C00, InstName.Setpn, IsaVersion.v88, InstFlags.RdRnRsS), + new(0x19C01400, 0x3FE03C00, InstName.Setpt, IsaVersion.v88, InstFlags.RdRnRsS), + new(0x19C03400, 0x3FE03C00, InstName.Setptn, IsaVersion.v88, InstFlags.RdRnRsS), + new(0xD503209F, 0xFFFFFFFF, InstName.Sev, IsaVersion.v80, InstFlags.None), + new(0xD50320BF, 0xFFFFFFFF, InstName.Sevl, IsaVersion.v80, InstFlags.None), + new(0x5E000000, 0xFFE0FC00, InstName.Sha1cAdvsimd, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x5E280800, 0xFFFFFC00, InstName.Sha1hAdvsimd, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x5E002000, 0xFFE0FC00, InstName.Sha1mAdvsimd, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x5E001000, 0xFFE0FC00, InstName.Sha1pAdvsimd, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x5E003000, 0xFFE0FC00, InstName.Sha1su0Advsimd, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x5E281800, 0xFFFFFC00, InstName.Sha1su1Advsimd, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x5E005000, 0xFFE0FC00, InstName.Sha256h2Advsimd, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x5E004000, 0xFFE0FC00, InstName.Sha256hAdvsimd, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x5E282800, 0xFFFFFC00, InstName.Sha256su0Advsimd, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x5E006000, 0xFFE0FC00, InstName.Sha256su1Advsimd, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0xCE608400, 0xFFE0FC00, InstName.Sha512h2Advsimd, IsaVersion.v82, InstFlags.RdRnRmFpSimd), + new(0xCE608000, 0xFFE0FC00, InstName.Sha512hAdvsimd, IsaVersion.v82, InstFlags.RdRnRmFpSimd), + new(0xCEC08000, 0xFFFFFC00, InstName.Sha512su0Advsimd, IsaVersion.v82, InstFlags.RdRnFpSimd), + new(0xCE608800, 0xFFE0FC00, InstName.Sha512su1Advsimd, IsaVersion.v82, InstFlags.RdRnRmFpSimd), + new(0x0E200400, 0xBF20FC00, sizeConstraints, InstName.ShaddAdvsimd, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x2E213800, 0xBF3FFC00, sizeConstraints, InstName.ShllAdvsimd, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x5F405400, 0xFFC0FC00, immhConstraints, InstName.ShlAdvsimdS, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x0F005400, 0xBF80FC00, immhQimmhConstraints, InstName.ShlAdvsimdV, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x0F008400, 0xBF80FC00, immhImmhConstraints, InstName.ShrnAdvsimd, IsaVersion.v80, InstFlags.RdReadRdRnFpSimd), + new(0x0E202400, 0xBF20FC00, sizeConstraints, InstName.ShsubAdvsimd, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x7F405400, 0xFFC0FC00, immhConstraints, InstName.SliAdvsimdS, IsaVersion.v80, InstFlags.RdReadRdRnFpSimd), + new(0x2F005400, 0xBF80FC00, immhQimmhConstraints, InstName.SliAdvsimdV, IsaVersion.v80, InstFlags.RdReadRdRnFpSimd), + new(0xCE60C000, 0xFFE0FC00, InstName.Sm3partw1Advsimd, IsaVersion.v82, InstFlags.RdRnRmFpSimd), + new(0xCE60C400, 0xFFE0FC00, InstName.Sm3partw2Advsimd, IsaVersion.v82, InstFlags.RdRnRmFpSimd), + new(0xCE400000, 0xFFE08000, InstName.Sm3ss1Advsimd, IsaVersion.v82, InstFlags.RdRnRmRaFpSimd), + new(0xCE408000, 0xFFE0CC00, InstName.Sm3tt1aAdvsimd, IsaVersion.v82, InstFlags.RdRnRmFpSimd), + new(0xCE408400, 0xFFE0CC00, InstName.Sm3tt1bAdvsimd, IsaVersion.v82, InstFlags.RdRnRmFpSimd), + new(0xCE408800, 0xFFE0CC00, InstName.Sm3tt2aAdvsimd, IsaVersion.v82, InstFlags.RdRnRmFpSimd), + new(0xCE408C00, 0xFFE0CC00, InstName.Sm3tt2bAdvsimd, IsaVersion.v82, InstFlags.RdRnRmFpSimd), + new(0xCE60C800, 0xFFE0FC00, InstName.Sm4ekeyAdvsimd, IsaVersion.v82, InstFlags.RdRnRmFpSimd), + new(0xCEC08400, 0xFFFFFC00, InstName.Sm4eAdvsimd, IsaVersion.v82, InstFlags.RdReadRdRnFpSimd), + new(0x9B200000, 0xFFE08000, InstName.Smaddl, IsaVersion.v80, InstFlags.RdRnRmRa), + new(0x0E20A400, 0xBF20FC00, sizeConstraints, InstName.SmaxpAdvsimd, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x0E30A800, 0xBF3FFC00, qsizeSizeConstraints, InstName.SmaxvAdvsimd, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x0E206400, 0xBF20FC00, sizeConstraints, InstName.SmaxAdvsimd, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x11C00000, 0x7FFC0000, InstName.SmaxImm, IsaVersion.v89, InstFlags.RdRn), + new(0x1AC06000, 0x7FE0FC00, InstName.SmaxReg, IsaVersion.v89, InstFlags.RdRnRm), + new(0xD4000003, 0xFFE0001F, InstName.Smc, IsaVersion.v80, InstFlags.None), + new(0x0E20AC00, 0xBF20FC00, sizeConstraints, InstName.SminpAdvsimd, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x0E31A800, 0xBF3FFC00, qsizeSizeConstraints, InstName.SminvAdvsimd, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x0E206C00, 0xBF20FC00, sizeConstraints, InstName.SminAdvsimd, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x11C80000, 0x7FFC0000, InstName.SminImm, IsaVersion.v89, InstFlags.RdRn), + new(0x1AC06800, 0x7FE0FC00, InstName.SminReg, IsaVersion.v89, InstFlags.RdRnRm), + new(0x0F002000, 0xBF00F400, sizeSizeConstraints, InstName.SmlalAdvsimdElt, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x0E208000, 0xBF20FC00, sizeConstraints, InstName.SmlalAdvsimdVec, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x0F006000, 0xBF00F400, sizeSizeConstraints, InstName.SmlslAdvsimdElt, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x0E20A000, 0xBF20FC00, sizeConstraints, InstName.SmlslAdvsimdVec, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x4E80A400, 0xFFE0FC00, InstName.SmmlaAdvsimdVec, IsaVersion.v86, InstFlags.RdRnRmFpSimd), + new(0x0E012C00, 0xBFE1FC00, InstName.SmovAdvsimd, IsaVersion.v80, InstFlags.RdRnFpSimdToGpr), + new(0x0E022C00, 0xBFE3FC00, InstName.SmovAdvsimd, IsaVersion.v80, InstFlags.RdRnFpSimdToGpr), + new(0x4E042C00, 0xFFE7FC00, InstName.SmovAdvsimd, IsaVersion.v80, InstFlags.RdRnFpSimdToGpr), + new(0x9B208000, 0xFFE08000, InstName.Smsubl, IsaVersion.v80, InstFlags.RdRnRmRa), + new(0x9B407C00, 0xFFE0FC00, InstName.Smulh, IsaVersion.v80, InstFlags.RdRnRm), + new(0x0F00A000, 0xBF00F400, sizeSizeConstraints, InstName.SmullAdvsimdElt, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x0E20C000, 0xBF20FC00, sizeConstraints, InstName.SmullAdvsimdVec, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x5E207800, 0xFF3FFC00, InstName.SqabsAdvsimdS, IsaVersion.v80, InstFlags.RdRnQcFpSimd), + new(0x0E207800, 0xBF3FFC00, qsizeConstraints, InstName.SqabsAdvsimdV, IsaVersion.v80, InstFlags.RdRnQcFpSimd), + new(0x5E200C00, 0xFF20FC00, InstName.SqaddAdvsimdS, IsaVersion.v80, InstFlags.RdRnRmQcFpSimd), + new(0x0E200C00, 0xBF20FC00, qsizeConstraints, InstName.SqaddAdvsimdV, IsaVersion.v80, InstFlags.RdRnRmQcFpSimd), + new(0x5F003000, 0xFF00F400, sizeSizeConstraints, InstName.SqdmlalAdvsimdElt2regScalar, IsaVersion.v80, InstFlags.RdRnRmQcFpSimd), + new(0x0F003000, 0xBF00F400, sizeSizeConstraints, InstName.SqdmlalAdvsimdElt2regElement, IsaVersion.v80, InstFlags.RdRnRmQcFpSimd), + new(0x5E209000, 0xFF20FC00, sizeSizeConstraints, InstName.SqdmlalAdvsimdVecS, IsaVersion.v80, InstFlags.RdRnRmQcFpSimd), + new(0x0E209000, 0xBF20FC00, sizeSizeConstraints, InstName.SqdmlalAdvsimdVecV, IsaVersion.v80, InstFlags.RdRnRmQcFpSimd), + new(0x5F007000, 0xFF00F400, sizeSizeConstraints, InstName.SqdmlslAdvsimdElt2regScalar, IsaVersion.v80, InstFlags.RdRnRmQcFpSimd), + new(0x0F007000, 0xBF00F400, sizeSizeConstraints, InstName.SqdmlslAdvsimdElt2regElement, IsaVersion.v80, InstFlags.RdRnRmQcFpSimd), + new(0x5E20B000, 0xFF20FC00, sizeSizeConstraints, InstName.SqdmlslAdvsimdVecS, IsaVersion.v80, InstFlags.RdRnRmQcFpSimd), + new(0x0E20B000, 0xBF20FC00, sizeSizeConstraints, InstName.SqdmlslAdvsimdVecV, IsaVersion.v80, InstFlags.RdRnRmQcFpSimd), + new(0x5F00C000, 0xFF00F400, sizeSizeConstraints, InstName.SqdmulhAdvsimdElt2regScalar, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x0F00C000, 0xBF00F400, sizeSizeConstraints, InstName.SqdmulhAdvsimdElt2regElement, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x5E20B400, 0xFF20FC00, sizeSizeConstraints4, InstName.SqdmulhAdvsimdVecS, IsaVersion.v80, InstFlags.RdRnRmQcFpSimd), + new(0x0E20B400, 0xBF20FC00, sizeSizeConstraints4, InstName.SqdmulhAdvsimdVecV, IsaVersion.v80, InstFlags.RdRnRmQcFpSimd), + new(0x5F00B000, 0xFF00F400, sizeSizeConstraints, InstName.SqdmullAdvsimdElt2regScalar, IsaVersion.v80, InstFlags.RdRnRmQcFpSimd), + new(0x0F00B000, 0xBF00F400, sizeSizeConstraints, InstName.SqdmullAdvsimdElt2regElement, IsaVersion.v80, InstFlags.RdRnRmQcFpSimd), + new(0x5E20D000, 0xFF20FC00, sizeSizeConstraints, InstName.SqdmullAdvsimdVecS, IsaVersion.v80, InstFlags.RdRnRmQcFpSimd), + new(0x0E20D000, 0xBF20FC00, sizeSizeConstraints, InstName.SqdmullAdvsimdVecV, IsaVersion.v80, InstFlags.RdRnRmQcFpSimd), + new(0x7E207800, 0xFF3FFC00, InstName.SqnegAdvsimdS, IsaVersion.v80, InstFlags.RdRnQcFpSimd), + new(0x2E207800, 0xBF3FFC00, qsizeConstraints, InstName.SqnegAdvsimdV, IsaVersion.v80, InstFlags.RdRnQcFpSimd), + new(0x7F00D000, 0xFF00F400, sizeSizeConstraints, InstName.SqrdmlahAdvsimdElt2regScalar, IsaVersion.v81, InstFlags.RdReadRdRnRmQcFpSimd), + new(0x2F00D000, 0xBF00F400, sizeSizeConstraints, InstName.SqrdmlahAdvsimdElt2regElement, IsaVersion.v81, InstFlags.RdReadRdRnRmQcFpSimd), + new(0x7E008400, 0xFF20FC00, sizeSizeConstraints4, InstName.SqrdmlahAdvsimdVecS, IsaVersion.v81, InstFlags.RdReadRdRnRmQcFpSimd), + new(0x2E008400, 0xBF20FC00, sizeSizeConstraints4, InstName.SqrdmlahAdvsimdVecV, IsaVersion.v81, InstFlags.RdReadRdRnRmQcFpSimd), + new(0x7F00F000, 0xFF00F400, sizeSizeConstraints, InstName.SqrdmlshAdvsimdElt2regScalar, IsaVersion.v81, InstFlags.RdReadRdRnRmQcFpSimd), + new(0x2F00F000, 0xBF00F400, sizeSizeConstraints, InstName.SqrdmlshAdvsimdElt2regElement, IsaVersion.v81, InstFlags.RdReadRdRnRmQcFpSimd), + new(0x7E008C00, 0xFF20FC00, sizeSizeConstraints4, InstName.SqrdmlshAdvsimdVecS, IsaVersion.v81, InstFlags.RdReadRdRnRmQcFpSimd), + new(0x2E008C00, 0xBF20FC00, sizeSizeConstraints4, InstName.SqrdmlshAdvsimdVecV, IsaVersion.v81, InstFlags.RdReadRdRnRmQcFpSimd), + new(0x5F00D000, 0xFF00F400, sizeSizeConstraints, InstName.SqrdmulhAdvsimdElt2regScalar, IsaVersion.v80, InstFlags.RdRnRmQcFpSimd), + new(0x0F00D000, 0xBF00F400, sizeSizeConstraints, InstName.SqrdmulhAdvsimdElt2regElement, IsaVersion.v80, InstFlags.RdRnRmQcFpSimd), + new(0x7E20B400, 0xFF20FC00, sizeSizeConstraints4, InstName.SqrdmulhAdvsimdVecS, IsaVersion.v80, InstFlags.RdRnRmQcFpSimd), + new(0x2E20B400, 0xBF20FC00, sizeSizeConstraints4, InstName.SqrdmulhAdvsimdVecV, IsaVersion.v80, InstFlags.RdRnRmQcFpSimd), + new(0x5E205C00, 0xFF20FC00, ssizeSsizeSsizeConstraints, InstName.SqrshlAdvsimdS, IsaVersion.v80, InstFlags.RdRnRmQcFpSimd), + new(0x0E205C00, 0xBF20FC00, qsizeConstraints, InstName.SqrshlAdvsimdV, IsaVersion.v80, InstFlags.RdRnRmQcFpSimd), + new(0x5F009C00, 0xFF80FC00, immhImmhConstraints, InstName.SqrshrnAdvsimdS, IsaVersion.v80, InstFlags.RdReadRdRnQcFpSimd), + new(0x0F009C00, 0xBF80FC00, immhImmhConstraints, InstName.SqrshrnAdvsimdV, IsaVersion.v80, InstFlags.RdReadRdRnQcFpSimd), + new(0x7F008C00, 0xFF80FC00, immhImmhConstraints, InstName.SqrshrunAdvsimdS, IsaVersion.v80, InstFlags.RdReadRdRnQcFpSimd), + new(0x2F008C00, 0xBF80FC00, immhImmhConstraints, InstName.SqrshrunAdvsimdV, IsaVersion.v80, InstFlags.RdReadRdRnQcFpSimd), + new(0x7F006400, 0xFF80FC00, immhOpuConstraints, InstName.SqshluAdvsimdS, IsaVersion.v80, InstFlags.RdRnQcFpSimd), + new(0x2F006400, 0xBF80FC00, immhQimmhOpuConstraints, InstName.SqshluAdvsimdV, IsaVersion.v80, InstFlags.RdRnQcFpSimd), + new(0x5F007400, 0xFF80FC00, immhOpuConstraints, InstName.SqshlAdvsimdImmS, IsaVersion.v80, InstFlags.RdRnQcFpSimd), + new(0x0F007400, 0xBF80FC00, immhQimmhOpuConstraints, InstName.SqshlAdvsimdImmV, IsaVersion.v80, InstFlags.RdRnQcFpSimd), + new(0x5E204C00, 0xFF20FC00, ssizeSsizeSsizeConstraints, InstName.SqshlAdvsimdRegS, IsaVersion.v80, InstFlags.RdRnRmQcFpSimd), + new(0x0E204C00, 0xBF20FC00, qsizeConstraints, InstName.SqshlAdvsimdRegV, IsaVersion.v80, InstFlags.RdRnRmQcFpSimd), + new(0x5F009400, 0xFF80FC00, immhImmhConstraints, InstName.SqshrnAdvsimdS, IsaVersion.v80, InstFlags.RdReadRdRnQcFpSimd), + new(0x0F009400, 0xBF80FC00, immhImmhConstraints, InstName.SqshrnAdvsimdV, IsaVersion.v80, InstFlags.RdReadRdRnQcFpSimd), + new(0x7F008400, 0xFF80FC00, immhImmhConstraints, InstName.SqshrunAdvsimdS, IsaVersion.v80, InstFlags.RdReadRdRnQcFpSimd), + new(0x2F008400, 0xBF80FC00, immhImmhConstraints, InstName.SqshrunAdvsimdV, IsaVersion.v80, InstFlags.RdReadRdRnQcFpSimd), + new(0x5E202C00, 0xFF20FC00, InstName.SqsubAdvsimdS, IsaVersion.v80, InstFlags.RdRnRmQcFpSimd), + new(0x0E202C00, 0xBF20FC00, qsizeConstraints, InstName.SqsubAdvsimdV, IsaVersion.v80, InstFlags.RdRnRmQcFpSimd), + new(0x5E214800, 0xFF3FFC00, sizeConstraints, InstName.SqxtnAdvsimdS, IsaVersion.v80, InstFlags.RdReadRdRnQcFpSimd), + new(0x0E214800, 0xBF3FFC00, sizeConstraints, InstName.SqxtnAdvsimdV, IsaVersion.v80, InstFlags.RdReadRdRnQcFpSimd), + new(0x7E212800, 0xFF3FFC00, sizeConstraints, InstName.SqxtunAdvsimdS, IsaVersion.v80, InstFlags.RdReadRdRnQcFpSimd), + new(0x2E212800, 0xBF3FFC00, sizeConstraints, InstName.SqxtunAdvsimdV, IsaVersion.v80, InstFlags.RdReadRdRnQcFpSimd), + new(0x0E201400, 0xBF20FC00, sizeConstraints, InstName.SrhaddAdvsimd, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x7F404400, 0xFFC0FC00, immhConstraints, InstName.SriAdvsimdS, IsaVersion.v80, InstFlags.RdReadRdRnFpSimd), + new(0x2F004400, 0xBF80FC00, immhQimmhConstraints, InstName.SriAdvsimdV, IsaVersion.v80, InstFlags.RdReadRdRnFpSimd), + new(0x5E205400, 0xFF20FC00, ssizeSsizeSsizeConstraints, InstName.SrshlAdvsimdS, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x0E205400, 0xBF20FC00, qsizeConstraints, InstName.SrshlAdvsimdV, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x5F402400, 0xFFC0FC00, immhConstraints, InstName.SrshrAdvsimdS, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x0F002400, 0xBF80FC00, immhQimmhConstraints, InstName.SrshrAdvsimdV, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x5F403400, 0xFFC0FC00, immhConstraints, InstName.SrsraAdvsimdS, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x0F003400, 0xBF80FC00, immhQimmhConstraints, InstName.SrsraAdvsimdV, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x0F00A400, 0xBF80FC00, immhImmhConstraints, InstName.SshllAdvsimd, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x5E204400, 0xFF20FC00, ssizeSsizeSsizeConstraints, InstName.SshlAdvsimdS, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x0E204400, 0xBF20FC00, qsizeConstraints, InstName.SshlAdvsimdV, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x5F400400, 0xFFC0FC00, immhConstraints, InstName.SshrAdvsimdS, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x0F000400, 0xBF80FC00, immhQimmhConstraints, InstName.SshrAdvsimdV, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x5F401400, 0xFFC0FC00, immhConstraints, InstName.SsraAdvsimdS, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x0F001400, 0xBF80FC00, immhQimmhConstraints, InstName.SsraAdvsimdV, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x0E202000, 0xBF20FC00, sizeConstraints, InstName.SsublAdvsimd, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x0E203000, 0xBF20FC00, sizeConstraints, InstName.SsubwAdvsimd, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x0C002000, 0xBFFFF000, InstName.St1AdvsimdMultAsNoPostIndex, IsaVersion.v80, InstFlags.RtSeqReadRtRnSPFpSimd, AddressForm.StructNoOffset), + new(0x0C006000, 0xBFFFF000, InstName.St1AdvsimdMultAsNoPostIndex, IsaVersion.v80, InstFlags.RtSeqReadRtRnSPFpSimd, AddressForm.StructNoOffset), + new(0x0C007000, 0xBFFFF000, InstName.St1AdvsimdMultAsNoPostIndex, IsaVersion.v80, InstFlags.RtSeqReadRtRnSPFpSimd, AddressForm.StructNoOffset), + new(0x0C00A000, 0xBFFFF000, InstName.St1AdvsimdMultAsNoPostIndex, IsaVersion.v80, InstFlags.RtSeqReadRtRnSPFpSimd, AddressForm.StructNoOffset), + new(0x0C006000, 0xBFFFF000, InstName.St1AdvsimdMultAsNoPostIndex, IsaVersion.v80, InstFlags.RtSeqReadRtRnSPFpSimd, AddressForm.StructNoOffset), + new(0x0C007000, 0xBFFFF000, InstName.St1AdvsimdMultAsNoPostIndex, IsaVersion.v80, InstFlags.RtSeqReadRtRnSPFpSimd, AddressForm.StructNoOffset), + new(0x0C00A000, 0xBFFFF000, InstName.St1AdvsimdMultAsNoPostIndex, IsaVersion.v80, InstFlags.RtSeqReadRtRnSPFpSimd, AddressForm.StructNoOffset), + new(0x0C802000, 0xBFE0F000, InstName.St1AdvsimdMultAsPostIndex, IsaVersion.v80, InstFlags.RtSeqReadRtRnSPRmFpSimdMemWBack, AddressForm.StructPostIndexedReg), + new(0x0C806000, 0xBFE0F000, InstName.St1AdvsimdMultAsPostIndex, IsaVersion.v80, InstFlags.RtSeqReadRtRnSPRmFpSimdMemWBack, AddressForm.StructPostIndexedReg), + new(0x0C807000, 0xBFE0F000, InstName.St1AdvsimdMultAsPostIndex, IsaVersion.v80, InstFlags.RtSeqReadRtRnSPRmFpSimdMemWBack, AddressForm.StructPostIndexedReg), + new(0x0C80A000, 0xBFE0F000, InstName.St1AdvsimdMultAsPostIndex, IsaVersion.v80, InstFlags.RtSeqReadRtRnSPRmFpSimdMemWBack, AddressForm.StructPostIndexedReg), + new(0x0C806000, 0xBFE0F000, InstName.St1AdvsimdMultAsPostIndex, IsaVersion.v80, InstFlags.RtSeqReadRtRnSPRmFpSimdMemWBack, AddressForm.StructPostIndexedReg), + new(0x0C807000, 0xBFE0F000, InstName.St1AdvsimdMultAsPostIndex, IsaVersion.v80, InstFlags.RtSeqReadRtRnSPRmFpSimdMemWBack, AddressForm.StructPostIndexedReg), + new(0x0C80A000, 0xBFE0F000, InstName.St1AdvsimdMultAsPostIndex, IsaVersion.v80, InstFlags.RtSeqReadRtRnSPRmFpSimdMemWBack, AddressForm.StructPostIndexedReg), + new(0x0D000000, 0xBFFF2000, opcodesizeOpcodesizeOpcodesizesOpcodesizeConstraints, InstName.St1AdvsimdSnglAsNoPostIndex, IsaVersion.v80, InstFlags.RtReadRtRnSPFpSimd, AddressForm.StructNoOffset), + new(0x0D800000, 0xBFE02000, opcodesizeOpcodesizeOpcodesizesOpcodesizeConstraints, InstName.St1AdvsimdSnglAsPostIndex, IsaVersion.v80, InstFlags.RtReadRtRnSPRmFpSimdMemWBack, AddressForm.StructPostIndexedReg), + new(0xD9A00400, 0xFFE00C00, InstName.St2gPostIndexed, IsaVersion.v85, InstFlags.MemWBack, AddressForm.PostIndexed), + new(0xD9A00C00, 0xFFE00C00, InstName.St2gPreIndexed, IsaVersion.v85, InstFlags.MemWBack, AddressForm.PreIndexed), + new(0xD9A00800, 0xFFE00C00, InstName.St2gSignedScaledOffset, IsaVersion.v85, InstFlags.None, AddressForm.SignedScaled), + new(0x0C008000, 0xBFFFF000, qsizeConstraints2, InstName.St2AdvsimdMultAsNoPostIndex, IsaVersion.v80, InstFlags.RtSeqReadRtRnSPFpSimd, AddressForm.StructNoOffset), + new(0x0C808000, 0xBFE0F000, qsizeConstraints2, InstName.St2AdvsimdMultAsPostIndex, IsaVersion.v80, InstFlags.RtSeqReadRtRnSPRmFpSimdMemWBack, AddressForm.StructPostIndexedReg), + new(0x0D200000, 0xBFFF2000, opcodesizeOpcodesizeOpcodesizesOpcodesizeConstraints, InstName.St2AdvsimdSnglAsNoPostIndex, IsaVersion.v80, InstFlags.RtSeqReadRtRnSPFpSimd, AddressForm.StructNoOffset), + new(0x0DA00000, 0xBFE02000, opcodesizeOpcodesizeOpcodesizesOpcodesizeConstraints, InstName.St2AdvsimdSnglAsPostIndex, IsaVersion.v80, InstFlags.RtSeqReadRtRnSPRmFpSimdMemWBack, AddressForm.StructPostIndexedReg), + new(0x0C004000, 0xBFFFF000, qsizeConstraints2, InstName.St3AdvsimdMultAsNoPostIndex, IsaVersion.v80, InstFlags.RtSeqReadRtRnSPFpSimd, AddressForm.StructNoOffset), + new(0x0C804000, 0xBFE0F000, qsizeConstraints2, InstName.St3AdvsimdMultAsPostIndex, IsaVersion.v80, InstFlags.RtSeqReadRtRnSPRmFpSimdMemWBack, AddressForm.StructPostIndexedReg), + new(0x0D002000, 0xBFFF2000, opcodesizeOpcodesizeOpcodesizesOpcodesizeConstraints, InstName.St3AdvsimdSnglAsNoPostIndex, IsaVersion.v80, InstFlags.RtSeqReadRtRnSPFpSimd, AddressForm.StructNoOffset), + new(0x0D802000, 0xBFE02000, opcodesizeOpcodesizeOpcodesizesOpcodesizeConstraints, InstName.St3AdvsimdSnglAsPostIndex, IsaVersion.v80, InstFlags.RtSeqReadRtRnSPRmFpSimdMemWBack, AddressForm.StructPostIndexedReg), + new(0x0C000000, 0xBFFFF000, qsizeConstraints2, InstName.St4AdvsimdMultAsNoPostIndex, IsaVersion.v80, InstFlags.RtSeqReadRtRnSPFpSimd, AddressForm.StructNoOffset), + new(0x0C800000, 0xBFE0F000, qsizeConstraints2, InstName.St4AdvsimdMultAsPostIndex, IsaVersion.v80, InstFlags.RtSeqReadRtRnSPRmFpSimdMemWBack, AddressForm.StructPostIndexedReg), + new(0x0D202000, 0xBFFF2000, opcodesizeOpcodesizeOpcodesizesOpcodesizeConstraints, InstName.St4AdvsimdSnglAsNoPostIndex, IsaVersion.v80, InstFlags.RtSeqReadRtRnSPFpSimd, AddressForm.StructNoOffset), + new(0x0DA02000, 0xBFE02000, opcodesizeOpcodesizeOpcodesizesOpcodesizeConstraints, InstName.St4AdvsimdSnglAsPostIndex, IsaVersion.v80, InstFlags.RtSeqReadRtRnSPRmFpSimdMemWBack, AddressForm.StructPostIndexedReg), + new(0xF83F9000, 0xFFFFFC00, rtRtConstraints, InstName.St64b, IsaVersion.v87, InstFlags.RtReadRtRnSP), + new(0xF820B000, 0xFFE0FC00, rtRtConstraints, InstName.St64bv, IsaVersion.v87, InstFlags.RtReadRtRnSPRs), + new(0xF820A000, 0xFFE0FC00, rtRtConstraints, InstName.St64bv0, IsaVersion.v87, InstFlags.RtReadRtRnSPRs), + new(0xD9200400, 0xFFE00C00, InstName.StgPostIndexed, IsaVersion.v85, InstFlags.MemWBack, AddressForm.PostIndexed), + new(0xD9200C00, 0xFFE00C00, InstName.StgPreIndexed, IsaVersion.v85, InstFlags.MemWBack, AddressForm.PreIndexed), + new(0xD9200800, 0xFFE00C00, InstName.StgSignedScaledOffset, IsaVersion.v85, InstFlags.None, AddressForm.SignedScaled), + new(0xD9A00000, 0xFFFFFC00, InstName.Stgm, IsaVersion.v85, InstFlags.None), + new(0x68800000, 0xFFC00000, InstName.StgpPostIndexed, IsaVersion.v85, InstFlags.MemWBack, AddressForm.PostIndexed), + new(0x69800000, 0xFFC00000, InstName.StgpPreIndexed, IsaVersion.v85, InstFlags.MemWBack, AddressForm.PreIndexed), + new(0x69000000, 0xFFC00000, InstName.StgpSignedScaledOffset, IsaVersion.v85, InstFlags.None, AddressForm.SignedScaled), + new(0x99000800, 0xBFE0EC00, InstName.Stilp, IsaVersion.v82, InstFlags.RtReadRtRt2RnSP), + new(0x0D018400, 0xBFFFFC00, opcodesizeOpcodesizeOpcodesizesOpcodesizeConstraints, InstName.Stl1AdvsimdSngl, IsaVersion.v82, InstFlags.RtReadRtRnSPFpSimd, AddressForm.StructNoOffset), + new(0x889F7C00, 0xBFFFFC00, InstName.Stllr, IsaVersion.v81, InstFlags.RtReadRtRnSP, AddressForm.BaseRegister), + new(0x089F7C00, 0xFFFFFC00, InstName.Stllrb, IsaVersion.v81, InstFlags.RtReadRtRnSP, AddressForm.BaseRegister), + new(0x489F7C00, 0xFFFFFC00, InstName.Stllrh, IsaVersion.v81, InstFlags.RtReadRtRnSP, AddressForm.BaseRegister), + new(0x889FFC00, 0xBFFFFC00, InstName.StlrBaseRegister, IsaVersion.v80, InstFlags.RtReadRtRnSP, AddressForm.BaseRegister), + new(0x99800800, 0xBFFFFC00, InstName.StlrPreIndexed, IsaVersion.v82, InstFlags.RtReadRtRnSPMemWBack, AddressForm.PreIndexed), + new(0x089FFC00, 0xFFFFFC00, InstName.Stlrb, IsaVersion.v80, InstFlags.RtReadRtRnSP, AddressForm.BaseRegister), + new(0x489FFC00, 0xFFFFFC00, InstName.Stlrh, IsaVersion.v80, InstFlags.RtReadRtRnSP, AddressForm.BaseRegister), + new(0x19000000, 0xFFE00C00, InstName.Stlurb, IsaVersion.v84, InstFlags.RtReadRtRnSP, AddressForm.BasePlusOffset), + new(0x59000000, 0xFFE00C00, InstName.Stlurh, IsaVersion.v84, InstFlags.RtReadRtRnSP, AddressForm.BasePlusOffset), + new(0x1D000800, 0x3F600C00, opc1sizeOpc1sizeOpc1sizeConstraints, InstName.StlurFpsimd, IsaVersion.v82, InstFlags.RtReadRtRnSPFpSimd, AddressForm.BasePlusOffset), + new(0x99000000, 0xBFE00C00, InstName.StlurGen, IsaVersion.v84, InstFlags.RtReadRtRnSP, AddressForm.BasePlusOffset), + new(0x88208000, 0xBFE08000, InstName.Stlxp, IsaVersion.v80, InstFlags.RtReadRtRt2RnSPRs, AddressForm.BaseRegister), + new(0x8800FC00, 0xBFE0FC00, InstName.Stlxr, IsaVersion.v80, InstFlags.RtReadRtRnSPRs, AddressForm.BaseRegister), + new(0x0800FC00, 0xFFE0FC00, InstName.Stlxrb, IsaVersion.v80, InstFlags.RtReadRtRnSPRs, AddressForm.BaseRegister), + new(0x4800FC00, 0xFFE0FC00, InstName.Stlxrh, IsaVersion.v80, InstFlags.RtReadRtRnSPRs, AddressForm.BaseRegister), + new(0x2C000000, 0x3FC00000, opcConstraints, InstName.StnpFpsimd, IsaVersion.v80, InstFlags.RtReadRtRt2RnSPFpSimd, AddressForm.SignedScaled), + new(0x28000000, 0x7FC00000, opcConstraints2, InstName.StnpGen, IsaVersion.v80, InstFlags.RtReadRtRt2RnSP, AddressForm.SignedScaled), + new(0x2C800000, 0x3FC00000, opcConstraints, InstName.StpFpsimdPostIndexed, IsaVersion.v80, InstFlags.RtReadRtRt2RnSPFpSimdMemWBack, AddressForm.PostIndexed), + new(0x2D800000, 0x3FC00000, opcConstraints, InstName.StpFpsimdPreIndexed, IsaVersion.v80, InstFlags.RtReadRtRt2RnSPFpSimdMemWBack, AddressForm.PreIndexed), + new(0x2D000000, 0x3FC00000, opcConstraints, InstName.StpFpsimdSignedScaledOffset, IsaVersion.v80, InstFlags.RtReadRtRt2RnSPFpSimd, AddressForm.SignedScaled), + new(0x28800000, 0x7FC00000, opclOpcConstraints, InstName.StpGenPostIndexed, IsaVersion.v80, InstFlags.RtReadRtRt2RnSPMemWBack, AddressForm.PostIndexed), + new(0x29800000, 0x7FC00000, opclOpcConstraints, InstName.StpGenPreIndexed, IsaVersion.v80, InstFlags.RtReadRtRt2RnSPMemWBack, AddressForm.PreIndexed), + new(0x29000000, 0x7FC00000, opclOpcConstraints, InstName.StpGenSignedScaledOffset, IsaVersion.v80, InstFlags.RtReadRtRt2RnSP, AddressForm.SignedScaled), + new(0x38000400, 0xFFE00C00, InstName.StrbImmPostIndexed, IsaVersion.v80, InstFlags.RtReadRtRnSPMemWBack, AddressForm.PostIndexed), + new(0x38000C00, 0xFFE00C00, InstName.StrbImmPreIndexed, IsaVersion.v80, InstFlags.RtReadRtRnSPMemWBack, AddressForm.PreIndexed), + new(0x39000000, 0xFFC00000, InstName.StrbImmUnsignedScaledOffset, IsaVersion.v80, InstFlags.RtReadRtRnSP, AddressForm.UnsignedScaled), + new(0x38200800, 0xFFE00C00, optionConstraints, InstName.StrbReg, IsaVersion.v80, InstFlags.RtReadRtRnSPRm, AddressForm.OffsetReg), + new(0x78000400, 0xFFE00C00, InstName.StrhImmPostIndexed, IsaVersion.v80, InstFlags.RtReadRtRnSPMemWBack, AddressForm.PostIndexed), + new(0x78000C00, 0xFFE00C00, InstName.StrhImmPreIndexed, IsaVersion.v80, InstFlags.RtReadRtRnSPMemWBack, AddressForm.PreIndexed), + new(0x79000000, 0xFFC00000, InstName.StrhImmUnsignedScaledOffset, IsaVersion.v80, InstFlags.RtReadRtRnSP, AddressForm.UnsignedScaled), + new(0x78200800, 0xFFE00C00, optionConstraints, InstName.StrhReg, IsaVersion.v80, InstFlags.RtReadRtRnSPRm, AddressForm.OffsetReg), + new(0x3C000400, 0x3F600C00, opc1sizeOpc1sizeOpc1sizeConstraints, InstName.StrImmFpsimdPostIndexed, IsaVersion.v80, InstFlags.RtReadRtRnSPFpSimdMemWBack, AddressForm.PostIndexed), + new(0x3C000C00, 0x3F600C00, opc1sizeOpc1sizeOpc1sizeConstraints, InstName.StrImmFpsimdPreIndexed, IsaVersion.v80, InstFlags.RtReadRtRnSPFpSimdMemWBack, AddressForm.PreIndexed), + new(0x3D000000, 0x3F400000, opc1sizeOpc1sizeOpc1sizeConstraints, InstName.StrImmFpsimdUnsignedScaledOffset, IsaVersion.v80, InstFlags.RtReadRtRnSPFpSimd, AddressForm.UnsignedScaled), + new(0xB8000400, 0xBFE00C00, InstName.StrImmGenPostIndexed, IsaVersion.v80, InstFlags.RtReadRtRnSPMemWBack, AddressForm.PostIndexed), + new(0xB8000C00, 0xBFE00C00, InstName.StrImmGenPreIndexed, IsaVersion.v80, InstFlags.RtReadRtRnSPMemWBack, AddressForm.PreIndexed), + new(0xB9000000, 0xBFC00000, InstName.StrImmGenUnsignedScaledOffset, IsaVersion.v80, InstFlags.RtReadRtRnSP, AddressForm.UnsignedScaled), + new(0x3C200800, 0x3F600C00, opc1sizeOpc1sizeOpc1sizeOptionConstraints, InstName.StrRegFpsimd, IsaVersion.v80, InstFlags.RtReadRtRnSPRmFpSimd, AddressForm.OffsetReg), + new(0xB8200800, 0xBFE00C00, optionConstraints, InstName.StrRegGen, IsaVersion.v80, InstFlags.RtReadRtRnSPRm, AddressForm.OffsetReg), + new(0xB8000800, 0xBFE00C00, InstName.Sttr, IsaVersion.v80, InstFlags.RtReadRtRnSP, AddressForm.BasePlusOffset), + new(0x38000800, 0xFFE00C00, InstName.Sttrb, IsaVersion.v80, InstFlags.RtReadRtRnSP, AddressForm.BasePlusOffset), + new(0x78000800, 0xFFE00C00, InstName.Sttrh, IsaVersion.v80, InstFlags.RtReadRtRnSP, AddressForm.BasePlusOffset), + new(0x38000000, 0xFFE00C00, InstName.Sturb, IsaVersion.v80, InstFlags.RtReadRtRnSP, AddressForm.BasePlusOffset), + new(0x78000000, 0xFFE00C00, InstName.Sturh, IsaVersion.v80, InstFlags.RtReadRtRnSP, AddressForm.BasePlusOffset), + new(0x3C000000, 0x3F600C00, opc1sizeOpc1sizeOpc1sizeConstraints, InstName.SturFpsimd, IsaVersion.v80, InstFlags.RtReadRtRnSPFpSimd, AddressForm.BasePlusOffset), + new(0xB8000000, 0xBFE00C00, InstName.SturGen, IsaVersion.v80, InstFlags.RtReadRtRnSP, AddressForm.BasePlusOffset), + new(0x88200000, 0xBFE08000, InstName.Stxp, IsaVersion.v80, InstFlags.RtReadRtRt2RnSPRs, AddressForm.BaseRegister), + new(0x88007C00, 0xBFE0FC00, InstName.Stxr, IsaVersion.v80, InstFlags.RtReadRtRnSPRs, AddressForm.BaseRegister), + new(0x08007C00, 0xFFE0FC00, InstName.Stxrb, IsaVersion.v80, InstFlags.RtReadRtRnSPRs, AddressForm.BaseRegister), + new(0x48007C00, 0xFFE0FC00, InstName.Stxrh, IsaVersion.v80, InstFlags.RtReadRtRnSPRs, AddressForm.BaseRegister), + new(0xD9E00400, 0xFFE00C00, InstName.Stz2gPostIndexed, IsaVersion.v85, InstFlags.MemWBack, AddressForm.PostIndexed), + new(0xD9E00C00, 0xFFE00C00, InstName.Stz2gPreIndexed, IsaVersion.v85, InstFlags.MemWBack, AddressForm.PreIndexed), + new(0xD9E00800, 0xFFE00C00, InstName.Stz2gSignedScaledOffset, IsaVersion.v85, InstFlags.None, AddressForm.SignedScaled), + new(0xD9600400, 0xFFE00C00, InstName.StzgPostIndexed, IsaVersion.v85, InstFlags.MemWBack, AddressForm.PostIndexed), + new(0xD9600C00, 0xFFE00C00, InstName.StzgPreIndexed, IsaVersion.v85, InstFlags.MemWBack, AddressForm.PreIndexed), + new(0xD9600800, 0xFFE00C00, InstName.StzgSignedScaledOffset, IsaVersion.v85, InstFlags.None, AddressForm.SignedScaled), + new(0xD9200000, 0xFFFFFC00, InstName.Stzgm, IsaVersion.v85, InstFlags.None), + new(0xD1800000, 0xFFC0C000, InstName.Subg, IsaVersion.v85, InstFlags.None), + new(0x0E206000, 0xBF20FC00, sizeConstraints, InstName.SubhnAdvsimd, IsaVersion.v80, InstFlags.RdReadRdRnRmFpSimd), + new(0x9AC00000, 0xFFE0FC00, InstName.Subp, IsaVersion.v85, InstFlags.None), + new(0xBAC00000, 0xFFE0FC00, InstName.Subps, IsaVersion.v85, InstFlags.S), + new(0x6B200000, 0x7FE00000, opuOpuOpuConstraints, InstName.SubsAddsubExt, IsaVersion.v80, InstFlags.RdRnSPRmS), + new(0x71000000, 0x7F800000, InstName.SubsAddsubImm, IsaVersion.v80, InstFlags.RdRnSPS), + new(0x6B000000, 0x7F200000, shiftSfimm6Constraints, InstName.SubsAddsubShift, IsaVersion.v80, InstFlags.RdRnRmS), + new(0x4B200000, 0x7FE00000, opuOpuOpuConstraints, InstName.SubAddsubExt, IsaVersion.v80, InstFlags.RdSPRnSPRm), + new(0x51000000, 0x7F800000, InstName.SubAddsubImm, IsaVersion.v80, InstFlags.RdSPRnSP), + new(0x4B000000, 0x7F200000, shiftSfimm6Constraints, InstName.SubAddsubShift, IsaVersion.v80, InstFlags.RdRnRm), + new(0x7EE08400, 0xFFE0FC00, InstName.SubAdvsimdS, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x2E208400, 0xBF20FC00, qsizeConstraints, InstName.SubAdvsimdV, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x0F00F000, 0xBFC0F400, InstName.SudotAdvsimdElt, IsaVersion.v86, InstFlags.RdReadRdRnRmFpSimd), + new(0x5E203800, 0xFF3FFC00, InstName.SuqaddAdvsimdS, IsaVersion.v80, InstFlags.RdReadRdRnQcFpSimd), + new(0x0E203800, 0xBF3FFC00, qsizeConstraints, InstName.SuqaddAdvsimdV, IsaVersion.v80, InstFlags.RdReadRdRnQcFpSimd), + new(0xD4000001, 0xFFE0001F, InstName.Svc, IsaVersion.v80, InstFlags.None), + new(0xB8208000, 0xBF20FC00, InstName.Swp, IsaVersion.v81, InstFlags.RtReadRtRnSPRs), + new(0x38208000, 0xFF20FC00, InstName.Swpb, IsaVersion.v81, InstFlags.RtReadRtRnSPRs), + new(0x78208000, 0xFF20FC00, InstName.Swph, IsaVersion.v81, InstFlags.RtReadRtRnSPRs), + new(0x19208000, 0xFF20FC00, rtRt2Constraints, InstName.Swpp, IsaVersion.None, InstFlags.RtReadRtRt2RnSP), + new(0xD5080000, 0xFFF80000, InstName.Sys, IsaVersion.v80, InstFlags.RtReadRt), + new(0xD5280000, 0xFFF80000, InstName.Sysl, IsaVersion.v80, InstFlags.Rt), + new(0xD5480000, 0xFFF80000, InstName.Sysp, IsaVersion.None, InstFlags.RtReadRt), + new(0x0E000000, 0xBFE09C00, InstName.TblAdvsimd, IsaVersion.v80, InstFlags.RdRnSeqRmFpSimd), + new(0x37000000, 0x7F000000, InstName.Tbnz, IsaVersion.v80, InstFlags.RtReadRt), + new(0x0E001000, 0xBFE09C00, InstName.TbxAdvsimd, IsaVersion.v80, InstFlags.RdRnSeqRmFpSimd), + new(0x36000000, 0x7F000000, InstName.Tbz, IsaVersion.v80, InstFlags.RtReadRt), + new(0xD4600000, 0xFFE0001F, InstName.Tcancel, IsaVersion.None, InstFlags.None), + new(0xD503307F, 0xFFFFFFFF, InstName.Tcommit, IsaVersion.None, InstFlags.None), + new(0x0E002800, 0xBF20FC00, qsizeConstraints, InstName.Trn1Advsimd, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x0E006800, 0xBF20FC00, qsizeConstraints, InstName.Trn2Advsimd, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0xD503225F, 0xFFFFFFFF, InstName.Tsb, IsaVersion.v84, InstFlags.None), + new(0xD5233060, 0xFFFFFFE0, InstName.Tstart, IsaVersion.None, InstFlags.RtReadRt), + new(0xD5233160, 0xFFFFFFE0, InstName.Ttest, IsaVersion.None, InstFlags.RtReadRt), + new(0x2E205000, 0xBF20FC00, sizeConstraints, InstName.UabalAdvsimd, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x2E207C00, 0xBF20FC00, sizeConstraints, InstName.UabaAdvsimd, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x2E207000, 0xBF20FC00, sizeConstraints, InstName.UabdlAdvsimd, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x2E207400, 0xBF20FC00, sizeConstraints, InstName.UabdAdvsimd, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x2E206800, 0xBF3FFC00, sizeConstraints, InstName.UadalpAdvsimd, IsaVersion.v80, InstFlags.RdReadRdRnFpSimd), + new(0x2E202800, 0xBF3FFC00, sizeConstraints, InstName.UaddlpAdvsimd, IsaVersion.v80, InstFlags.RdReadRdRnFpSimd), + new(0x2E303800, 0xBF3FFC00, qsizeSizeConstraints, InstName.UaddlvAdvsimd, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x2E200000, 0xBF20FC00, sizeConstraints, InstName.UaddlAdvsimd, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x2E201000, 0xBF20FC00, sizeConstraints, InstName.UaddwAdvsimd, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x53000000, 0x7F800000, sfnSfnSfimmr5Sfimms5Constraints, InstName.Ubfm, IsaVersion.v80, InstFlags.RdRn), + new(0x7F40E400, 0xFFC0FC00, immhConstraints, InstName.UcvtfAdvsimdFixS, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x7F10E400, 0xFFF0FC00, immhConstraints, InstName.UcvtfAdvsimdFixS, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x7F20E400, 0xFFE0FC00, immhConstraints, InstName.UcvtfAdvsimdFixS, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x2F40E400, 0xBFC0FC00, immhQimmhConstraints, InstName.UcvtfAdvsimdFixV, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x2F10E400, 0xBFF0FC00, immhQimmhConstraints, InstName.UcvtfAdvsimdFixV, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x2F20E400, 0xBFE0FC00, immhQimmhConstraints, InstName.UcvtfAdvsimdFixV, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x7E79D800, 0xFFFFFC00, InstName.UcvtfAdvsimdIntSH, IsaVersion.v82, InstFlags.RdRnFpSimd), + new(0x7E21D800, 0xFFBFFC00, InstName.UcvtfAdvsimdIntS, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x2E79D800, 0xBFFFFC00, InstName.UcvtfAdvsimdIntVH, IsaVersion.v82, InstFlags.RdRnFpSimd), + new(0x2E21D800, 0xBFBFFC00, qszConstraints, InstName.UcvtfAdvsimdIntV, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x1E030000, 0x7FBF0000, sfscaleConstraints, InstName.UcvtfFloatFix, IsaVersion.v80, InstFlags.RdRnFpSimdFromGpr), + new(0x1EC30000, 0x7FFF0000, sfscaleConstraints, InstName.UcvtfFloatFix, IsaVersion.v80, InstFlags.RdRnFpSimdFromGpr), + new(0x1E230000, 0x7FBFFC00, InstName.UcvtfFloatInt, IsaVersion.v80, InstFlags.RdRnFpSimdFromGpr), + new(0x1EE30000, 0x7FFFFC00, InstName.UcvtfFloatInt, IsaVersion.v80, InstFlags.RdRnFpSimdFromGpr), + new(0x00000000, 0xFFFF0000, InstName.UdfPermUndef, IsaVersion.v80, InstFlags.None), + new(0x1AC00800, 0x7FE0FC00, InstName.Udiv, IsaVersion.v80, InstFlags.RdRnRm), + new(0x2F80E000, 0xBFC0F400, InstName.UdotAdvsimdElt, IsaVersion.v82, InstFlags.RdReadRdRnRmFpSimd), + new(0x2E809400, 0xBFE0FC00, InstName.UdotAdvsimdVec, IsaVersion.v82, InstFlags.RdReadRdRnRmFpSimd), + new(0x2E200400, 0xBF20FC00, sizeConstraints, InstName.UhaddAdvsimd, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x2E202400, 0xBF20FC00, sizeConstraints, InstName.UhsubAdvsimd, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x9BA00000, 0xFFE08000, InstName.Umaddl, IsaVersion.v80, InstFlags.RdRnRmRa), + new(0x2E20A400, 0xBF20FC00, sizeConstraints, InstName.UmaxpAdvsimd, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x2E30A800, 0xBF3FFC00, qsizeSizeConstraints, InstName.UmaxvAdvsimd, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x2E206400, 0xBF20FC00, sizeConstraints, InstName.UmaxAdvsimd, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x11C40000, 0x7FFC0000, InstName.UmaxImm, IsaVersion.v89, InstFlags.RdRn), + new(0x1AC06400, 0x7FE0FC00, InstName.UmaxReg, IsaVersion.v89, InstFlags.RdRnRm), + new(0x2E20AC00, 0xBF20FC00, sizeConstraints, InstName.UminpAdvsimd, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x2E31A800, 0xBF3FFC00, qsizeSizeConstraints, InstName.UminvAdvsimd, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x2E206C00, 0xBF20FC00, sizeConstraints, InstName.UminAdvsimd, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x11CC0000, 0x7FFC0000, InstName.UminImm, IsaVersion.v89, InstFlags.RdRn), + new(0x1AC06C00, 0x7FE0FC00, InstName.UminReg, IsaVersion.v89, InstFlags.RdRnRm), + new(0x2F002000, 0xBF00F400, sizeSizeConstraints, InstName.UmlalAdvsimdElt, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x2E208000, 0xBF20FC00, sizeConstraints, InstName.UmlalAdvsimdVec, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x2F006000, 0xBF00F400, sizeSizeConstraints, InstName.UmlslAdvsimdElt, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x2E20A000, 0xBF20FC00, sizeConstraints, InstName.UmlslAdvsimdVec, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x6E80A400, 0xFFE0FC00, InstName.UmmlaAdvsimdVec, IsaVersion.v86, InstFlags.RdRnRmFpSimd), + new(0x0E013C00, 0xFFE1FC00, InstName.UmovAdvsimd, IsaVersion.v80, InstFlags.RdRnFpSimdToGpr), + new(0x0E023C00, 0xFFE3FC00, InstName.UmovAdvsimd, IsaVersion.v80, InstFlags.RdRnFpSimdToGpr), + new(0x0E043C00, 0xFFE7FC00, InstName.UmovAdvsimd, IsaVersion.v80, InstFlags.RdRnFpSimdToGpr), + new(0x4E083C00, 0xFFEFFC00, InstName.UmovAdvsimd, IsaVersion.v80, InstFlags.RdRnFpSimdToGpr), + new(0x9BA08000, 0xFFE08000, InstName.Umsubl, IsaVersion.v80, InstFlags.RdRnRmRa), + new(0x9BC07C00, 0xFFE0FC00, InstName.Umulh, IsaVersion.v80, InstFlags.RdRnRm), + new(0x2F00A000, 0xBF00F400, sizeSizeConstraints, InstName.UmullAdvsimdElt, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x2E20C000, 0xBF20FC00, sizeConstraints, InstName.UmullAdvsimdVec, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x7E200C00, 0xFF20FC00, InstName.UqaddAdvsimdS, IsaVersion.v80, InstFlags.RdRnRmQcFpSimd), + new(0x2E200C00, 0xBF20FC00, qsizeConstraints, InstName.UqaddAdvsimdV, IsaVersion.v80, InstFlags.RdRnRmQcFpSimd), + new(0x7E205C00, 0xFF20FC00, ssizeSsizeSsizeConstraints, InstName.UqrshlAdvsimdS, IsaVersion.v80, InstFlags.RdRnRmQcFpSimd), + new(0x2E205C00, 0xBF20FC00, qsizeConstraints, InstName.UqrshlAdvsimdV, IsaVersion.v80, InstFlags.RdRnRmQcFpSimd), + new(0x7F009C00, 0xFF80FC00, immhImmhConstraints, InstName.UqrshrnAdvsimdS, IsaVersion.v80, InstFlags.RdReadRdRnQcFpSimd), + new(0x2F009C00, 0xBF80FC00, immhImmhConstraints, InstName.UqrshrnAdvsimdV, IsaVersion.v80, InstFlags.RdReadRdRnQcFpSimd), + new(0x7F007400, 0xFF80FC00, immhOpuConstraints, InstName.UqshlAdvsimdImmS, IsaVersion.v80, InstFlags.RdRnQcFpSimd), + new(0x2F007400, 0xBF80FC00, immhQimmhOpuConstraints, InstName.UqshlAdvsimdImmV, IsaVersion.v80, InstFlags.RdRnQcFpSimd), + new(0x7E204C00, 0xFF20FC00, ssizeSsizeSsizeConstraints, InstName.UqshlAdvsimdRegS, IsaVersion.v80, InstFlags.RdRnRmQcFpSimd), + new(0x2E204C00, 0xBF20FC00, qsizeConstraints, InstName.UqshlAdvsimdRegV, IsaVersion.v80, InstFlags.RdRnRmQcFpSimd), + new(0x7F009400, 0xFF80FC00, immhImmhConstraints, InstName.UqshrnAdvsimdS, IsaVersion.v80, InstFlags.RdReadRdRnQcFpSimd), + new(0x2F009400, 0xBF80FC00, immhImmhConstraints, InstName.UqshrnAdvsimdV, IsaVersion.v80, InstFlags.RdReadRdRnQcFpSimd), + new(0x7E202C00, 0xFF20FC00, InstName.UqsubAdvsimdS, IsaVersion.v80, InstFlags.RdRnRmQcFpSimd), + new(0x2E202C00, 0xBF20FC00, qsizeConstraints, InstName.UqsubAdvsimdV, IsaVersion.v80, InstFlags.RdRnRmQcFpSimd), + new(0x7E214800, 0xFF3FFC00, sizeConstraints, InstName.UqxtnAdvsimdS, IsaVersion.v80, InstFlags.RdReadRdRnQcFpSimd), + new(0x2E214800, 0xBF3FFC00, sizeConstraints, InstName.UqxtnAdvsimdV, IsaVersion.v80, InstFlags.RdReadRdRnQcFpSimd), + new(0x0EA1C800, 0xBFBFFC00, szConstraints, InstName.UrecpeAdvsimd, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x2E201400, 0xBF20FC00, sizeConstraints, InstName.UrhaddAdvsimd, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x7E205400, 0xFF20FC00, ssizeSsizeSsizeConstraints, InstName.UrshlAdvsimdS, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x2E205400, 0xBF20FC00, qsizeConstraints, InstName.UrshlAdvsimdV, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x7F402400, 0xFFC0FC00, immhConstraints, InstName.UrshrAdvsimdS, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x2F002400, 0xBF80FC00, immhQimmhConstraints, InstName.UrshrAdvsimdV, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x2EA1C800, 0xBFBFFC00, szConstraints, InstName.UrsqrteAdvsimd, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x7F403400, 0xFFC0FC00, immhConstraints, InstName.UrsraAdvsimdS, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x2F003400, 0xBF80FC00, immhQimmhConstraints, InstName.UrsraAdvsimdV, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x0F80F000, 0xBFC0F400, InstName.UsdotAdvsimdElt, IsaVersion.v86, InstFlags.RdReadRdRnRmFpSimd), + new(0x0E809C00, 0xBFE0FC00, InstName.UsdotAdvsimdVec, IsaVersion.v86, InstFlags.RdReadRdRnRmFpSimd), + new(0x2F00A400, 0xBF80FC00, immhImmhConstraints, InstName.UshllAdvsimd, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x7E204400, 0xFF20FC00, ssizeSsizeSsizeConstraints, InstName.UshlAdvsimdS, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x2E204400, 0xBF20FC00, qsizeConstraints, InstName.UshlAdvsimdV, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x7F400400, 0xFFC0FC00, immhConstraints, InstName.UshrAdvsimdS, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x2F000400, 0xBF80FC00, immhQimmhConstraints, InstName.UshrAdvsimdV, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x4E80AC00, 0xFFE0FC00, InstName.UsmmlaAdvsimdVec, IsaVersion.v86, InstFlags.RdRnRmFpSimd), + new(0x7E203800, 0xFF3FFC00, InstName.UsqaddAdvsimdS, IsaVersion.v80, InstFlags.RdReadRdRnQcFpSimd), + new(0x2E203800, 0xBF3FFC00, qsizeConstraints, InstName.UsqaddAdvsimdV, IsaVersion.v80, InstFlags.RdReadRdRnQcFpSimd), + new(0x7F401400, 0xFFC0FC00, immhConstraints, InstName.UsraAdvsimdS, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x2F001400, 0xBF80FC00, immhQimmhConstraints, InstName.UsraAdvsimdV, IsaVersion.v80, InstFlags.RdRnFpSimd), + new(0x2E202000, 0xBF20FC00, sizeConstraints, InstName.UsublAdvsimd, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x2E203000, 0xBF20FC00, sizeConstraints, InstName.UsubwAdvsimd, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x0E001800, 0xBF20FC00, qsizeConstraints, InstName.Uzp1Advsimd, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x0E005800, 0xBF20FC00, qsizeConstraints, InstName.Uzp2Advsimd, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0xD503205F, 0xFFFFFFFF, InstName.Wfe, IsaVersion.v80, InstFlags.None), + new(0xD5031000, 0xFFFFFFE0, InstName.Wfet, IsaVersion.v87, InstFlags.Rd), + new(0xD503207F, 0xFFFFFFFF, InstName.Wfi, IsaVersion.v80, InstFlags.None), + new(0xD5031020, 0xFFFFFFE0, InstName.Wfit, IsaVersion.v87, InstFlags.Rd), + new(0xD500403F, 0xFFFFFFFF, InstName.Xaflag, IsaVersion.v85, InstFlags.C), + new(0xCE800000, 0xFFE00000, InstName.XarAdvsimd, IsaVersion.v82, InstFlags.RdRnRmFpSimd), + new(0xDAC143E0, 0xFFFFFBE0, InstName.XpacGeneral, IsaVersion.v83, InstFlags.Rd), + new(0xD50320FF, 0xFFFFFFFF, InstName.XpacSystem, IsaVersion.v83, InstFlags.None), + new(0x0E212800, 0xBF3FFC00, sizeConstraints, InstName.XtnAdvsimd, IsaVersion.v80, InstFlags.RdReadRdRnFpSimd), + new(0xD503203F, 0xFFFFFFFF, InstName.Yield, IsaVersion.v80, InstFlags.None), + new(0x0E003800, 0xBF20FC00, qsizeConstraints, InstName.Zip1Advsimd, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + new(0x0E007800, 0xBF20FC00, qsizeConstraints, InstName.Zip2Advsimd, IsaVersion.v80, InstFlags.RdRnRmFpSimd), + }; + + _table = new(insts); + } + + public static (InstName, InstFlags, AddressForm) GetInstNameAndFlags(uint encoding, IsaVersion version, IsaFeature features) + { + if (_table.TryFind(encoding, version, features, out InstInfo info)) + { + return (info.Name, info.Flags, info.AddressForm); + } + + return new(InstName.UdfPermUndef, InstFlags.None, AddressForm.None); + } + } +} |