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authorgdkchan <gab.dark.100@gmail.com>2024-08-08 17:07:24 -0300
committerGitHub <noreply@github.com>2024-08-08 17:07:24 -0300
commit8d8983049ea23af0600e077b6389e2cd5de74c38 (patch)
tree660d4ca7f1a562b738b114fcb1fa136766697598 /src/ARMeilleure/Instructions/InstEmitSimdMove32.cs
parent7969fb6bbaf49a7a84df379d072b94286e4f7ada (diff)
Implement UQADD16, UQADD8, UQSUB16, UQSUB8, VQRDMULH, VSLI and VSWP Arm32 instructions (#7174)
Diffstat (limited to 'src/ARMeilleure/Instructions/InstEmitSimdMove32.cs')
-rw-r--r--src/ARMeilleure/Instructions/InstEmitSimdMove32.cs20
1 files changed, 20 insertions, 0 deletions
diff --git a/src/ARMeilleure/Instructions/InstEmitSimdMove32.cs b/src/ARMeilleure/Instructions/InstEmitSimdMove32.cs
index 9fa74099..fb2641f6 100644
--- a/src/ARMeilleure/Instructions/InstEmitSimdMove32.cs
+++ b/src/ARMeilleure/Instructions/InstEmitSimdMove32.cs
@@ -191,6 +191,26 @@ namespace ARMeilleure.Instructions
context.Copy(GetVecA32(op.Qd), res);
}
+ public static void Vswp(ArmEmitterContext context)
+ {
+ OpCode32Simd op = (OpCode32Simd)context.CurrOp;
+
+ if (op.Q)
+ {
+ Operand temp = context.Copy(GetVecA32(op.Qd));
+
+ context.Copy(GetVecA32(op.Qd), GetVecA32(op.Qm));
+ context.Copy(GetVecA32(op.Qm), temp);
+ }
+ else
+ {
+ Operand temp = ExtractScalar(context, OperandType.I64, op.Vd);
+
+ InsertScalar(context, op.Vd, ExtractScalar(context, OperandType.I64, op.Vm));
+ InsertScalar(context, op.Vm, temp);
+ }
+ }
+
public static void Vtbl(ArmEmitterContext context)
{
OpCode32SimdTbl op = (OpCode32SimdTbl)context.CurrOp;