diff options
| author | TSRBerry <20988865+TSRBerry@users.noreply.github.com> | 2023-06-26 07:25:06 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2023-06-26 07:25:06 +0200 |
| commit | ff53dcf5607a82ad38388502b4cf5cc8cca77733 (patch) | |
| tree | eef4e2781d078ca62eee5da4ace8ed3323914c4a /src/ARMeilleure/Decoders | |
| parent | 2de78a2d55a1306761788570ab192897299c55d8 (diff) | |
[ARMeilleure] Address dotnet-format issues (#5357)
* dotnet format style --severity info
Some changes were manually reverted.
* dotnet format analyzers --serverity info
Some changes have been minimally adapted.
* Restore a few unused methods and variables
* Silence dotnet format IDE0060 warnings
* Silence dotnet format IDE0052 warnings
* Address or silence dotnet format IDE1006 warnings
* Address or silence dotnet format CA2208 warnings
* Address dotnet format CA1822 warnings
* Address or silence dotnet format CA1069 warnings
* Silence CA1806 and CA1834 issues
* Address dotnet format CA1401 warnings
* Fix new dotnet-format issues after rebase
* Address review comments
* Address dotnet format CA2208 warnings properly
* Fix formatting for switch expressions
* Address most dotnet format whitespace warnings
* Apply dotnet format whitespace formatting
A few of them have been manually reverted and the corresponding warning was silenced
* Add previously silenced warnings back
I have no clue how these disappeared
* Revert formatting changes for OpCodeTable.cs
* Enable formatting for a few cases again
* Format if-blocks correctly
* Enable formatting for a few more cases again
* Fix inline comment alignment
* Run dotnet format after rebase and remove unused usings
- analyzers
- style
- whitespace
* Disable 'prefer switch expression' rule
* Add comments to disabled warnings
* Remove a few unused parameters
* Adjust namespaces
* Simplify properties and array initialization, Use const when possible, Remove trailing commas
* Start working on disabled warnings
* Fix and silence a few dotnet-format warnings again
* Address IDE0251 warnings
* Address a few disabled IDE0060 warnings
* Silence IDE0060 in .editorconfig
* Revert "Simplify properties and array initialization, Use const when possible, Remove trailing commas"
This reverts commit 9462e4136c0a2100dc28b20cf9542e06790aa67e.
* dotnet format whitespace after rebase
* First dotnet format pass
* Remove unnecessary formatting exclusion
* Add unsafe dotnet format changes
* Change visibility of JitSupportDarwin to internal
Diffstat (limited to 'src/ARMeilleure/Decoders')
122 files changed, 521 insertions, 476 deletions
diff --git a/src/ARMeilleure/Decoders/Block.cs b/src/ARMeilleure/Decoders/Block.cs index f296d299..bb88170d 100644 --- a/src/ARMeilleure/Decoders/Block.cs +++ b/src/ARMeilleure/Decoders/Block.cs @@ -5,10 +5,10 @@ namespace ARMeilleure.Decoders { class Block { - public ulong Address { get; set; } + public ulong Address { get; set; } public ulong EndAddress { get; set; } - public Block Next { get; set; } + public Block Next { get; set; } public Block Branch { get; set; } public bool Exit { get; set; } @@ -43,14 +43,14 @@ namespace ARMeilleure.Decoders rightBlock.EndAddress = EndAddress; - rightBlock.Next = Next; + rightBlock.Next = Next; rightBlock.Branch = Branch; rightBlock.OpCodes.AddRange(OpCodes.GetRange(splitIndex, splitCount)); EndAddress = rightBlock.Address; - Next = rightBlock; + Next = rightBlock; Branch = null; OpCodes.RemoveRange(splitIndex, splitCount); @@ -58,9 +58,9 @@ namespace ARMeilleure.Decoders private static int BinarySearch(List<OpCode> opCodes, ulong address) { - int left = 0; + int left = 0; int middle = 0; - int right = opCodes.Count - 1; + int right = opCodes.Count - 1; while (left <= right) { @@ -92,10 +92,10 @@ namespace ARMeilleure.Decoders { if (OpCodes.Count > 0) { - return OpCodes[OpCodes.Count - 1]; + return OpCodes[^1]; } return null; } } -}
\ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/Condition.cs b/src/ARMeilleure/Decoders/Condition.cs index 727f897d..961825a1 100644 --- a/src/ARMeilleure/Decoders/Condition.cs +++ b/src/ARMeilleure/Decoders/Condition.cs @@ -2,22 +2,22 @@ namespace ARMeilleure.Decoders { enum Condition { - Eq = 0, - Ne = 1, + Eq = 0, + Ne = 1, GeUn = 2, LtUn = 3, - Mi = 4, - Pl = 5, - Vs = 6, - Vc = 7, + Mi = 4, + Pl = 5, + Vs = 6, + Vc = 7, GtUn = 8, LeUn = 9, - Ge = 10, - Lt = 11, - Gt = 12, - Le = 13, - Al = 14, - Nv = 15 + Ge = 10, + Lt = 11, + Gt = 12, + Le = 13, + Al = 14, + Nv = 15, } static class ConditionExtensions @@ -29,4 +29,4 @@ namespace ARMeilleure.Decoders return (Condition)((int)cond ^ 1); } } -}
\ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/DataOp.cs b/src/ARMeilleure/Decoders/DataOp.cs index 464d0089..f99fd5e7 100644 --- a/src/ARMeilleure/Decoders/DataOp.cs +++ b/src/ARMeilleure/Decoders/DataOp.cs @@ -2,9 +2,9 @@ namespace ARMeilleure.Decoders { enum DataOp { - Adr = 0, + Adr = 0, Arithmetic = 1, - Logical = 2, - BitField = 3 + Logical = 2, + BitField = 3, } -}
\ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/Decoder.cs b/src/ARMeilleure/Decoders/Decoder.cs index 426465aa..d8abeb9c 100644 --- a/src/ARMeilleure/Decoders/Decoder.cs +++ b/src/ARMeilleure/Decoders/Decoder.cs @@ -20,11 +20,11 @@ namespace ARMeilleure.Decoders public static Block[] Decode(IMemoryManager memory, ulong address, ExecutionMode mode, bool highCq, DecoderMode dMode) { - List<Block> blocks = new List<Block>(); + List<Block> blocks = new(); - Queue<Block> workQueue = new Queue<Block>(); + Queue<Block> workQueue = new(); - Dictionary<ulong, Block> visited = new Dictionary<ulong, Block>(); + Dictionary<ulong, Block> visited = new(); Debug.Assert(MaxInstsPerFunctionLowCq <= MaxInstsPerFunction); @@ -163,7 +163,7 @@ namespace ARMeilleure.Decoders { index = 0; - int left = 0; + int left = 0; int right = blocks.Count - 1; while (left <= right) @@ -196,9 +196,9 @@ namespace ARMeilleure.Decoders private static void FillBlock( IMemoryManager memory, - ExecutionMode mode, - Block block, - ulong limitAddress) + ExecutionMode mode, + Block block, + ulong limitAddress) { ulong address = block.Address; int itBlockSize = 0; @@ -241,12 +241,12 @@ namespace ARMeilleure.Decoders private static bool IsUnconditionalBranch(OpCode opCode) { return opCode is OpCodeBImmAl || - opCode is OpCodeBReg || IsAarch32UnconditionalBranch(opCode); + opCode is OpCodeBReg || IsAarch32UnconditionalBranch(opCode); } private static bool IsAarch32UnconditionalBranch(OpCode opCode) { - if (!(opCode is OpCode32 op)) + if (opCode is not OpCode32 op) { return false; } @@ -290,9 +290,9 @@ namespace ARMeilleure.Decoders if (opCode is IOpCode32Mem opMem) { - rt = opMem.Rt; - rn = opMem.Rn; - wBack = opMem.WBack; + rt = opMem.Rt; + rn = opMem.Rn; + wBack = opMem.WBack; isLoad = opMem.IsLoad; // For the dual load, we also need to take into account the @@ -306,10 +306,10 @@ namespace ARMeilleure.Decoders { const int pcMask = 1 << RegisterAlias.Aarch32Pc; - rt = (opMemMult.RegisterMask & pcMask) != 0 ? RegisterAlias.Aarch32Pc : 0; - rn = opMemMult.Rn; - wBack = opMemMult.PostOffset != 0; - isLoad = opMemMult.IsLoad; + rt = (opMemMult.RegisterMask & pcMask) != 0 ? RegisterAlias.Aarch32Pc : 0; + rn = opMemMult.Rn; + wBack = opMemMult.PostOffset != 0; + isLoad = opMemMult.IsLoad; } else { @@ -388,4 +388,4 @@ namespace ARMeilleure.Decoders } } } -}
\ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/DecoderHelper.cs b/src/ARMeilleure/Decoders/DecoderHelper.cs index 5227e6a1..35e57395 100644 --- a/src/ARMeilleure/Decoders/DecoderHelper.cs +++ b/src/ARMeilleure/Decoders/DecoderHelper.cs @@ -10,7 +10,7 @@ namespace ARMeilleure.Decoders Imm8ToFP64Table = BuildImm8ToFP64Table(); } - public static readonly uint[] Imm8ToFP32Table; + public static readonly uint[] Imm8ToFP32Table; public static readonly ulong[] Imm8ToFP64Table; private static uint[] BuildImm8ToFP32Table() @@ -40,47 +40,47 @@ namespace ARMeilleure.Decoders // abcdefgh -> aBbbbbbc defgh000 00000000 00000000 (B = ~b) private static uint ExpandImm8ToFP32(uint imm) { - uint MoveBit(uint bits, int from, int to) + static uint MoveBit(uint bits, int from, int to) { return ((bits >> from) & 1U) << to; } return MoveBit(imm, 7, 31) | MoveBit(~imm, 6, 30) | - MoveBit(imm, 6, 29) | MoveBit( imm, 6, 28) | - MoveBit(imm, 6, 27) | MoveBit( imm, 6, 26) | - MoveBit(imm, 6, 25) | MoveBit( imm, 5, 24) | - MoveBit(imm, 4, 23) | MoveBit( imm, 3, 22) | - MoveBit(imm, 2, 21) | MoveBit( imm, 1, 20) | + MoveBit(imm, 6, 29) | MoveBit(imm, 6, 28) | + MoveBit(imm, 6, 27) | MoveBit(imm, 6, 26) | + MoveBit(imm, 6, 25) | MoveBit(imm, 5, 24) | + MoveBit(imm, 4, 23) | MoveBit(imm, 3, 22) | + MoveBit(imm, 2, 21) | MoveBit(imm, 1, 20) | MoveBit(imm, 0, 19); } // abcdefgh -> aBbbbbbb bbcdefgh 00000000 00000000 00000000 00000000 00000000 00000000 (B = ~b) private static ulong ExpandImm8ToFP64(ulong imm) { - ulong MoveBit(ulong bits, int from, int to) + static ulong MoveBit(ulong bits, int from, int to) { return ((bits >> from) & 1UL) << to; } return MoveBit(imm, 7, 63) | MoveBit(~imm, 6, 62) | - MoveBit(imm, 6, 61) | MoveBit( imm, 6, 60) | - MoveBit(imm, 6, 59) | MoveBit( imm, 6, 58) | - MoveBit(imm, 6, 57) | MoveBit( imm, 6, 56) | - MoveBit(imm, 6, 55) | MoveBit( imm, 6, 54) | - MoveBit(imm, 5, 53) | MoveBit( imm, 4, 52) | - MoveBit(imm, 3, 51) | MoveBit( imm, 2, 50) | - MoveBit(imm, 1, 49) | MoveBit( imm, 0, 48); + MoveBit(imm, 6, 61) | MoveBit(imm, 6, 60) | + MoveBit(imm, 6, 59) | MoveBit(imm, 6, 58) | + MoveBit(imm, 6, 57) | MoveBit(imm, 6, 56) | + MoveBit(imm, 6, 55) | MoveBit(imm, 6, 54) | + MoveBit(imm, 5, 53) | MoveBit(imm, 4, 52) | + MoveBit(imm, 3, 51) | MoveBit(imm, 2, 50) | + MoveBit(imm, 1, 49) | MoveBit(imm, 0, 48); } public struct BitMask { public long WMask; public long TMask; - public int Pos; - public int Shift; + public int Pos; + public int Shift; public bool IsUndefined; - public static BitMask Invalid => new BitMask { IsUndefined = true }; + public static BitMask Invalid => new() { IsUndefined = true }; } public static BitMask DecodeBitMask(int opCode, bool immediate) @@ -88,7 +88,7 @@ namespace ARMeilleure.Decoders int immS = (opCode >> 10) & 0x3f; int immR = (opCode >> 16) & 0x3f; - int n = (opCode >> 22) & 1; + int n = (opCode >> 22) & 1; int sf = (opCode >> 31) & 1; int length = BitUtils.HighestBitSet((~immS & 0x3f) | (n << 6)); @@ -115,7 +115,7 @@ namespace ARMeilleure.Decoders if (r > 0) { - wMask = BitUtils.RotateRight(wMask, r, size); + wMask = BitUtils.RotateRight(wMask, r, size); wMask &= BitUtils.FillWithOnes(size); } @@ -124,8 +124,8 @@ namespace ARMeilleure.Decoders WMask = BitUtils.Replicate(wMask, size), TMask = BitUtils.Replicate(tMask, size), - Pos = immS, - Shift = immR + Pos = immS, + Shift = immR, }; } @@ -164,4 +164,4 @@ namespace ARMeilleure.Decoders return false; } } -}
\ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/DecoderMode.cs b/src/ARMeilleure/Decoders/DecoderMode.cs index 55362084..280ebb64 100644 --- a/src/ARMeilleure/Decoders/DecoderMode.cs +++ b/src/ARMeilleure/Decoders/DecoderMode.cs @@ -6,4 +6,4 @@ SingleBlock, SingleInstruction, } -}
\ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/IOpCode.cs b/src/ARMeilleure/Decoders/IOpCode.cs index 37ba7a4c..9d5e3bf7 100644 --- a/src/ARMeilleure/Decoders/IOpCode.cs +++ b/src/ARMeilleure/Decoders/IOpCode.cs @@ -14,4 +14,4 @@ namespace ARMeilleure.Decoders OperandType GetOperandType(); } -}
\ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/IOpCode32.cs b/src/ARMeilleure/Decoders/IOpCode32.cs index 126c1069..578925de 100644 --- a/src/ARMeilleure/Decoders/IOpCode32.cs +++ b/src/ARMeilleure/Decoders/IOpCode32.cs @@ -6,4 +6,4 @@ namespace ARMeilleure.Decoders uint GetPc(); } -}
\ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/IOpCode32Alu.cs b/src/ARMeilleure/Decoders/IOpCode32Alu.cs index 69fee164..a85ef44a 100644 --- a/src/ARMeilleure/Decoders/IOpCode32Alu.cs +++ b/src/ARMeilleure/Decoders/IOpCode32Alu.cs @@ -5,4 +5,4 @@ namespace ARMeilleure.Decoders int Rd { get; } int Rn { get; } } -}
\ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/IOpCode32AluImm.cs b/src/ARMeilleure/Decoders/IOpCode32AluImm.cs index 342fb8f6..9d49a440 100644 --- a/src/ARMeilleure/Decoders/IOpCode32AluImm.cs +++ b/src/ARMeilleure/Decoders/IOpCode32AluImm.cs @@ -6,4 +6,4 @@ bool IsRotated { get; } } -}
\ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/IOpCode32AluImm16.cs b/src/ARMeilleure/Decoders/IOpCode32AluImm16.cs index cd128f65..dd42a70b 100644 --- a/src/ARMeilleure/Decoders/IOpCode32AluImm16.cs +++ b/src/ARMeilleure/Decoders/IOpCode32AluImm16.cs @@ -4,4 +4,4 @@ namespace ARMeilleure.Decoders { int Immediate { get; } } -}
\ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/IOpCode32AluRsImm.cs b/src/ARMeilleure/Decoders/IOpCode32AluRsImm.cs index e899a659..8b976b58 100644 --- a/src/ARMeilleure/Decoders/IOpCode32AluRsImm.cs +++ b/src/ARMeilleure/Decoders/IOpCode32AluRsImm.cs @@ -7,4 +7,4 @@ ShiftType ShiftType { get; } } -}
\ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/IOpCode32AluRsReg.cs b/src/ARMeilleure/Decoders/IOpCode32AluRsReg.cs index 879db059..e8c33c2b 100644 --- a/src/ARMeilleure/Decoders/IOpCode32AluRsReg.cs +++ b/src/ARMeilleure/Decoders/IOpCode32AluRsReg.cs @@ -7,4 +7,4 @@ ShiftType ShiftType { get; } } -}
\ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/IOpCode32BImm.cs b/src/ARMeilleure/Decoders/IOpCode32BImm.cs index ec7db2c2..8d22d5c4 100644 --- a/src/ARMeilleure/Decoders/IOpCode32BImm.cs +++ b/src/ARMeilleure/Decoders/IOpCode32BImm.cs @@ -1,4 +1,4 @@ namespace ARMeilleure.Decoders { interface IOpCode32BImm : IOpCode32, IOpCodeBImm { } -}
\ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/IOpCode32BReg.cs b/src/ARMeilleure/Decoders/IOpCode32BReg.cs index 097ab427..9badc985 100644 --- a/src/ARMeilleure/Decoders/IOpCode32BReg.cs +++ b/src/ARMeilleure/Decoders/IOpCode32BReg.cs @@ -4,4 +4,4 @@ namespace ARMeilleure.Decoders { int Rm { get; } } -}
\ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/IOpCode32Exception.cs b/src/ARMeilleure/Decoders/IOpCode32Exception.cs index 8f0fb81a..4c1fc231 100644 --- a/src/ARMeilleure/Decoders/IOpCode32Exception.cs +++ b/src/ARMeilleure/Decoders/IOpCode32Exception.cs @@ -4,4 +4,4 @@ { int Id { get; } } -}
\ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/IOpCode32HasSetFlags.cs b/src/ARMeilleure/Decoders/IOpCode32HasSetFlags.cs index 71ca6d19..772e1080 100644 --- a/src/ARMeilleure/Decoders/IOpCode32HasSetFlags.cs +++ b/src/ARMeilleure/Decoders/IOpCode32HasSetFlags.cs @@ -4,4 +4,4 @@ { bool? SetFlags { get; } } -}
\ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/IOpCode32Mem.cs b/src/ARMeilleure/Decoders/IOpCode32Mem.cs index 6664ddff..a34bc0e2 100644 --- a/src/ARMeilleure/Decoders/IOpCode32Mem.cs +++ b/src/ARMeilleure/Decoders/IOpCode32Mem.cs @@ -13,4 +13,4 @@ namespace ARMeilleure.Decoders int Immediate { get; } } -}
\ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/IOpCode32MemMult.cs b/src/ARMeilleure/Decoders/IOpCode32MemMult.cs index 4b891bc1..0c5e48f2 100644 --- a/src/ARMeilleure/Decoders/IOpCode32MemMult.cs +++ b/src/ARMeilleure/Decoders/IOpCode32MemMult.cs @@ -12,4 +12,4 @@ namespace ARMeilleure.Decoders int Offset { get; } } -}
\ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/IOpCode32MemReg.cs b/src/ARMeilleure/Decoders/IOpCode32MemReg.cs index 7fe1b022..f356e4d7 100644 --- a/src/ARMeilleure/Decoders/IOpCode32MemReg.cs +++ b/src/ARMeilleure/Decoders/IOpCode32MemReg.cs @@ -4,4 +4,4 @@ { int Rm { get; } } -}
\ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/IOpCode32MemRsImm.cs b/src/ARMeilleure/Decoders/IOpCode32MemRsImm.cs index 65b7ee0b..3407e98a 100644 --- a/src/ARMeilleure/Decoders/IOpCode32MemRsImm.cs +++ b/src/ARMeilleure/Decoders/IOpCode32MemRsImm.cs @@ -5,4 +5,4 @@ namespace ARMeilleure.Decoders int Rm { get; } ShiftType ShiftType { get; } } -}
\ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/IOpCodeAlu.cs b/src/ARMeilleure/Decoders/IOpCodeAlu.cs index b8c28513..059769ba 100644 --- a/src/ARMeilleure/Decoders/IOpCodeAlu.cs +++ b/src/ARMeilleure/Decoders/IOpCodeAlu.cs @@ -7,4 +7,4 @@ namespace ARMeilleure.Decoders DataOp DataOp { get; } } -}
\ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/IOpCodeAluImm.cs b/src/ARMeilleure/Decoders/IOpCodeAluImm.cs index 02f4c997..40a69cc9 100644 --- a/src/ARMeilleure/Decoders/IOpCodeAluImm.cs +++ b/src/ARMeilleure/Decoders/IOpCodeAluImm.cs @@ -4,4 +4,4 @@ namespace ARMeilleure.Decoders { long Immediate { get; } } -}
\ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/IOpCodeAluRs.cs b/src/ARMeilleure/Decoders/IOpCodeAluRs.cs index 22540b11..eec95698 100644 --- a/src/ARMeilleure/Decoders/IOpCodeAluRs.cs +++ b/src/ARMeilleure/Decoders/IOpCodeAluRs.cs @@ -3,8 +3,8 @@ namespace ARMeilleure.Decoders interface IOpCodeAluRs : IOpCodeAlu { int Shift { get; } - int Rm { get; } + int Rm { get; } ShiftType ShiftType { get; } } -}
\ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/IOpCodeAluRx.cs b/src/ARMeilleure/Decoders/IOpCodeAluRx.cs index 9d16be78..e5a8559d 100644 --- a/src/ARMeilleure/Decoders/IOpCodeAluRx.cs +++ b/src/ARMeilleure/Decoders/IOpCodeAluRx.cs @@ -3,8 +3,8 @@ namespace ARMeilleure.Decoders interface IOpCodeAluRx : IOpCodeAlu { int Shift { get; } - int Rm { get; } + int Rm { get; } IntType IntType { get; } } -}
\ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/IOpCodeBImm.cs b/src/ARMeilleure/Decoders/IOpCodeBImm.cs index 958bff28..9ce7512a 100644 --- a/src/ARMeilleure/Decoders/IOpCodeBImm.cs +++ b/src/ARMeilleure/Decoders/IOpCodeBImm.cs @@ -4,4 +4,4 @@ namespace ARMeilleure.Decoders { long Immediate { get; } } -}
\ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/IOpCodeCond.cs b/src/ARMeilleure/Decoders/IOpCodeCond.cs index 9808f7c0..6604f19a 100644 --- a/src/ARMeilleure/Decoders/IOpCodeCond.cs +++ b/src/ARMeilleure/Decoders/IOpCodeCond.cs @@ -4,4 +4,4 @@ namespace ARMeilleure.Decoders { Condition Cond { get; } } -}
\ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/IOpCodeLit.cs b/src/ARMeilleure/Decoders/IOpCodeLit.cs index 74084a45..434e4da8 100644 --- a/src/ARMeilleure/Decoders/IOpCodeLit.cs +++ b/src/ARMeilleure/Decoders/IOpCodeLit.cs @@ -2,10 +2,10 @@ namespace ARMeilleure.Decoders { interface IOpCodeLit : IOpCode { - int Rt { get; } + int Rt { get; } long Immediate { get; } - int Size { get; } - bool Signed { get; } - bool Prefetch { get; } + int Size { get; } + bool Signed { get; } + bool Prefetch { get; } } -}
\ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/IOpCodeSimd.cs b/src/ARMeilleure/Decoders/IOpCodeSimd.cs index 056ef045..598d9d7f 100644 --- a/src/ARMeilleure/Decoders/IOpCodeSimd.cs +++ b/src/ARMeilleure/Decoders/IOpCodeSimd.cs @@ -4,4 +4,4 @@ namespace ARMeilleure.Decoders { int Size { get; } } -}
\ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/InstDescriptor.cs b/src/ARMeilleure/Decoders/InstDescriptor.cs index 577ff394..c35c754a 100644 --- a/src/ARMeilleure/Decoders/InstDescriptor.cs +++ b/src/ARMeilleure/Decoders/InstDescriptor.cs @@ -4,15 +4,15 @@ namespace ARMeilleure.Decoders { readonly struct InstDescriptor { - public static InstDescriptor Undefined => new InstDescriptor(InstName.Und, InstEmit.Und); + public static InstDescriptor Undefined => new(InstName.Und, InstEmit.Und); - public InstName Name { get; } + public InstName Name { get; } public InstEmitter Emitter { get; } public InstDescriptor(InstName name, InstEmitter emitter) { - Name = name; + Name = name; Emitter = emitter; } } -}
\ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/InstEmitter.cs b/src/ARMeilleure/Decoders/InstEmitter.cs index a8b52656..43bfcdca 100644 --- a/src/ARMeilleure/Decoders/InstEmitter.cs +++ b/src/ARMeilleure/Decoders/InstEmitter.cs @@ -3,4 +3,4 @@ using ARMeilleure.Translation; namespace ARMeilleure.Decoders { delegate void InstEmitter(ArmEmitterContext context); -}
\ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/IntType.cs b/src/ARMeilleure/Decoders/IntType.cs index 244e9680..937a569a 100644 --- a/src/ARMeilleure/Decoders/IntType.cs +++ b/src/ARMeilleure/Decoders/IntType.cs @@ -2,13 +2,13 @@ namespace ARMeilleure.Decoders { enum IntType { - UInt8 = 0, + UInt8 = 0, UInt16 = 1, UInt32 = 2, UInt64 = 3, - Int8 = 4, - Int16 = 5, - Int32 = 6, - Int64 = 7 + Int8 = 4, + Int16 = 5, + Int32 = 6, + Int64 = 7, } -}
\ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCode.cs b/src/ARMeilleure/Decoders/OpCode.cs index f9aed792..c8123308 100644 --- a/src/ARMeilleure/Decoders/OpCode.cs +++ b/src/ARMeilleure/Decoders/OpCode.cs @@ -5,8 +5,8 @@ namespace ARMeilleure.Decoders { class OpCode : IOpCode { - public ulong Address { get; } - public int RawOpCode { get; } + public ulong Address { get; } + public int RawOpCode { get; } public int OpCodeSizeInBytes { get; protected set; } = 4; @@ -14,13 +14,13 @@ namespace ARMeilleure.Decoders public RegisterSize RegisterSize { get; protected set; } - public static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode(inst, address, opCode); + public static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new(inst, address, opCode); public OpCode(InstDescriptor inst, ulong address, int opCode) { Instruction = inst; - Address = address; - RawOpCode = opCode; + Address = address; + RawOpCode = opCode; RegisterSize = RegisterSize.Int64; } @@ -30,15 +30,14 @@ namespace ARMeilleure.Decoders public int GetBitsCount() { - switch (RegisterSize) + return RegisterSize switch { - case RegisterSize.Int32: return 32; - case RegisterSize.Int64: return 64; - case RegisterSize.Simd64: return 64; - case RegisterSize.Simd128: return 128; - } - - throw new InvalidOperationException(); + RegisterSize.Int32 => 32, + RegisterSize.Int64 => 64, + RegisterSize.Simd64 => 64, + RegisterSize.Simd128 => 128, + _ => throw new InvalidOperationException(), + }; } public OperandType GetOperandType() @@ -46,4 +45,4 @@ namespace ARMeilleure.Decoders return RegisterSize == RegisterSize.Int32 ? OperandType.I32 : OperandType.I64; } } -}
\ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCode32.cs b/src/ARMeilleure/Decoders/OpCode32.cs index c2f14145..a2be01e9 100644 --- a/src/ARMeilleure/Decoders/OpCode32.cs +++ b/src/ARMeilleure/Decoders/OpCode32.cs @@ -31,4 +31,4 @@ namespace ARMeilleure.Decoders } } } -}
\ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCode32Alu.cs b/src/ARMeilleure/Decoders/OpCode32Alu.cs index 1625aee0..8634f5ce 100644 --- a/src/ARMeilleure/Decoders/OpCode32Alu.cs +++ b/src/ARMeilleure/Decoders/OpCode32Alu.cs @@ -17,4 +17,4 @@ namespace ARMeilleure.Decoders SetFlags = ((opCode >> 20) & 1) != 0; } } -}
\ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCode32AluImm.cs b/src/ARMeilleure/Decoders/OpCode32AluImm.cs index b5435aaf..c8b05e6b 100644 --- a/src/ARMeilleure/Decoders/OpCode32AluImm.cs +++ b/src/ARMeilleure/Decoders/OpCode32AluImm.cs @@ -20,4 +20,4 @@ namespace ARMeilleure.Decoders IsRotated = shift != 0; } } -}
\ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCode32AluRsImm.cs b/src/ARMeilleure/Decoders/OpCode32AluRsImm.cs index c2dee6c9..4b2c5897 100644 --- a/src/ARMeilleure/Decoders/OpCode32AluRsImm.cs +++ b/src/ARMeilleure/Decoders/OpCode32AluRsImm.cs @@ -2,7 +2,7 @@ namespace ARMeilleure.Decoders { class OpCode32AluRsImm : OpCode32Alu, IOpCode32AluRsImm { - public int Rm { get; } + public int Rm { get; } public int Immediate { get; } public ShiftType ShiftType { get; } @@ -11,10 +11,10 @@ namespace ARMeilleure.Decoders public OpCode32AluRsImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { - Rm = (opCode >> 0) & 0xf; + Rm = (opCode >> 0) & 0xf; Immediate = (opCode >> 7) & 0x1f; ShiftType = (ShiftType)((opCode >> 5) & 3); } } -}
\ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCode32BImm.cs b/src/ARMeilleure/Decoders/OpCode32BImm.cs index f2959b33..e7f5d6db 100644 --- a/src/ARMeilleure/Decoders/OpCode32BImm.cs +++ b/src/ARMeilleure/Decoders/OpCode32BImm.cs @@ -26,4 +26,4 @@ namespace ARMeilleure.Decoders } } } -}
\ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCode32BReg.cs b/src/ARMeilleure/Decoders/OpCode32BReg.cs index d4f5f760..8939c0de 100644 --- a/src/ARMeilleure/Decoders/OpCode32BReg.cs +++ b/src/ARMeilleure/Decoders/OpCode32BReg.cs @@ -11,4 +11,4 @@ namespace ARMeilleure.Decoders Rm = opCode & 0xf; } } -}
\ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCode32Mem.cs b/src/ARMeilleure/Decoders/OpCode32Mem.cs index ceb1e49f..8a242199 100644 --- a/src/ARMeilleure/Decoders/OpCode32Mem.cs +++ b/src/ARMeilleure/Decoders/OpCode32Mem.cs @@ -9,9 +9,9 @@ namespace ARMeilleure.Decoders public int Immediate { get; protected set; } - public bool Index { get; } - public bool Add { get; } - public bool WBack { get; } + public bool Index { get; } + public bool Add { get; } + public bool WBack { get; } public bool Unprivileged { get; } public bool IsLoad { get; } @@ -24,16 +24,16 @@ namespace ARMeilleure.Decoders Rn = (opCode >> 16) & 0xf; bool isLoad = (opCode & (1 << 20)) != 0; - bool w = (opCode & (1 << 21)) != 0; - bool u = (opCode & (1 << 23)) != 0; - bool p = (opCode & (1 << 24)) != 0; + bool w = (opCode & (1 << 21)) != 0; + bool u = (opCode & (1 << 23)) != 0; + bool p = (opCode & (1 << 24)) != 0; - Index = p; - Add = u; - WBack = !p || w; + Index = p; + Add = u; + WBack = !p || w; Unprivileged = !p && w; IsLoad = isLoad || inst.Name == InstName.Ldrd; } } -}
\ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCode32MemImm.cs b/src/ARMeilleure/Decoders/OpCode32MemImm.cs index 3af4b6f7..fa10e04e 100644 --- a/src/ARMeilleure/Decoders/OpCode32MemImm.cs +++ b/src/ARMeilleure/Decoders/OpCode32MemImm.cs @@ -9,4 +9,4 @@ namespace ARMeilleure.Decoders Immediate = opCode & 0xfff; } } -}
\ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCode32MemImm8.cs b/src/ARMeilleure/Decoders/OpCode32MemImm8.cs index 1b8a57de..248ee8e6 100644 --- a/src/ARMeilleure/Decoders/OpCode32MemImm8.cs +++ b/src/ARMeilleure/Decoders/OpCode32MemImm8.cs @@ -12,4 +12,4 @@ namespace ARMeilleure.Decoders Immediate = imm4L | (imm4H << 4); } } -}
\ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCode32MemMult.cs b/src/ARMeilleure/Decoders/OpCode32MemMult.cs index 522b96bb..6e39e347 100644 --- a/src/ARMeilleure/Decoders/OpCode32MemMult.cs +++ b/src/ARMeilleure/Decoders/OpCode32MemMult.cs @@ -7,8 +7,8 @@ namespace ARMeilleure.Decoders public int Rn { get; } public int RegisterMask { get; } - public int Offset { get; } - public int PostOffset { get; } + public int Offset { get; } + public int PostOffset { get; } public bool IsLoad { get; } @@ -19,9 +19,9 @@ namespace ARMeilleure.Decoders Rn = (opCode >> 16) & 0xf; bool isLoad = (opCode & (1 << 20)) != 0; - bool w = (opCode & (1 << 21)) != 0; - bool u = (opCode & (1 << 23)) != 0; - bool p = (opCode & (1 << 24)) != 0; + bool w = (opCode & (1 << 21)) != 0; + bool u = (opCode & (1 << 23)) != 0; + bool p = (opCode & (1 << 24)) != 0; RegisterMask = opCode & 0xffff; @@ -49,4 +49,4 @@ namespace ARMeilleure.Decoders IsLoad = isLoad; } } -}
\ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCode32Mrs.cs b/src/ARMeilleure/Decoders/OpCode32Mrs.cs index c34a8b99..b681b54c 100644 --- a/src/ARMeilleure/Decoders/OpCode32Mrs.cs +++ b/src/ARMeilleure/Decoders/OpCode32Mrs.cs @@ -2,8 +2,8 @@ namespace ARMeilleure.Decoders { class OpCode32Mrs : OpCode32 { - public bool R { get; } - public int Rd { get; } + public bool R { get; } + public int Rd { get; } public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32Mrs(inst, address, opCode); diff --git a/src/ARMeilleure/Decoders/OpCode32MsrReg.cs b/src/ARMeilleure/Decoders/OpCode32MsrReg.cs index d897ffd8..7186ebf7 100644 --- a/src/ARMeilleure/Decoders/OpCode32MsrReg.cs +++ b/src/ARMeilleure/Decoders/OpCode32MsrReg.cs @@ -4,11 +4,11 @@ namespace ARMeilleure.Decoders { class OpCode32MsrReg : OpCode32 { - public bool R { get; } - public int Mask { get; } - public int Rd { get; } + public bool R { get; } + public int Mask { get; } + public int Rd { get; } public bool Banked { get; } - public int Rn { get; } + public int Rn { get; } public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCode32MsrReg(inst, address, opCode); diff --git a/src/ARMeilleure/Decoders/OpCode32Sat.cs b/src/ARMeilleure/Decoders/OpCode32Sat.cs index 621def27..35c5cf47 100644 --- a/src/ARMeilleure/Decoders/OpCode32Sat.cs +++ b/src/ARMeilleure/Decoders/OpCode32Sat.cs @@ -21,4 +21,4 @@ namespace ARMeilleure.Decoders ShiftType = (ShiftType)((opCode >> 5) & 2); } } -}
\ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCode32Sat16.cs b/src/ARMeilleure/Decoders/OpCode32Sat16.cs index 51061b07..01f4d3b2 100644 --- a/src/ARMeilleure/Decoders/OpCode32Sat16.cs +++ b/src/ARMeilleure/Decoders/OpCode32Sat16.cs @@ -15,4 +15,4 @@ namespace ARMeilleure.Decoders SatImm = (opCode >> 16) & 0xf; } } -}
\ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCode32SimdBase.cs b/src/ARMeilleure/Decoders/OpCode32SimdBase.cs index 4382fc2a..2361ac1e 100644 --- a/src/ARMeilleure/Decoders/OpCode32SimdBase.cs +++ b/src/ARMeilleure/Decoders/OpCode32SimdBase.cs @@ -24,27 +24,21 @@ namespace ARMeilleure.Decoders protected int GetQuadwordIndex(int index) { - switch (RegisterSize) + return RegisterSize switch { - case RegisterSize.Simd128: - case RegisterSize.Simd64: - return index >> 1; - } - - throw new InvalidOperationException(); + RegisterSize.Simd128 or RegisterSize.Simd64 => index >> 1, + _ => throw new InvalidOperationException(), + }; } protected int GetQuadwordSubindex(int index) { - switch (RegisterSize) + return RegisterSize switch { - case RegisterSize.Simd128: - return 0; - case RegisterSize.Simd64: - return index & 1; - } - - throw new InvalidOperationException(); + RegisterSize.Simd128 => 0, + RegisterSize.Simd64 => index & 1, + _ => throw new InvalidOperationException(), + }; } protected OpCode32SimdBase(InstDescriptor inst, ulong address, int opCode, bool isThumb) : base(inst, address, opCode) diff --git a/src/ARMeilleure/Decoders/OpCode32SimdCvtTB.cs b/src/ARMeilleure/Decoders/OpCode32SimdCvtTB.cs index a95b32ab..d3beb4bf 100644 --- a/src/ARMeilleure/Decoders/OpCode32SimdCvtTB.cs +++ b/src/ARMeilleure/Decoders/OpCode32SimdCvtTB.cs @@ -15,8 +15,8 @@ namespace ARMeilleure.Decoders { IsThumb = isThumb; - Op = ((opCode >> 16) & 0x1) != 0; - T = ((opCode >> 7) & 0x1) != 0; + Op = ((opCode >> 16) & 0x1) != 0; + T = ((opCode >> 7) & 0x1) != 0; Size = ((opCode >> 8) & 0x1); RegisterSize = Size == 1 ? RegisterSize.Int64 : RegisterSize.Int32; @@ -41,4 +41,4 @@ namespace ARMeilleure.Decoders } } } -}
\ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCode32SimdLong.cs b/src/ARMeilleure/Decoders/OpCode32SimdLong.cs index 8d64d673..558771a3 100644 --- a/src/ARMeilleure/Decoders/OpCode32SimdLong.cs +++ b/src/ARMeilleure/Decoders/OpCode32SimdLong.cs @@ -14,9 +14,15 @@ // The value must be a power of 2, otherwise it is the encoding of another instruction. switch (imm3h) { - case 1: Size = 0; break; - case 2: Size = 1; break; - case 4: Size = 2; break; + case 1: + Size = 0; + break; + case 2: + Size = 1; + break; + case 4: + Size = 2; + break; } U = ((opCode >> (isThumb ? 28 : 24)) & 0x1) != 0; diff --git a/src/ARMeilleure/Decoders/OpCode32SimdMemPair.cs b/src/ARMeilleure/Decoders/OpCode32SimdMemPair.cs index da88eed2..325be4ec 100644 --- a/src/ARMeilleure/Decoders/OpCode32SimdMemPair.cs +++ b/src/ARMeilleure/Decoders/OpCode32SimdMemPair.cs @@ -4,12 +4,12 @@ namespace ARMeilleure.Decoders { class OpCode32SimdMemPair : OpCode32, IOpCode32Simd { - private static int[] _regsMap = + private static readonly int[] _regsMap = { 1, 1, 4, 2, 1, 1, 3, 1, 1, 1, 2, 1, - 1, 1, 1, 1 + 1, 1, 1, 1, }; public int Vd { get; } diff --git a/src/ARMeilleure/Decoders/OpCode32SimdSel.cs b/src/ARMeilleure/Decoders/OpCode32SimdSel.cs index bd4865ea..cb28418c 100644 --- a/src/ARMeilleure/Decoders/OpCode32SimdSel.cs +++ b/src/ARMeilleure/Decoders/OpCode32SimdSel.cs @@ -18,6 +18,6 @@ Eq = 0, Vs, Ge, - Gt + Gt, } } diff --git a/src/ARMeilleure/Decoders/OpCodeAdr.cs b/src/ARMeilleure/Decoders/OpCodeAdr.cs index 9655c766..08028040 100644 --- a/src/ARMeilleure/Decoders/OpCodeAdr.cs +++ b/src/ARMeilleure/Decoders/OpCodeAdr.cs @@ -6,14 +6,14 @@ namespace ARMeilleure.Decoders public long Immediate { get; } - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeAdr(inst, address, opCode); + public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeAdr(inst, address, opCode); public OpCodeAdr(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Rd = opCode & 0x1f; - Immediate = DecoderHelper.DecodeImmS19_2(opCode); + Immediate = DecoderHelper.DecodeImmS19_2(opCode); Immediate |= ((long)opCode >> 29) & 3; } } -}
\ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeAlu.cs b/src/ARMeilleure/Decoders/OpCodeAlu.cs index 4d7f03a7..1619ecd8 100644 --- a/src/ARMeilleure/Decoders/OpCodeAlu.cs +++ b/src/ARMeilleure/Decoders/OpCodeAlu.cs @@ -11,8 +11,8 @@ namespace ARMeilleure.Decoders public OpCodeAlu(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { - Rd = (opCode >> 0) & 0x1f; - Rn = (opCode >> 5) & 0x1f; + Rd = (opCode >> 0) & 0x1f; + Rn = (opCode >> 5) & 0x1f; DataOp = (DataOp)((opCode >> 24) & 0x3); RegisterSize = (opCode >> 31) != 0 @@ -20,4 +20,4 @@ namespace ARMeilleure.Decoders : RegisterSize.Int32; } } -}
\ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeAluBinary.cs b/src/ARMeilleure/Decoders/OpCodeAluBinary.cs index e8b10656..4413581c 100644 --- a/src/ARMeilleure/Decoders/OpCodeAluBinary.cs +++ b/src/ARMeilleure/Decoders/OpCodeAluBinary.cs @@ -11,4 +11,4 @@ namespace ARMeilleure.Decoders Rm = (opCode >> 16) & 0x1f; } } -}
\ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeAluImm.cs b/src/ARMeilleure/Decoders/OpCodeAluImm.cs index 91aa9553..0d2f7202 100644 --- a/src/ARMeilleure/Decoders/OpCodeAluImm.cs +++ b/src/ARMeilleure/Decoders/OpCodeAluImm.cs @@ -33,8 +33,8 @@ namespace ARMeilleure.Decoders } else { - throw new ArgumentException(nameof(opCode)); + throw new ArgumentException($"Invalid data operation: {DataOp}", nameof(opCode)); } } } -}
\ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeAluRs.cs b/src/ARMeilleure/Decoders/OpCodeAluRs.cs index 94983336..47a47e7d 100644 --- a/src/ARMeilleure/Decoders/OpCodeAluRs.cs +++ b/src/ARMeilleure/Decoders/OpCodeAluRs.cs @@ -3,7 +3,7 @@ namespace ARMeilleure.Decoders class OpCodeAluRs : OpCodeAlu, IOpCodeAluRs { public int Shift { get; } - public int Rm { get; } + public int Rm { get; } public ShiftType ShiftType { get; } @@ -22,8 +22,8 @@ namespace ARMeilleure.Decoders Shift = shift; - Rm = (opCode >> 16) & 0x1f; + Rm = (opCode >> 16) & 0x1f; ShiftType = (ShiftType)((opCode >> 22) & 0x3); } } -}
\ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeAluRx.cs b/src/ARMeilleure/Decoders/OpCodeAluRx.cs index d39da9e7..c2148678 100644 --- a/src/ARMeilleure/Decoders/OpCodeAluRx.cs +++ b/src/ARMeilleure/Decoders/OpCodeAluRx.cs @@ -3,7 +3,7 @@ namespace ARMeilleure.Decoders class OpCodeAluRx : OpCodeAlu, IOpCodeAluRx { public int Shift { get; } - public int Rm { get; } + public int Rm { get; } public IntType IntType { get; } @@ -11,9 +11,9 @@ namespace ARMeilleure.Decoders public OpCodeAluRx(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { - Shift = (opCode >> 10) & 0x7; + Shift = (opCode >> 10) & 0x7; IntType = (IntType)((opCode >> 13) & 0x7); - Rm = (opCode >> 16) & 0x1f; + Rm = (opCode >> 16) & 0x1f; } } -}
\ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeBImm.cs b/src/ARMeilleure/Decoders/OpCodeBImm.cs index e302516e..2848c140 100644 --- a/src/ARMeilleure/Decoders/OpCodeBImm.cs +++ b/src/ARMeilleure/Decoders/OpCodeBImm.cs @@ -8,4 +8,4 @@ namespace ARMeilleure.Decoders public OpCodeBImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { } } -}
\ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeBImmAl.cs b/src/ARMeilleure/Decoders/OpCodeBImmAl.cs index 47ae5f56..6c4b28c6 100644 --- a/src/ARMeilleure/Decoders/OpCodeBImmAl.cs +++ b/src/ARMeilleure/Decoders/OpCodeBImmAl.cs @@ -9,4 +9,4 @@ namespace ARMeilleure.Decoders Immediate = (long)address + DecoderHelper.DecodeImm26_2(opCode); } } -}
\ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeBImmCmp.cs b/src/ARMeilleure/Decoders/OpCodeBImmCmp.cs index a5246569..c477ddec 100644 --- a/src/ARMeilleure/Decoders/OpCodeBImmCmp.cs +++ b/src/ARMeilleure/Decoders/OpCodeBImmCmp.cs @@ -17,4 +17,4 @@ namespace ARMeilleure.Decoders : RegisterSize.Int32; } } -}
\ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeBImmCond.cs b/src/ARMeilleure/Decoders/OpCodeBImmCond.cs index b57a7ea8..7a51a072 100644 --- a/src/ARMeilleure/Decoders/OpCodeBImmCond.cs +++ b/src/ARMeilleure/Decoders/OpCodeBImmCond.cs @@ -22,4 +22,4 @@ namespace ARMeilleure.Decoders Immediate = (long)address + DecoderHelper.DecodeImmS19_2(opCode); } } -}
\ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeBImmTest.cs b/src/ARMeilleure/Decoders/OpCodeBImmTest.cs index bad98405..f989e59e 100644 --- a/src/ARMeilleure/Decoders/OpCodeBImmTest.cs +++ b/src/ARMeilleure/Decoders/OpCodeBImmTest.cs @@ -2,7 +2,7 @@ namespace ARMeilleure.Decoders { class OpCodeBImmTest : OpCodeBImm { - public int Rt { get; } + public int Rt { get; } public int Bit { get; } public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeBImmTest(inst, address, opCode); @@ -13,8 +13,8 @@ namespace ARMeilleure.Decoders Immediate = (long)address + DecoderHelper.DecodeImmS14_2(opCode); - Bit = (opCode >> 19) & 0x1f; + Bit = (opCode >> 19) & 0x1f; Bit |= (opCode >> 26) & 0x20; } } -}
\ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeBReg.cs b/src/ARMeilleure/Decoders/OpCodeBReg.cs index b5dcbfd8..3b84cf5c 100644 --- a/src/ARMeilleure/Decoders/OpCodeBReg.cs +++ b/src/ARMeilleure/Decoders/OpCodeBReg.cs @@ -8,7 +8,7 @@ namespace ARMeilleure.Decoders public OpCodeBReg(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { - int op4 = (opCode >> 0) & 0x1f; + int op4 = (opCode >> 0) & 0x1f; int op2 = (opCode >> 16) & 0x1f; if (op2 != 0b11111 || op4 != 0b00000) @@ -21,4 +21,4 @@ namespace ARMeilleure.Decoders Rn = (opCode >> 5) & 0x1f; } } -}
\ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeBfm.cs b/src/ARMeilleure/Decoders/OpCodeBfm.cs index 8e1c7836..d51efade 100644 --- a/src/ARMeilleure/Decoders/OpCodeBfm.cs +++ b/src/ARMeilleure/Decoders/OpCodeBfm.cs @@ -4,8 +4,8 @@ namespace ARMeilleure.Decoders { public long WMask { get; } public long TMask { get; } - public int Pos { get; } - public int Shift { get; } + public int Pos { get; } + public int Shift { get; } public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeBfm(inst, address, opCode); @@ -22,8 +22,8 @@ namespace ARMeilleure.Decoders WMask = bm.WMask; TMask = bm.TMask; - Pos = bm.Pos; + Pos = bm.Pos; Shift = bm.Shift; } } -}
\ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeCcmp.cs b/src/ARMeilleure/Decoders/OpCodeCcmp.cs index aa47146f..d4035348 100644 --- a/src/ARMeilleure/Decoders/OpCodeCcmp.cs +++ b/src/ARMeilleure/Decoders/OpCodeCcmp.cs @@ -4,7 +4,7 @@ namespace ARMeilleure.Decoders { class OpCodeCcmp : OpCodeAlu, IOpCodeCond { - public int Nzcv { get; } + public int Nzcv { get; } protected int RmImm; public Condition Cond { get; } @@ -22,11 +22,11 @@ namespace ARMeilleure.Decoders return; } - Nzcv = (opCode >> 0) & 0xf; - Cond = (Condition)((opCode >> 12) & 0xf); - RmImm = (opCode >> 16) & 0x1f; + Nzcv = (opCode >> 0) & 0xf; + Cond = (Condition)((opCode >> 12) & 0xf); + RmImm = (opCode >> 16) & 0x1f; Rd = RegisterAlias.Zr; } } -}
\ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeCcmpImm.cs b/src/ARMeilleure/Decoders/OpCodeCcmpImm.cs index 3548f2da..9d6acf19 100644 --- a/src/ARMeilleure/Decoders/OpCodeCcmpImm.cs +++ b/src/ARMeilleure/Decoders/OpCodeCcmpImm.cs @@ -8,4 +8,4 @@ namespace ARMeilleure.Decoders public OpCodeCcmpImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { } } -}
\ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeCcmpReg.cs b/src/ARMeilleure/Decoders/OpCodeCcmpReg.cs index d5df3b10..349afa12 100644 --- a/src/ARMeilleure/Decoders/OpCodeCcmpReg.cs +++ b/src/ARMeilleure/Decoders/OpCodeCcmpReg.cs @@ -12,4 +12,4 @@ namespace ARMeilleure.Decoders public OpCodeCcmpReg(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { } } -}
\ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeCsel.cs b/src/ARMeilleure/Decoders/OpCodeCsel.cs index 4b8dc7fd..418962e0 100644 --- a/src/ARMeilleure/Decoders/OpCodeCsel.cs +++ b/src/ARMeilleure/Decoders/OpCodeCsel.cs @@ -10,8 +10,8 @@ namespace ARMeilleure.Decoders public OpCodeCsel(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { - Rm = (opCode >> 16) & 0x1f; + Rm = (opCode >> 16) & 0x1f; Cond = (Condition)((opCode >> 12) & 0xf); } } -}
\ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeException.cs b/src/ARMeilleure/Decoders/OpCodeException.cs index 6b72138e..eee63640 100644 --- a/src/ARMeilleure/Decoders/OpCodeException.cs +++ b/src/ARMeilleure/Decoders/OpCodeException.cs @@ -11,4 +11,4 @@ namespace ARMeilleure.Decoders Id = (opCode >> 5) & 0xffff; } } -}
\ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeMem.cs b/src/ARMeilleure/Decoders/OpCodeMem.cs index 0ba2bcd1..9b4e5ff3 100644 --- a/src/ARMeilleure/Decoders/OpCodeMem.cs +++ b/src/ARMeilleure/Decoders/OpCodeMem.cs @@ -2,18 +2,18 @@ namespace ARMeilleure.Decoders { class OpCodeMem : OpCode { - public int Rt { get; protected set; } - public int Rn { get; protected set; } - public int Size { get; protected set; } + public int Rt { get; protected set; } + public int Rn { get; protected set; } + public int Size { get; protected set; } public bool Extend64 { get; protected set; } public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeMem(inst, address, opCode); public OpCodeMem(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { - Rt = (opCode >> 0) & 0x1f; - Rn = (opCode >> 5) & 0x1f; + Rt = (opCode >> 0) & 0x1f; + Rn = (opCode >> 5) & 0x1f; Size = (opCode >> 30) & 0x3; } } -}
\ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeMemEx.cs b/src/ARMeilleure/Decoders/OpCodeMemEx.cs index 89902485..1dc73140 100644 --- a/src/ARMeilleure/Decoders/OpCodeMemEx.cs +++ b/src/ARMeilleure/Decoders/OpCodeMemEx.cs @@ -3,14 +3,14 @@ namespace ARMeilleure.Decoders class OpCodeMemEx : OpCodeMem { public int Rt2 { get; } - public int Rs { get; } + public int Rs { get; } public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeMemEx(inst, address, opCode); public OpCodeMemEx(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Rt2 = (opCode >> 10) & 0x1f; - Rs = (opCode >> 16) & 0x1f; + Rs = (opCode >> 16) & 0x1f; } } -}
\ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeMemImm.cs b/src/ARMeilleure/Decoders/OpCodeMemImm.cs index d6ed2282..4d5eeb1e 100644 --- a/src/ARMeilleure/Decoders/OpCodeMemImm.cs +++ b/src/ARMeilleure/Decoders/OpCodeMemImm.cs @@ -2,18 +2,18 @@ namespace ARMeilleure.Decoders { class OpCodeMemImm : OpCodeMem { - public long Immediate { get; protected set; } - public bool WBack { get; protected set; } - public bool PostIdx { get; protected set; } - protected bool Unscaled { get; } + public long Immediate { get; protected set; } + public bool WBack { get; protected set; } + public bool PostIdx { get; protected set; } + protected bool Unscaled { get; } private enum MemOp { - Unscaled = 0, - PostIndexed = 1, + Unscaled = 0, + PostIndexed = 1, Unprivileged = 2, - PreIndexed = 3, - Unsigned + PreIndexed = 3, + Unsigned, } public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeMemImm(inst, address, opCode); @@ -21,13 +21,13 @@ namespace ARMeilleure.Decoders public OpCodeMemImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { Extend64 = ((opCode >> 22) & 3) == 2; - WBack = ((opCode >> 24) & 1) == 0; + WBack = ((opCode >> 24) & 1) == 0; // The type is not valid for the Unsigned Immediate 12-bits encoding, // because the bits 11:10 are used for the larger Immediate offset. MemOp type = WBack ? (MemOp)((opCode >> 10) & 3) : MemOp.Unsigned; - PostIdx = type == MemOp.PostIndexed; + PostIdx = type == MemOp.PostIndexed; Unscaled = type == MemOp.Unscaled || type == MemOp.Unprivileged; @@ -50,4 +50,4 @@ namespace ARMeilleure.Decoders } } } -}
\ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeMemLit.cs b/src/ARMeilleure/Decoders/OpCodeMemLit.cs index 986d6634..8712a78e 100644 --- a/src/ARMeilleure/Decoders/OpCodeMemLit.cs +++ b/src/ARMeilleure/Decoders/OpCodeMemLit.cs @@ -2,11 +2,11 @@ namespace ARMeilleure.Decoders { class OpCodeMemLit : OpCode, IOpCodeLit { - public int Rt { get; } + public int Rt { get; } public long Immediate { get; } - public int Size { get; } - public bool Signed { get; } - public bool Prefetch { get; } + public int Size { get; } + public bool Signed { get; } + public bool Prefetch { get; } public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeMemLit(inst, address, opCode); @@ -18,11 +18,27 @@ namespace ARMeilleure.Decoders switch ((opCode >> 30) & 3) { - case 0: Size = 2; Signed = false; Prefetch = false; break; - case 1: Size = 3; Signed = false; Prefetch = false; break; - case 2: Size = 2; Signed = true; Prefetch = false; break; - case 3: Size = 0; Signed = false; Prefetch = true; break; + case 0: + Size = 2; + Signed = false; + Prefetch = false; + break; + case 1: + Size = 3; + Signed = false; + Prefetch = false; + break; + case 2: + Size = 2; + Signed = true; + Prefetch = false; + break; + case 3: + Size = 0; + Signed = false; + Prefetch = true; + break; } } } -}
\ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeMemPair.cs b/src/ARMeilleure/Decoders/OpCodeMemPair.cs index 21018033..eb696cfe 100644 --- a/src/ARMeilleure/Decoders/OpCodeMemPair.cs +++ b/src/ARMeilleure/Decoders/OpCodeMemPair.cs @@ -8,11 +8,11 @@ namespace ARMeilleure.Decoders public OpCodeMemPair(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { - Rt2 = (opCode >> 10) & 0x1f; - WBack = ((opCode >> 23) & 0x1) != 0; - PostIdx = ((opCode >> 23) & 0x3) == 1; + Rt2 = (opCode >> 10) & 0x1f; + WBack = ((opCode >> 23) & 0x1) != 0; + PostIdx = ((opCode >> 23) & 0x3) == 1; Extend64 = ((opCode >> 30) & 0x3) == 1; - Size = ((opCode >> 31) & 0x1) | 2; + Size = ((opCode >> 31) & 0x1) | 2; DecodeImm(opCode); } @@ -22,4 +22,4 @@ namespace ARMeilleure.Decoders Immediate = ((long)(opCode >> 15) << 57) >> (57 - Size); } } -}
\ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeMemReg.cs b/src/ARMeilleure/Decoders/OpCodeMemReg.cs index 73d6c5d2..9b0d1595 100644 --- a/src/ARMeilleure/Decoders/OpCodeMemReg.cs +++ b/src/ARMeilleure/Decoders/OpCodeMemReg.cs @@ -3,7 +3,7 @@ namespace ARMeilleure.Decoders class OpCodeMemReg : OpCodeMem { public bool Shift { get; } - public int Rm { get; } + public int Rm { get; } public IntType IntType { get; } @@ -11,10 +11,10 @@ namespace ARMeilleure.Decoders public OpCodeMemReg(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { - Shift = ((opCode >> 12) & 0x1) != 0; - IntType = (IntType)((opCode >> 13) & 0x7); - Rm = (opCode >> 16) & 0x1f; - Extend64 = ((opCode >> 22) & 0x3) == 2; + Shift = ((opCode >> 12) & 0x1) != 0; + IntType = (IntType)((opCode >> 13) & 0x7); + Rm = (opCode >> 16) & 0x1f; + Extend64 = ((opCode >> 22) & 0x3) == 2; } } -}
\ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeMov.cs b/src/ARMeilleure/Decoders/OpCodeMov.cs index 50af88cb..a2914b71 100644 --- a/src/ARMeilleure/Decoders/OpCodeMov.cs +++ b/src/ARMeilleure/Decoders/OpCodeMov.cs @@ -22,9 +22,9 @@ namespace ARMeilleure.Decoders return; } - Rd = (opCode >> 0) & 0x1f; - Immediate = (opCode >> 5) & 0xffff; - Bit = (opCode >> 21) & 0x3; + Rd = (opCode >> 0) & 0x1f; + Immediate = (opCode >> 5) & 0xffff; + Bit = (opCode >> 21) & 0x3; Bit <<= 4; @@ -35,4 +35,4 @@ namespace ARMeilleure.Decoders : RegisterSize.Int32; } } -}
\ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeMul.cs b/src/ARMeilleure/Decoders/OpCodeMul.cs index 31d140a6..9b1dd37b 100644 --- a/src/ARMeilleure/Decoders/OpCodeMul.cs +++ b/src/ARMeilleure/Decoders/OpCodeMul.cs @@ -13,4 +13,4 @@ namespace ARMeilleure.Decoders Rm = (opCode >> 16) & 0x1f; } } -}
\ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeSimd.cs b/src/ARMeilleure/Decoders/OpCodeSimd.cs index 85713690..bd34d74d 100644 --- a/src/ARMeilleure/Decoders/OpCodeSimd.cs +++ b/src/ARMeilleure/Decoders/OpCodeSimd.cs @@ -2,18 +2,18 @@ namespace ARMeilleure.Decoders { class OpCodeSimd : OpCode, IOpCodeSimd { - public int Rd { get; } - public int Rn { get; } - public int Opc { get; } + public int Rd { get; } + public int Rn { get; } + public int Opc { get; } public int Size { get; protected set; } public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimd(inst, address, opCode); public OpCodeSimd(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { - Rd = (opCode >> 0) & 0x1f; - Rn = (opCode >> 5) & 0x1f; - Opc = (opCode >> 15) & 0x3; + Rd = (opCode >> 0) & 0x1f; + Rn = (opCode >> 5) & 0x1f; + Opc = (opCode >> 15) & 0x3; Size = (opCode >> 22) & 0x3; RegisterSize = ((opCode >> 30) & 1) != 0 @@ -21,4 +21,4 @@ namespace ARMeilleure.Decoders : RegisterSize.Simd64; } } -}
\ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeSimdCvt.cs b/src/ARMeilleure/Decoders/OpCodeSimdCvt.cs index 05b32941..e50cf12e 100644 --- a/src/ARMeilleure/Decoders/OpCodeSimdCvt.cs +++ b/src/ARMeilleure/Decoders/OpCodeSimdCvt.cs @@ -9,7 +9,7 @@ namespace ARMeilleure.Decoders public OpCodeSimdCvt(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { int scale = (opCode >> 10) & 0x3f; - int sf = (opCode >> 31) & 0x1; + int sf = (opCode >> 31) & 0x1; FBits = 64 - scale; @@ -18,4 +18,4 @@ namespace ARMeilleure.Decoders : RegisterSize.Int32; } } -}
\ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeSimdExt.cs b/src/ARMeilleure/Decoders/OpCodeSimdExt.cs index a0e264d9..0a3359e1 100644 --- a/src/ARMeilleure/Decoders/OpCodeSimdExt.cs +++ b/src/ARMeilleure/Decoders/OpCodeSimdExt.cs @@ -11,4 +11,4 @@ namespace ARMeilleure.Decoders Imm4 = (opCode >> 11) & 0xf; } } -}
\ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeSimdFcond.cs b/src/ARMeilleure/Decoders/OpCodeSimdFcond.cs index aa16e0c1..510cd310 100644 --- a/src/ARMeilleure/Decoders/OpCodeSimdFcond.cs +++ b/src/ARMeilleure/Decoders/OpCodeSimdFcond.cs @@ -10,7 +10,7 @@ namespace ARMeilleure.Decoders public OpCodeSimdFcond(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { - Nzcv = (opCode >> 0) & 0xf; + Nzcv = (opCode >> 0) & 0xf; Cond = (Condition)((opCode >> 12) & 0xf); } } diff --git a/src/ARMeilleure/Decoders/OpCodeSimdFmov.cs b/src/ARMeilleure/Decoders/OpCodeSimdFmov.cs index 9f9062b8..662abe28 100644 --- a/src/ARMeilleure/Decoders/OpCodeSimdFmov.cs +++ b/src/ARMeilleure/Decoders/OpCodeSimdFmov.cs @@ -2,9 +2,9 @@ namespace ARMeilleure.Decoders { class OpCodeSimdFmov : OpCode, IOpCodeSimd { - public int Rd { get; } + public int Rd { get; } public long Immediate { get; } - public int Size { get; } + public int Size { get; } public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimdFmov(inst, address, opCode); @@ -16,7 +16,7 @@ namespace ARMeilleure.Decoders long imm; - Rd = (opCode >> 0) & 0x1f; + Rd = (opCode >> 0) & 0x1f; imm = (opCode >> 13) & 0xff; if (type == 0) @@ -29,4 +29,4 @@ namespace ARMeilleure.Decoders } } } -}
\ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeSimdHelper.cs b/src/ARMeilleure/Decoders/OpCodeSimdHelper.cs index 02f74d03..d900ed9b 100644 --- a/src/ARMeilleure/Decoders/OpCodeSimdHelper.cs +++ b/src/ARMeilleure/Decoders/OpCodeSimdHelper.cs @@ -52,17 +52,20 @@ else if ((modeHigh & 0b110) == 0b100) { // 16-bits shifted Immediate. - size = 1; imm <<= (modeHigh & 1) << 3; + size = 1; + imm <<= (modeHigh & 1) << 3; } else if ((modeHigh & 0b100) == 0b000) { // 32-bits shifted Immediate. - size = 2; imm <<= modeHigh << 3; + size = 2; + imm <<= modeHigh << 3; } else if ((modeHigh & 0b111) == 0b110) { // 32-bits shifted Immediate (fill with ones). - size = 2; imm = ShlOnes(imm, 8 << modeLow); + size = 2; + imm = ShlOnes(imm, 8 << modeLow); } else { diff --git a/src/ARMeilleure/Decoders/OpCodeSimdImm.cs b/src/ARMeilleure/Decoders/OpCodeSimdImm.cs index eeca7709..3f4bad7f 100644 --- a/src/ARMeilleure/Decoders/OpCodeSimdImm.cs +++ b/src/ARMeilleure/Decoders/OpCodeSimdImm.cs @@ -2,9 +2,9 @@ namespace ARMeilleure.Decoders { class OpCodeSimdImm : OpCode, IOpCodeSimd { - public int Rd { get; } + public int Rd { get; } public long Immediate { get; } - public int Size { get; } + public int Size { get; } public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimdImm(inst, address, opCode); @@ -13,14 +13,14 @@ namespace ARMeilleure.Decoders Rd = opCode & 0x1f; int cMode = (opCode >> 12) & 0xf; - int op = (opCode >> 29) & 0x1; + int op = (opCode >> 29) & 0x1; - int modeLow = cMode & 1; + int modeLow = cMode & 1; int modeHigh = cMode >> 1; long imm; - imm = ((uint)opCode >> 5) & 0x1f; + imm = ((uint)opCode >> 5) & 0x1f; imm |= ((uint)opCode >> 11) & 0xe0; if (modeHigh == 0b111) @@ -67,17 +67,20 @@ namespace ARMeilleure.Decoders else if ((modeHigh & 0b110) == 0b100) { // 16-bits shifted Immediate. - Size = 1; imm <<= (modeHigh & 1) << 3; + Size = 1; + imm <<= (modeHigh & 1) << 3; } else if ((modeHigh & 0b100) == 0b000) { // 32-bits shifted Immediate. - Size = 2; imm <<= modeHigh << 3; + Size = 2; + imm <<= modeHigh << 3; } else if ((modeHigh & 0b111) == 0b110) { // 32-bits shifted Immediate (fill with ones). - Size = 2; imm = ShlOnes(imm, 8 << modeLow); + Size = 2; + imm = ShlOnes(imm, 8 << modeLow); } else { @@ -104,4 +107,4 @@ namespace ARMeilleure.Decoders } } } -}
\ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeSimdIns.cs b/src/ARMeilleure/Decoders/OpCodeSimdIns.cs index f6f9249d..95436879 100644 --- a/src/ARMeilleure/Decoders/OpCodeSimdIns.cs +++ b/src/ARMeilleure/Decoders/OpCodeSimdIns.cs @@ -23,14 +23,22 @@ namespace ARMeilleure.Decoders switch (Size) { - case 1: Size = 0; break; - case 2: Size = 1; break; - case 4: Size = 2; break; - case 8: Size = 3; break; + case 1: + Size = 0; + break; + case 2: + Size = 1; + break; + case 4: + Size = 2; + break; + case 8: + Size = 3; + break; } - SrcIndex = imm4 >> Size; + SrcIndex = imm4 >> Size; DstIndex = imm5 >> (Size + 1); } } -}
\ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeSimdMemImm.cs b/src/ARMeilleure/Decoders/OpCodeSimdMemImm.cs index c11594cb..14a9d7c9 100644 --- a/src/ARMeilleure/Decoders/OpCodeSimdMemImm.cs +++ b/src/ARMeilleure/Decoders/OpCodeSimdMemImm.cs @@ -25,4 +25,4 @@ namespace ARMeilleure.Decoders Extend64 = false; } } -}
\ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeSimdMemLit.cs b/src/ARMeilleure/Decoders/OpCodeSimdMemLit.cs index 8e212966..efa558bf 100644 --- a/src/ARMeilleure/Decoders/OpCodeSimdMemLit.cs +++ b/src/ARMeilleure/Decoders/OpCodeSimdMemLit.cs @@ -2,10 +2,10 @@ namespace ARMeilleure.Decoders { class OpCodeSimdMemLit : OpCode, IOpCodeSimd, IOpCodeLit { - public int Rt { get; } + public int Rt { get; } public long Immediate { get; } - public int Size { get; } - public bool Signed => false; + public int Size { get; } + public bool Signed => false; public bool Prefetch => false; public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimdMemLit(inst, address, opCode); @@ -28,4 +28,4 @@ namespace ARMeilleure.Decoders Size = opc + 2; } } -}
\ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeSimdMemMs.cs b/src/ARMeilleure/Decoders/OpCodeSimdMemMs.cs index 8922c18f..c05b5249 100644 --- a/src/ARMeilleure/Decoders/OpCodeSimdMemMs.cs +++ b/src/ARMeilleure/Decoders/OpCodeSimdMemMs.cs @@ -2,10 +2,10 @@ namespace ARMeilleure.Decoders { class OpCodeSimdMemMs : OpCodeMemReg, IOpCodeSimd { - public int Reps { get; } - public int SElems { get; } - public int Elems { get; } - public bool WBack { get; } + public int Reps { get; } + public int SElems { get; } + public int Elems { get; } + public bool WBack { get; } public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimdMemMs(inst, address, opCode); @@ -13,18 +13,41 @@ namespace ARMeilleure.Decoders { switch ((opCode >> 12) & 0xf) { - case 0b0000: Reps = 1; SElems = 4; break; - case 0b0010: Reps = 4; SElems = 1; break; - case 0b0100: Reps = 1; SElems = 3; break; - case 0b0110: Reps = 3; SElems = 1; break; - case 0b0111: Reps = 1; SElems = 1; break; - case 0b1000: Reps = 1; SElems = 2; break; - case 0b1010: Reps = 2; SElems = 1; break; - - default: Instruction = InstDescriptor.Undefined; return; + case 0b0000: + Reps = 1; + SElems = 4; + break; + case 0b0010: + Reps = 4; + SElems = 1; + break; + case 0b0100: + Reps = 1; + SElems = 3; + break; + case 0b0110: + Reps = 3; + SElems = 1; + break; + case 0b0111: + Reps = 1; + SElems = 1; + break; + case 0b1000: + Reps = 1; + SElems = 2; + break; + case 0b1010: + Reps = 2; + SElems = 1; + break; + + default: + Instruction = InstDescriptor.Undefined; + return; } - Size = (opCode >> 10) & 3; + Size = (opCode >> 10) & 3; WBack = ((opCode >> 23) & 1) != 0; bool q = ((opCode >> 30) & 1) != 0; @@ -45,4 +68,4 @@ namespace ARMeilleure.Decoders Elems = (GetBitsCount() >> 3) >> Size; } } -}
\ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeSimdMemPair.cs b/src/ARMeilleure/Decoders/OpCodeSimdMemPair.cs index 1ab95367..69716389 100644 --- a/src/ARMeilleure/Decoders/OpCodeSimdMemPair.cs +++ b/src/ARMeilleure/Decoders/OpCodeSimdMemPair.cs @@ -13,4 +13,4 @@ namespace ARMeilleure.Decoders DecodeImm(opCode); } } -}
\ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeSimdMemReg.cs b/src/ARMeilleure/Decoders/OpCodeSimdMemReg.cs index 9ea6dda3..be7b25b9 100644 --- a/src/ARMeilleure/Decoders/OpCodeSimdMemReg.cs +++ b/src/ARMeilleure/Decoders/OpCodeSimdMemReg.cs @@ -18,4 +18,4 @@ namespace ARMeilleure.Decoders Extend64 = false; } } -}
\ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeSimdMemSs.cs b/src/ARMeilleure/Decoders/OpCodeSimdMemSs.cs index 44abdd38..5bc614e1 100644 --- a/src/ARMeilleure/Decoders/OpCodeSimdMemSs.cs +++ b/src/ARMeilleure/Decoders/OpCodeSimdMemSs.cs @@ -2,21 +2,21 @@ namespace ARMeilleure.Decoders { class OpCodeSimdMemSs : OpCodeMemReg, IOpCodeSimd { - public int SElems { get; } - public int Index { get; } + public int SElems { get; } + public int Index { get; } public bool Replicate { get; } - public bool WBack { get; } + public bool WBack { get; } public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimdMemSs(inst, address, opCode); public OpCodeSimdMemSs(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { - int size = (opCode >> 10) & 3; - int s = (opCode >> 12) & 1; + int size = (opCode >> 10) & 3; + int s = (opCode >> 12) & 1; int sElems = (opCode >> 12) & 2; - int scale = (opCode >> 14) & 3; - int l = (opCode >> 22) & 1; - int q = (opCode >> 30) & 1; + int scale = (opCode >> 14) & 3; + int l = (opCode >> 22) & 1; + int q = (opCode >> 30) & 1; sElems |= (opCode >> 21) & 1; @@ -27,63 +27,63 @@ namespace ARMeilleure.Decoders switch (scale) { case 1: - { - if ((size & 1) != 0) { - Instruction = InstDescriptor.Undefined; + if ((size & 1) != 0) + { + Instruction = InstDescriptor.Undefined; - return; - } - - index >>= 1; - - break; - } + return; + } - case 2: - { - if ((size & 2) != 0 || - ((size & 1) != 0 && s != 0)) - { - Instruction = InstDescriptor.Undefined; + index >>= 1; - return; + break; } - if ((size & 1) != 0) - { - index >>= 3; - - scale = 3; - } - else + case 2: { - index >>= 2; + if ((size & 2) != 0 || + ((size & 1) != 0 && s != 0)) + { + Instruction = InstDescriptor.Undefined; + + return; + } + + if ((size & 1) != 0) + { + index >>= 3; + + scale = 3; + } + else + { + index >>= 2; + } + + break; } - break; - } - case 3: - { - if (l == 0 || s != 0) { - Instruction = InstDescriptor.Undefined; + if (l == 0 || s != 0) + { + Instruction = InstDescriptor.Undefined; - return; - } + return; + } - scale = size; + scale = size; - Replicate = true; + Replicate = true; - break; - } + break; + } } - Index = index; + Index = index; SElems = sElems; - Size = scale; + Size = scale; Extend64 = false; @@ -94,4 +94,4 @@ namespace ARMeilleure.Decoders : RegisterSize.Simd64; } } -}
\ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeSimdReg.cs b/src/ARMeilleure/Decoders/OpCodeSimdReg.cs index ac4f71da..40f9b1c5 100644 --- a/src/ARMeilleure/Decoders/OpCodeSimdReg.cs +++ b/src/ARMeilleure/Decoders/OpCodeSimdReg.cs @@ -3,16 +3,16 @@ namespace ARMeilleure.Decoders class OpCodeSimdReg : OpCodeSimd { public bool Bit3 { get; } - public int Ra { get; } - public int Rm { get; protected set; } + public int Ra { get; } + public int Rm { get; protected set; } public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeSimdReg(inst, address, opCode); public OpCodeSimdReg(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { - Bit3 = ((opCode >> 3) & 0x1) != 0; - Ra = (opCode >> 10) & 0x1f; - Rm = (opCode >> 16) & 0x1f; + Bit3 = ((opCode >> 3) & 0x1) != 0; + Ra = (opCode >> 10) & 0x1f; + Rm = (opCode >> 16) & 0x1f; } } -}
\ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeSimdRegElem.cs b/src/ARMeilleure/Decoders/OpCodeSimdRegElem.cs index 92368dee..bb248ab6 100644 --- a/src/ARMeilleure/Decoders/OpCodeSimdRegElem.cs +++ b/src/ARMeilleure/Decoders/OpCodeSimdRegElem.cs @@ -12,7 +12,7 @@ namespace ARMeilleure.Decoders { case 1: Index = (opCode >> 20) & 3 | - (opCode >> 9) & 4; + (opCode >> 9) & 4; Rm &= 0xf; @@ -24,8 +24,10 @@ namespace ARMeilleure.Decoders break; - default: Instruction = InstDescriptor.Undefined; break; + default: + Instruction = InstDescriptor.Undefined; + break; } } } -}
\ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeSimdRegElemF.cs b/src/ARMeilleure/Decoders/OpCodeSimdRegElemF.cs index d46dd57e..c97bd787 100644 --- a/src/ARMeilleure/Decoders/OpCodeSimdRegElemF.cs +++ b/src/ARMeilleure/Decoders/OpCodeSimdRegElemF.cs @@ -26,7 +26,9 @@ namespace ARMeilleure.Decoders break; - default: Instruction = InstDescriptor.Undefined; break; + default: + Instruction = InstDescriptor.Undefined; + break; } } } diff --git a/src/ARMeilleure/Decoders/OpCodeSimdTbl.cs b/src/ARMeilleure/Decoders/OpCodeSimdTbl.cs index 9c631e48..3a7ef6ab 100644 --- a/src/ARMeilleure/Decoders/OpCodeSimdTbl.cs +++ b/src/ARMeilleure/Decoders/OpCodeSimdTbl.cs @@ -9,4 +9,4 @@ namespace ARMeilleure.Decoders Size = ((opCode >> 13) & 3) + 1; } } -}
\ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeSystem.cs b/src/ARMeilleure/Decoders/OpCodeSystem.cs index 4d79421a..21513415 100644 --- a/src/ARMeilleure/Decoders/OpCodeSystem.cs +++ b/src/ARMeilleure/Decoders/OpCodeSystem.cs @@ -2,7 +2,7 @@ namespace ARMeilleure.Decoders { class OpCodeSystem : OpCode { - public int Rt { get; } + public int Rt { get; } public int Op2 { get; } public int CRm { get; } public int CRn { get; } @@ -13,12 +13,12 @@ namespace ARMeilleure.Decoders public OpCodeSystem(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { - Rt = (opCode >> 0) & 0x1f; - Op2 = (opCode >> 5) & 0x7; - CRm = (opCode >> 8) & 0xf; - CRn = (opCode >> 12) & 0xf; - Op1 = (opCode >> 16) & 0x7; + Rt = (opCode >> 0) & 0x1f; + Op2 = (opCode >> 5) & 0x7; + CRm = (opCode >> 8) & 0xf; + CRn = (opCode >> 12) & 0xf; + Op1 = (opCode >> 16) & 0x7; Op0 = ((opCode >> 19) & 0x1) | 2; } } -}
\ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeT16.cs b/src/ARMeilleure/Decoders/OpCodeT16.cs index 9c3d6b00..de946b96 100644 --- a/src/ARMeilleure/Decoders/OpCodeT16.cs +++ b/src/ARMeilleure/Decoders/OpCodeT16.cs @@ -12,4 +12,4 @@ namespace ARMeilleure.Decoders OpCodeSizeInBytes = 2; } } -}
\ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeT16AddSubImm3.cs b/src/ARMeilleure/Decoders/OpCodeT16AddSubImm3.cs index 95f18054..cefb50e4 100644 --- a/src/ARMeilleure/Decoders/OpCodeT16AddSubImm3.cs +++ b/src/ARMeilleure/Decoders/OpCodeT16AddSubImm3.cs @@ -1,6 +1,6 @@ namespace ARMeilleure.Decoders { - class OpCodeT16AddSubImm3: OpCodeT16, IOpCode32AluImm + class OpCodeT16AddSubImm3 : OpCodeT16, IOpCode32AluImm { public int Rd { get; } public int Rn { get; } @@ -15,8 +15,8 @@ public OpCodeT16AddSubImm3(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { - Rd = (opCode >> 0) & 0x7; - Rn = (opCode >> 3) & 0x7; + Rd = (opCode >> 0) & 0x7; + Rn = (opCode >> 3) & 0x7; Immediate = (opCode >> 6) & 0x7; IsRotated = false; } diff --git a/src/ARMeilleure/Decoders/OpCodeT16BImm11.cs b/src/ARMeilleure/Decoders/OpCodeT16BImm11.cs index f230b20e..fab098a8 100644 --- a/src/ARMeilleure/Decoders/OpCodeT16BImm11.cs +++ b/src/ARMeilleure/Decoders/OpCodeT16BImm11.cs @@ -8,7 +8,7 @@ public OpCodeT16BImm11(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { - int imm = (opCode << 21) >> 20; + int imm = (opCode << 21) >> 20; Immediate = GetPc() + imm; } } diff --git a/src/ARMeilleure/Decoders/OpCodeT16BImm8.cs b/src/ARMeilleure/Decoders/OpCodeT16BImm8.cs index 5f684298..edfa86ba 100644 --- a/src/ARMeilleure/Decoders/OpCodeT16BImm8.cs +++ b/src/ARMeilleure/Decoders/OpCodeT16BImm8.cs @@ -10,7 +10,7 @@ { Cond = (Condition)((opCode >> 8) & 0xf); - int imm = (opCode << 24) >> 23; + int imm = (opCode << 24) >> 23; Immediate = GetPc() + imm; } } diff --git a/src/ARMeilleure/Decoders/OpCodeT16MemImm5.cs b/src/ARMeilleure/Decoders/OpCodeT16MemImm5.cs index 20ef31e2..873c63b9 100644 --- a/src/ARMeilleure/Decoders/OpCodeT16MemImm5.cs +++ b/src/ARMeilleure/Decoders/OpCodeT16MemImm5.cs @@ -36,23 +36,13 @@ namespace ARMeilleure.Decoders break; } - switch (inst.Name) + Immediate = inst.Name switch { - case InstName.Str: - case InstName.Ldr: - Immediate = ((opCode >> 6) & 0x1f) << 2; - break; - case InstName.Strb: - case InstName.Ldrb: - Immediate = ((opCode >> 6) & 0x1f); - break; - case InstName.Strh: - case InstName.Ldrh: - Immediate = ((opCode >> 6) & 0x1f) << 1; - break; - default: - throw new InvalidOperationException(); - } + InstName.Str or InstName.Ldr => ((opCode >> 6) & 0x1f) << 2, + InstName.Strb or InstName.Ldrb => ((opCode >> 6) & 0x1f), + InstName.Strh or InstName.Ldrh => ((opCode >> 6) & 0x1f) << 1, + _ => throw new InvalidOperationException(), + }; } } } diff --git a/src/ARMeilleure/Decoders/OpCodeT16MemMult.cs b/src/ARMeilleure/Decoders/OpCodeT16MemMult.cs index f4185cfc..3f3057ac 100644 --- a/src/ARMeilleure/Decoders/OpCodeT16MemMult.cs +++ b/src/ARMeilleure/Decoders/OpCodeT16MemMult.cs @@ -27,7 +27,7 @@ namespace ARMeilleure.Decoders { InstName.Ldm => true, InstName.Stm => false, - _ => throw new InvalidOperationException() + _ => throw new InvalidOperationException(), }; } } diff --git a/src/ARMeilleure/Decoders/OpCodeT16ShiftImm.cs b/src/ARMeilleure/Decoders/OpCodeT16ShiftImm.cs index a540026e..8f35e439 100644 --- a/src/ARMeilleure/Decoders/OpCodeT16ShiftImm.cs +++ b/src/ARMeilleure/Decoders/OpCodeT16ShiftImm.cs @@ -15,8 +15,8 @@ public OpCodeT16ShiftImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { - Rd = (opCode >> 0) & 0x7; - Rm = (opCode >> 3) & 0x7; + Rd = (opCode >> 0) & 0x7; + Rm = (opCode >> 3) & 0x7; Immediate = (opCode >> 6) & 0x1F; ShiftType = (ShiftType)((opCode >> 11) & 3); } diff --git a/src/ARMeilleure/Decoders/OpCodeT32.cs b/src/ARMeilleure/Decoders/OpCodeT32.cs index cf43d429..5ccbd6a2 100644 --- a/src/ARMeilleure/Decoders/OpCodeT32.cs +++ b/src/ARMeilleure/Decoders/OpCodeT32.cs @@ -12,4 +12,4 @@ OpCodeSizeInBytes = 4; } } -}
\ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeT32Alu.cs b/src/ARMeilleure/Decoders/OpCodeT32Alu.cs index a81b3b3d..1f92f755 100644 --- a/src/ARMeilleure/Decoders/OpCodeT32Alu.cs +++ b/src/ARMeilleure/Decoders/OpCodeT32Alu.cs @@ -17,4 +17,4 @@ SetFlags = ((opCode >> 20) & 1) != 0; } } -}
\ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeT32AluImm.cs b/src/ARMeilleure/Decoders/OpCodeT32AluImm.cs index 0895c29b..863d14bd 100644 --- a/src/ARMeilleure/Decoders/OpCodeT32AluImm.cs +++ b/src/ARMeilleure/Decoders/OpCodeT32AluImm.cs @@ -35,4 +35,4 @@ namespace ARMeilleure.Decoders } } } -}
\ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeT32AluImm12.cs b/src/ARMeilleure/Decoders/OpCodeT32AluImm12.cs index 31de63dd..12b65a10 100644 --- a/src/ARMeilleure/Decoders/OpCodeT32AluImm12.cs +++ b/src/ARMeilleure/Decoders/OpCodeT32AluImm12.cs @@ -13,4 +13,4 @@ namespace ARMeilleure.Decoders Immediate = (opCode & 0xff) | ((opCode >> 4) & 0x700) | ((opCode >> 15) & 0x800); } } -}
\ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeT32AluReg.cs b/src/ARMeilleure/Decoders/OpCodeT32AluReg.cs index a487f55a..4ac98347 100644 --- a/src/ARMeilleure/Decoders/OpCodeT32AluReg.cs +++ b/src/ARMeilleure/Decoders/OpCodeT32AluReg.cs @@ -11,4 +11,4 @@ namespace ARMeilleure.Decoders Rm = (opCode >> 0) & 0xf; } } -}
\ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeT32AluRsImm.cs b/src/ARMeilleure/Decoders/OpCodeT32AluRsImm.cs index 1c9ba7a2..edf0298d 100644 --- a/src/ARMeilleure/Decoders/OpCodeT32AluRsImm.cs +++ b/src/ARMeilleure/Decoders/OpCodeT32AluRsImm.cs @@ -2,7 +2,7 @@ { class OpCodeT32AluRsImm : OpCodeT32Alu, IOpCode32AluRsImm { - public int Rm { get; } + public int Rm { get; } public int Immediate { get; } public ShiftType ShiftType { get; } @@ -11,10 +11,10 @@ public OpCodeT32AluRsImm(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) { - Rm = (opCode >> 0) & 0xf; + Rm = (opCode >> 0) & 0xf; Immediate = ((opCode >> 6) & 3) | ((opCode >> 10) & 0x1c); ShiftType = (ShiftType)((opCode >> 4) & 3); } } -}
\ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeT32BImm20.cs b/src/ARMeilleure/Decoders/OpCodeT32BImm20.cs index b6da8abd..13256ee5 100644 --- a/src/ARMeilleure/Decoders/OpCodeT32BImm20.cs +++ b/src/ARMeilleure/Decoders/OpCodeT32BImm20.cs @@ -24,4 +24,4 @@ Cond = (Condition)((opCode >> 22) & 0xf); } } -}
\ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeT32BImm24.cs b/src/ARMeilleure/Decoders/OpCodeT32BImm24.cs index 774ec3a6..d7c60661 100644 --- a/src/ARMeilleure/Decoders/OpCodeT32BImm24.cs +++ b/src/ARMeilleure/Decoders/OpCodeT32BImm24.cs @@ -32,4 +32,4 @@ namespace ARMeilleure.Decoders Immediate = pc + imm32; } } -}
\ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeT32MemImm12.cs b/src/ARMeilleure/Decoders/OpCodeT32MemImm12.cs index 7838604b..4977cdf5 100644 --- a/src/ARMeilleure/Decoders/OpCodeT32MemImm12.cs +++ b/src/ARMeilleure/Decoders/OpCodeT32MemImm12.cs @@ -22,4 +22,4 @@ IsLoad = ((opCode >> 20) & 1) != 0; } } -}
\ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeT32MemImm8.cs b/src/ARMeilleure/Decoders/OpCodeT32MemImm8.cs index d8b7763c..f84e4140 100644 --- a/src/ARMeilleure/Decoders/OpCodeT32MemImm8.cs +++ b/src/ARMeilleure/Decoders/OpCodeT32MemImm8.cs @@ -18,7 +18,7 @@ Rn = (opCode >> 16) & 0xf; Index = ((opCode >> 10) & 1) != 0; - Add = ((opCode >> 9) & 1) != 0; + Add = ((opCode >> 9) & 1) != 0; WBack = ((opCode >> 8) & 1) != 0; Immediate = opCode & 0xff; @@ -26,4 +26,4 @@ IsLoad = ((opCode >> 20) & 1) != 0; } } -}
\ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeT32MemImm8D.cs b/src/ARMeilleure/Decoders/OpCodeT32MemImm8D.cs index 7a078c48..51f5042f 100644 --- a/src/ARMeilleure/Decoders/OpCodeT32MemImm8D.cs +++ b/src/ARMeilleure/Decoders/OpCodeT32MemImm8D.cs @@ -20,7 +20,7 @@ namespace ARMeilleure.Decoders Rn = (opCode >> 16) & 0xf; Index = ((opCode >> 24) & 1) != 0; - Add = ((opCode >> 23) & 1) != 0; + Add = ((opCode >> 23) & 1) != 0; WBack = ((opCode >> 21) & 1) != 0; Immediate = (opCode & 0xff) << 2; @@ -28,4 +28,4 @@ namespace ARMeilleure.Decoders IsLoad = ((opCode >> 20) & 1) != 0; } } -}
\ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeT32MemMult.cs b/src/ARMeilleure/Decoders/OpCodeT32MemMult.cs index a9ba306d..d155842a 100644 --- a/src/ARMeilleure/Decoders/OpCodeT32MemMult.cs +++ b/src/ARMeilleure/Decoders/OpCodeT32MemMult.cs @@ -7,8 +7,8 @@ namespace ARMeilleure.Decoders public int Rn { get; } public int RegisterMask { get; } - public int Offset { get; } - public int PostOffset { get; } + public int Offset { get; } + public int PostOffset { get; } public bool IsLoad { get; } @@ -19,9 +19,9 @@ namespace ARMeilleure.Decoders Rn = (opCode >> 16) & 0xf; bool isLoad = (opCode & (1 << 20)) != 0; - bool w = (opCode & (1 << 21)) != 0; - bool u = (opCode & (1 << 23)) != 0; - bool p = (opCode & (1 << 24)) != 0; + bool w = (opCode & (1 << 21)) != 0; + bool u = (opCode & (1 << 23)) != 0; + bool p = (opCode & (1 << 24)) != 0; RegisterMask = opCode & 0xffff; @@ -49,4 +49,4 @@ namespace ARMeilleure.Decoders IsLoad = isLoad; } } -}
\ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeT32MovImm16.cs b/src/ARMeilleure/Decoders/OpCodeT32MovImm16.cs index 5161892b..2f871c74 100644 --- a/src/ARMeilleure/Decoders/OpCodeT32MovImm16.cs +++ b/src/ARMeilleure/Decoders/OpCodeT32MovImm16.cs @@ -4,8 +4,6 @@ namespace ARMeilleure.Decoders { public int Immediate { get; } - public bool IsRotated => false; - public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT32MovImm16(inst, address, opCode); public OpCodeT32MovImm16(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode) @@ -13,4 +11,4 @@ namespace ARMeilleure.Decoders Immediate = (opCode & 0xff) | ((opCode >> 4) & 0x700) | ((opCode >> 15) & 0x800) | ((opCode >> 4) & 0xf000); } } -}
\ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeT32Tb.cs b/src/ARMeilleure/Decoders/OpCodeT32Tb.cs index 527754b1..0a4d2a6c 100644 --- a/src/ARMeilleure/Decoders/OpCodeT32Tb.cs +++ b/src/ARMeilleure/Decoders/OpCodeT32Tb.cs @@ -13,4 +13,4 @@ namespace ARMeilleure.Decoders Rn = (opCode >> 16) & 0xf; } } -}
\ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/OpCodeTable.cs b/src/ARMeilleure/Decoders/OpCodeTable.cs index 4f359958..d3fc4ca0 100644 --- a/src/ARMeilleure/Decoders/OpCodeTable.cs +++ b/src/ARMeilleure/Decoders/OpCodeTable.cs @@ -13,7 +13,7 @@ namespace ARMeilleure.Decoders private readonly struct InstInfo { - public int Mask { get; } + public int Mask { get; } public int Value { get; } public InstDescriptor Inst { get; } @@ -22,24 +22,25 @@ namespace ARMeilleure.Decoders public InstInfo(int mask, int value, InstDescriptor inst, MakeOp makeOp) { - Mask = mask; - Value = value; - Inst = inst; + Mask = mask; + Value = value; + Inst = inst; MakeOp = makeOp; } } - private static List<InstInfo> AllInstA32 = new(); - private static List<InstInfo> AllInstT32 = new(); - private static List<InstInfo> AllInstA64 = new(); + private static readonly List<InstInfo> _allInstA32 = new(); + private static readonly List<InstInfo> _allInstT32 = new(); + private static readonly List<InstInfo> _allInstA64 = new(); - private static InstInfo[][] InstA32FastLookup = new InstInfo[FastLookupSize][]; - private static InstInfo[][] InstT32FastLookup = new InstInfo[FastLookupSize][]; - private static InstInfo[][] InstA64FastLookup = new InstInfo[FastLookupSize][]; + private static readonly InstInfo[][] _instA32FastLookup = new InstInfo[FastLookupSize][]; + private static readonly InstInfo[][] _instT32FastLookup = new InstInfo[FastLookupSize][]; + private static readonly InstInfo[][] _instA64FastLookup = new InstInfo[FastLookupSize][]; static OpCodeTable() { -#region "OpCode Table (AArch64)" +#pragma warning disable IDE0055 // Disable formatting + #region "OpCode Table (AArch64)" // Base SetA64("x0011010000xxxxx000000xxxxxxxxxx", InstName.Adc, InstEmit.Adc, OpCodeAluRs.Create); SetA64("x0111010000xxxxx000000xxxxxxxxxx", InstName.Adcs, InstEmit.Adcs, OpCodeAluRs.Create); @@ -638,9 +639,9 @@ namespace ARMeilleure.Decoders SetA64("0x001110<<100001001010xxxxxxxxxx", InstName.Xtn_V, InstEmit.Xtn_V, OpCodeSimd.Create); SetA64("0>001110<<0xxxxx001110xxxxxxxxxx", InstName.Zip1_V, InstEmit.Zip1_V, OpCodeSimdReg.Create); SetA64("0>001110<<0xxxxx011110xxxxxxxxxx", InstName.Zip2_V, InstEmit.Zip2_V, OpCodeSimdReg.Create); -#endregion + #endregion -#region "OpCode Table (AArch32, A32)" + #region "OpCode Table (AArch32, A32)" // Base SetA32("<<<<0010101xxxxxxxxxxxxxxxxxxxxx", InstName.Adc, InstEmit32.Adc, OpCode32AluImm.Create); SetA32("<<<<0000101xxxxxxxxxxxxxxxx0xxxx", InstName.Adc, InstEmit32.Adc, OpCode32AluRsImm.Create); @@ -1050,9 +1051,9 @@ namespace ARMeilleure.Decoders SetAsimd("111100100x<<xxxxxxxx1000xxx1xxxx", InstName.Vtst, InstEmit32.Vtst, OpCode32SimdReg.Create, OpCode32SimdReg.CreateT32); SetAsimd("111100111x11<<10xxxx00010xx0xxxx", InstName.Vuzp, InstEmit32.Vuzp, OpCode32SimdCmpZ.Create, OpCode32SimdCmpZ.CreateT32); SetAsimd("111100111x11<<10xxxx00011xx0xxxx", InstName.Vzip, InstEmit32.Vzip, OpCode32SimdCmpZ.Create, OpCode32SimdCmpZ.CreateT32); -#endregion + #endregion -#region "OpCode Table (AArch32, T16)" + #region "OpCode Table (AArch32, T16)" SetT16("000<<xxxxxxxxxxx", InstName.Mov, InstEmit32.Mov, OpCodeT16ShiftImm.Create); SetT16("0001100xxxxxxxxx", InstName.Add, InstEmit32.Add, OpCodeT16AddSubReg.Create); SetT16("0001101xxxxxxxxx", InstName.Sub, InstEmit32.Sub, OpCodeT16AddSubReg.Create); @@ -1131,7 +1132,7 @@ namespace ARMeilleure.Decoders SetT16("11100xxxxxxxxxxx", InstName.B, InstEmit32.B, OpCodeT16BImm11.Create); #endregion -#region "OpCode Table (AArch32, T32)" + #region "OpCode Table (AArch32, T32)" // Base SetT32("11101011010xxxxx0xxxxxxxxxxxxxxx", InstName.Adc, InstEmit32.Adc, OpCodeT32AluRsImm.Create); SetT32("11110x01010xxxxx0xxxxxxxxxxxxxxx", InstName.Adc, InstEmit32.Adc, OpCodeT32AluImm.Create); @@ -1299,12 +1300,13 @@ namespace ARMeilleure.Decoders SetT32("11110011101011111000000000000001", InstName.Yield, InstEmit32.Nop, OpCodeT32.Create); #endregion - FillFastLookupTable(InstA32FastLookup, AllInstA32, ToFastLookupIndexA); - FillFastLookupTable(InstT32FastLookup, AllInstT32, ToFastLookupIndexT); - FillFastLookupTable(InstA64FastLookup, AllInstA64, ToFastLookupIndexA); + FillFastLookupTable(_instA32FastLookup, _allInstA32, ToFastLookupIndexA); + FillFastLookupTable(_instT32FastLookup, _allInstT32, ToFastLookupIndexT); + FillFastLookupTable(_instA64FastLookup, _allInstA64, ToFastLookupIndexA); +#pragma warning restore IDE0055 } - private static void FillFastLookupTable(InstInfo[][] table, List<InstInfo> allInsts, Func<int, int> ToFastLookupIndex) + private static void FillFastLookupTable(InstInfo[][] table, List<InstInfo> allInsts, Func<int, int> toFastLookupIndex) { List<InstInfo>[] temp = new List<InstInfo>[FastLookupSize]; @@ -1315,8 +1317,8 @@ namespace ARMeilleure.Decoders foreach (InstInfo inst in allInsts) { - int mask = ToFastLookupIndex(inst.Mask); - int value = ToFastLookupIndex(inst.Value); + int mask = toFastLookupIndex(inst.Mask); + int value = toFastLookupIndex(inst.Value); for (int index = 0; index < temp.Length; index++) { @@ -1335,22 +1337,21 @@ namespace ARMeilleure.Decoders private static void SetA32(string encoding, InstName name, InstEmitter emitter, MakeOp makeOp) { - Set(encoding, AllInstA32, new InstDescriptor(name, emitter), makeOp); + Set(encoding, _allInstA32, new InstDescriptor(name, emitter), makeOp); } private static void SetT16(string encoding, InstName name, InstEmitter emitter, MakeOp makeOp) { encoding = "xxxxxxxxxxxxxxxx" + encoding; - Set(encoding, AllInstT32, new InstDescriptor(name, emitter), makeOp); + Set(encoding, _allInstT32, new InstDescriptor(name, emitter), makeOp); } private static void SetT32(string encoding, InstName name, InstEmitter emitter, MakeOp makeOp) { string reversedEncoding = $"{encoding.AsSpan(16)}{encoding.AsSpan(0, 16)}"; - MakeOp reversedMakeOp = - (inst, address, opCode) + OpCode ReversedMakeOp(InstDescriptor inst, ulong address, int opCode) => makeOp(inst, address, (int)BitOperations.RotateRight((uint)opCode, 16)); - Set(reversedEncoding, AllInstT32, new InstDescriptor(name, emitter), reversedMakeOp); + Set(reversedEncoding, _allInstT32, new InstDescriptor(name, emitter), ReversedMakeOp); } private static void SetVfp(string encoding, InstName name, InstEmitter emitter, MakeOp makeOpA32, MakeOp makeOpT32) @@ -1395,12 +1396,12 @@ namespace ARMeilleure.Decoders private static void SetA64(string encoding, InstName name, InstEmitter emitter, MakeOp makeOp) { - Set(encoding, AllInstA64, new InstDescriptor(name, emitter), makeOp); + Set(encoding, _allInstA64, new InstDescriptor(name, emitter), makeOp); } private static void Set(string encoding, List<InstInfo> list, InstDescriptor inst, MakeOp makeOp) { - int bit = encoding.Length - 1; + int bit = encoding.Length - 1; int value = 0; int xMask = 0; int xBits = 0; @@ -1439,7 +1440,7 @@ namespace ARMeilleure.Decoders } else if (chr != '0') { - throw new ArgumentException(nameof(encoding)); + throw new ArgumentException($"Invalid encoding: {encoding}", nameof(encoding)); } } @@ -1470,17 +1471,17 @@ namespace ARMeilleure.Decoders public static (InstDescriptor inst, MakeOp makeOp) GetInstA32(int opCode) { - return GetInstFromList(InstA32FastLookup[ToFastLookupIndexA(opCode)], opCode); + return GetInstFromList(_instA32FastLookup[ToFastLookupIndexA(opCode)], opCode); } public static (InstDescriptor inst, MakeOp makeOp) GetInstT32(int opCode) { - return GetInstFromList(InstT32FastLookup[ToFastLookupIndexT(opCode)], opCode); + return GetInstFromList(_instT32FastLookup[ToFastLookupIndexT(opCode)], opCode); } public static (InstDescriptor inst, MakeOp makeOp) GetInstA64(int opCode) { - return GetInstFromList(InstA64FastLookup[ToFastLookupIndexA(opCode)], opCode); + return GetInstFromList(_instA64FastLookup[ToFastLookupIndexA(opCode)], opCode); } private static (InstDescriptor inst, MakeOp makeOp) GetInstFromList(InstInfo[] insts, int opCode) diff --git a/src/ARMeilleure/Decoders/Optimizations/TailCallRemover.cs b/src/ARMeilleure/Decoders/Optimizations/TailCallRemover.cs index 17c17812..ff9a6f27 100644 --- a/src/ARMeilleure/Decoders/Optimizations/TailCallRemover.cs +++ b/src/ARMeilleure/Decoders/Optimizations/TailCallRemover.cs @@ -22,10 +22,10 @@ namespace ARMeilleure.Decoders.Optimizations Block entryBlock = blocks[entryBlockId]; Block startBlock = entryBlock; - Block endBlock = entryBlock; + Block endBlock = entryBlock; int startBlockIndex = entryBlockId; - int endBlockIndex = entryBlockId; + int endBlockIndex = entryBlockId; for (int i = entryBlockId + 1; i < blocks.Count; i++) // Search forwards. { @@ -36,7 +36,7 @@ namespace ARMeilleure.Decoders.Optimizations break; // End of contiguous function. } - endBlock = block; + endBlock = block; endBlockIndex = i; } @@ -49,7 +49,7 @@ namespace ARMeilleure.Decoders.Optimizations break; // End of contiguous function. } - startBlock = block; + startBlock = block; startBlockIndex = i; } @@ -57,7 +57,7 @@ namespace ARMeilleure.Decoders.Optimizations { return blocks.ToArray(); // Nothing to do here. } - + // Mark branches whose target is outside of the contiguous region as an exit block. for (int i = startBlockIndex; i <= endBlockIndex; i++) { @@ -69,7 +69,7 @@ namespace ARMeilleure.Decoders.Optimizations } } - var newBlocks = new List<Block>(blocks.Count); + var newBlocks = new List<Block>(blocks.Count); // Finally, rebuild decoded block list, ignoring blocks outside the contiguous range. for (int i = 0; i < blocks.Count; i++) diff --git a/src/ARMeilleure/Decoders/RegisterSize.cs b/src/ARMeilleure/Decoders/RegisterSize.cs index c9cea03e..7c00984e 100644 --- a/src/ARMeilleure/Decoders/RegisterSize.cs +++ b/src/ARMeilleure/Decoders/RegisterSize.cs @@ -5,6 +5,6 @@ namespace ARMeilleure.Decoders Int32, Int64, Simd64, - Simd128 + Simd128, } -}
\ No newline at end of file +} diff --git a/src/ARMeilleure/Decoders/ShiftType.cs b/src/ARMeilleure/Decoders/ShiftType.cs index 8583f16a..43b738f3 100644 --- a/src/ARMeilleure/Decoders/ShiftType.cs +++ b/src/ARMeilleure/Decoders/ShiftType.cs @@ -5,6 +5,6 @@ namespace ARMeilleure.Decoders Lsl = 0, Lsr = 1, Asr = 2, - Ror = 3 + Ror = 3, } -}
\ No newline at end of file +} |