[ARMeilleure] Address dotnet-format issues (#5357)

* dotnet format style --severity info

Some changes were manually reverted.

* dotnet format analyzers --serverity info

Some changes have been minimally adapted.

* Restore a few unused methods and variables

* Silence dotnet format IDE0060 warnings

* Silence dotnet format IDE0052 warnings

* Address or silence dotnet format IDE1006 warnings

* Address or silence dotnet format CA2208 warnings

* Address dotnet format CA1822 warnings

* Address or silence dotnet format CA1069 warnings

* Silence CA1806 and CA1834 issues

* Address dotnet format CA1401 warnings

* Fix new dotnet-format issues after rebase

* Address review comments

* Address dotnet format CA2208 warnings properly

* Fix formatting for switch expressions

* Address most dotnet format whitespace warnings

* Apply dotnet format whitespace formatting

A few of them have been manually reverted and the corresponding warning was silenced

* Add previously silenced warnings back

I have no clue how these disappeared

* Revert formatting changes for OpCodeTable.cs

* Enable formatting for a few cases again

* Format if-blocks correctly

* Enable formatting for a few more cases again

* Fix inline comment alignment

* Run dotnet format after rebase and remove unused usings

- analyzers
- style
- whitespace

* Disable 'prefer switch expression' rule

* Add comments to disabled warnings

* Remove a few unused parameters

* Adjust namespaces

* Simplify properties and array initialization, Use const when possible, Remove trailing commas

* Start working on disabled warnings

* Fix and silence a few dotnet-format warnings again

* Address IDE0251 warnings

* Address a few disabled IDE0060 warnings

* Silence IDE0060 in .editorconfig

* Revert "Simplify properties and array initialization, Use const when possible, Remove trailing commas"

This reverts commit 9462e4136c0a2100dc28b20cf9542e06790aa67e.

* dotnet format whitespace after rebase

* First dotnet format pass

* Remove unnecessary formatting exclusion

* Add unsafe dotnet format changes

* Change visibility of JitSupportDarwin to internal

15 files changed, 201 insertions, 201 deletions

diff --git a/src/ARMeilleure/CodeGen/Arm64/Arm64Optimizer.cs b/src/ARMeilleure/CodeGen/Arm64/Arm64Optimizer.cs
index fdd4d024..00ffd195 100644
--- a/src/ARMeilleure/CodeGen/Arm64/Arm64Optimizer.cs
+++ b/src/ARMeilleure/CodeGen/Arm64/Arm64Optimizer.cs
@@ -221,7 +221,7 @@ namespace ARMeilleure.CodeGen.Arm64
                         2 => Multiplier.x4,
                         3 => Multiplier.x8,
                         4 => Multiplier.x16,
-                        _ => Multiplier.x1
+                        _ => Multiplier.x1,
                     };
 
                     baseOp = indexOnSrc2 ? src1 : src2;
diff --git a/src/ARMeilleure/CodeGen/Arm64/ArmCondition.cs b/src/ARMeilleure/CodeGen/Arm64/ArmCondition.cs
index db27a810..5db89859 100644
--- a/src/ARMeilleure/CodeGen/Arm64/ArmCondition.cs
+++ b/src/ARMeilleure/CodeGen/Arm64/ArmCondition.cs
@@ -5,22 +5,22 @@ namespace ARMeilleure.CodeGen.Arm64
 {
     enum ArmCondition
     {
-        Eq   = 0,
-        Ne   = 1,
+        Eq = 0,
+        Ne = 1,
         GeUn = 2,
         LtUn = 3,
-        Mi   = 4,
-        Pl   = 5,
-        Vs   = 6,
-        Vc   = 7,
+        Mi = 4,
+        Pl = 5,
+        Vs = 6,
+        Vc = 7,
         GtUn = 8,
         LeUn = 9,
-        Ge   = 10,
-        Lt   = 11,
-        Gt   = 12,
-        Le   = 13,
-        Al   = 14,
-        Nv   = 15
+        Ge = 10,
+        Lt = 11,
+        Gt = 12,
+        Le = 13,
+        Al = 14,
+        Nv = 15,
     }
 
     static class ComparisonArm64Extensions
@@ -29,6 +29,7 @@ namespace ARMeilleure.CodeGen.Arm64
         {
             return comp switch
             {
+#pragma warning disable IDE0055 // Disable formatting
                 Comparison.Equal            => ArmCondition.Eq,
                 Comparison.NotEqual         => ArmCondition.Ne,
                 Comparison.Greater          => ArmCondition.Gt,
@@ -39,8 +40,9 @@ namespace ARMeilleure.CodeGen.Arm64
                 Comparison.Less             => ArmCondition.Lt,
                 Comparison.GreaterOrEqualUI => ArmCondition.GeUn,
                 Comparison.LessUI           => ArmCondition.LtUn,
+#pragma warning restore IDE0055
 
-                _ => throw new ArgumentException(null, nameof(comp))
+                _ => throw new ArgumentException(null, nameof(comp)),
             };
         }
     }
diff --git a/src/ARMeilleure/CodeGen/Arm64/ArmExtensionType.cs b/src/ARMeilleure/CodeGen/Arm64/ArmExtensionType.cs
index 062a6d0b..20ccfd4b 100644
--- a/src/ARMeilleure/CodeGen/Arm64/ArmExtensionType.cs
+++ b/src/ARMeilleure/CodeGen/Arm64/ArmExtensionType.cs
@@ -9,6 +9,6 @@ namespace ARMeilleure.CodeGen.Arm64
         Sxtb = 4,
         Sxth = 5,
         Sxtw = 6,
-        Sxtx = 7
+        Sxtx = 7,
     }
 }
diff --git a/src/ARMeilleure/CodeGen/Arm64/ArmShiftType.cs b/src/ARMeilleure/CodeGen/Arm64/ArmShiftType.cs
index d223a146..f32407c4 100644
--- a/src/ARMeilleure/CodeGen/Arm64/ArmShiftType.cs
+++ b/src/ARMeilleure/CodeGen/Arm64/ArmShiftType.cs
@@ -6,6 +6,6 @@ namespace ARMeilleure.CodeGen.Arm64
         Lsl = 0,
         Lsr = 1,
         Asr = 2,
-        Ror = 3
+        Ror = 3,
     }
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/CodeGen/Arm64/Assembler.cs b/src/ARMeilleure/CodeGen/Arm64/Assembler.cs
index 0ec0be7c..41684faf 100644
--- a/src/ARMeilleure/CodeGen/Arm64/Assembler.cs
+++ b/src/ARMeilleure/CodeGen/Arm64/Assembler.cs
@@ -188,7 +188,7 @@ namespace ARMeilleure.CodeGen.Arm64
 
             uint rmode = topHalf ? 1u << 19 : 0u;
             uint ftype = rd.Type == OperandType.FP64 || rn.Type == OperandType.FP64 ? 1u << 22 : 0u;
-            uint sf    = rd.Type == OperandType.I64  || rn.Type == OperandType.I64  ? SfFlag   : 0u;
+            uint sf = rd.Type == OperandType.I64 || rn.Type == OperandType.I64 ? SfFlag : 0u;
 
             WriteUInt32(0x1e260000u | (opcode << 16) | rmode | ftype | sf | EncodeReg(rd) | (EncodeReg(rn) << 5));
         }
@@ -992,7 +992,7 @@ namespace ARMeilleure.CodeGen.Arm64
                 {
                     OperandType.FP32 => 0,
                     OperandType.FP64 => 1,
-                    _ => 2
+                    _ => 2,
                 };
 
                 instruction = vecInst | ((uint)opc << 30);
@@ -1124,10 +1124,11 @@ namespace ARMeilleure.CodeGen.Arm64
                 OperandType.FP32 => 2,
                 OperandType.FP64 => 3,
                 OperandType.V128 => 4,
-                _ => throw new ArgumentException($"Invalid type {type}.")
+                _ => throw new ArgumentException($"Invalid type {type}."),
             };
         }
 
+#pragma warning disable IDE0051 // Remove unused private member
         private void WriteInt16(short value)
         {
             WriteUInt16((ushort)value);
@@ -1142,6 +1143,7 @@ namespace ARMeilleure.CodeGen.Arm64
         {
             _stream.WriteByte(value);
         }
+#pragma warning restore IDE0051
 
         private void WriteUInt16(ushort value)
         {
diff --git a/src/ARMeilleure/CodeGen/Arm64/CallingConvention.cs b/src/ARMeilleure/CodeGen/Arm64/CallingConvention.cs
index fda8d786..a487c2ed 100644
--- a/src/ARMeilleure/CodeGen/Arm64/CallingConvention.cs
+++ b/src/ARMeilleure/CodeGen/Arm64/CallingConvention.cs
@@ -93,4 +93,4 @@ namespace ARMeilleure.CodeGen.Arm64
             return 0;
         }
     }
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/CodeGen/Arm64/CodeGenCommon.cs b/src/ARMeilleure/CodeGen/Arm64/CodeGenCommon.cs
index 8d1e597b..1f0148d5 100644
--- a/src/ARMeilleure/CodeGen/Arm64/CodeGenCommon.cs
+++ b/src/ARMeilleure/CodeGen/Arm64/CodeGenCommon.cs
@@ -88,4 +88,4 @@ namespace ARMeilleure.CodeGen.Arm64
             return true;
         }
     }
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/CodeGen/Arm64/CodeGenContext.cs b/src/ARMeilleure/CodeGen/Arm64/CodeGenContext.cs
index 0dd5355f..12ebabdd 100644
--- a/src/ARMeilleure/CodeGen/Arm64/CodeGenContext.cs
+++ b/src/ARMeilleure/CodeGen/Arm64/CodeGenContext.cs
@@ -14,7 +14,7 @@ namespace ARMeilleure.CodeGen.Arm64
         private const int CbnzInstLength = 4;
         private const int LdrLitInstLength = 4;
 
-        private Stream _stream;
+        private readonly Stream _stream;
 
         public int StreamOffset => (int)_stream.Length;
 
@@ -32,7 +32,7 @@ namespace ARMeilleure.CodeGen.Arm64
         private readonly Dictionary<BasicBlock, long> _visitedBlocks;
         private readonly Dictionary<BasicBlock, List<(ArmCondition Condition, long BranchPos)>> _pendingBranches;
 
-        private struct ConstantPoolEntry
+        private readonly struct ConstantPoolEntry
         {
             public readonly int Offset;
             public readonly Symbol Symbol;
@@ -58,7 +58,7 @@ namespace ARMeilleure.CodeGen.Arm64
 
         private readonly bool _relocatable;
 
-        public CodeGenContext(AllocationResult allocResult, int maxCallArgs, int blocksCount, bool relocatable)
+        public CodeGenContext(AllocationResult allocResult, int maxCallArgs, bool relocatable)
         {
             _stream = MemoryStreamManager.Shared.GetStream();
 
@@ -93,10 +93,10 @@ namespace ARMeilleure.CodeGen.Arm64
 
             if (_pendingBranches.TryGetValue(block, out var list))
             {
-                foreach (var tuple in list)
+                foreach ((ArmCondition condition, long branchPos) in list)
                 {
-                    _stream.Seek(tuple.BranchPos, SeekOrigin.Begin);
-                    WriteBranch(tuple.Condition, target);
+                    _stream.Seek(branchPos, SeekOrigin.Begin);
+                    WriteBranch(condition, target);
                 }
 
                 _stream.Seek(target, SeekOrigin.Begin);
@@ -284,4 +284,4 @@ namespace ARMeilleure.CodeGen.Arm64
             _stream.WriteByte((byte)(value >> 56));
         }
     }
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/CodeGen/Arm64/CodeGenerator.cs b/src/ARMeilleure/CodeGen/Arm64/CodeGenerator.cs
index 92719850..2df86671 100644
--- a/src/ARMeilleure/CodeGen/Arm64/CodeGenerator.cs
+++ b/src/ARMeilleure/CodeGen/Arm64/CodeGenerator.cs
@@ -10,7 +10,6 @@ using System;
 using System.Collections.Generic;
 using System.Diagnostics;
 using System.Numerics;
-
 using static ARMeilleure.IntermediateRepresentation.Operand;
 using static ARMeilleure.IntermediateRepresentation.Operand.Factory;
 
@@ -31,15 +30,16 @@ namespace ARMeilleure.CodeGen.Arm64
         {
             Byte,
             Hword,
-            Auto
+            Auto,
         }
 
-        private static Action<CodeGenContext, Operation>[] _instTable;
+        private static readonly Action<CodeGenContext, Operation>[] _instTable;
 
         static CodeGenerator()
         {
             _instTable = new Action<CodeGenContext, Operation>[EnumUtils.GetCount(typeof(Instruction))];
 
+#pragma warning disable IDE0055 // Disable formatting
             Add(Instruction.Add,                     GenerateAdd);
             Add(Instruction.BitwiseAnd,              GenerateBitwiseAnd);
             Add(Instruction.BitwiseExclusiveOr,      GenerateBitwiseExclusiveOr);
@@ -48,7 +48,7 @@ namespace ARMeilleure.CodeGen.Arm64
             Add(Instruction.BranchIf,                GenerateBranchIf);
             Add(Instruction.ByteSwap,                GenerateByteSwap);
             Add(Instruction.Call,                    GenerateCall);
-            //Add(Instruction.Clobber,                 GenerateClobber);
+            // Add(Instruction.Clobber,                 GenerateClobber);
             Add(Instruction.Compare,                 GenerateCompare);
             Add(Instruction.CompareAndSwap,          GenerateCompareAndSwap);
             Add(Instruction.CompareAndSwap16,        GenerateCompareAndSwap16);
@@ -100,6 +100,7 @@ namespace ARMeilleure.CodeGen.Arm64
             Add(Instruction.ZeroExtend16,            GenerateZeroExtend16);
             Add(Instruction.ZeroExtend32,            GenerateZeroExtend32);
             Add(Instruction.ZeroExtend8,             GenerateZeroExtend8);
+#pragma warning restore IDE0055
 
             static void Add(Instruction inst, Action<CodeGenContext, Operation> func)
             {
@@ -131,7 +132,7 @@ namespace ARMeilleure.CodeGen.Arm64
 
             StackAllocator stackAlloc = new();
 
-            PreAllocator.RunPass(cctx, stackAlloc, out int maxCallArgs);
+            PreAllocator.RunPass(cctx, out int maxCallArgs);
 
             Logger.EndPass(PassName.PreAllocation, cfg);
 
@@ -170,7 +171,7 @@ namespace ARMeilleure.CodeGen.Arm64
 
             bool relocatable = (cctx.Options & CompilerOptions.Relocatable) != 0;
 
-            CodeGenContext context = new(allocResult, maxCallArgs, cfg.Blocks.Count, relocatable);
+            CodeGenContext context = new(allocResult, maxCallArgs, relocatable);
 
             UnwindInfo unwindInfo = WritePrologue(context);
 
@@ -292,7 +293,7 @@ namespace ARMeilleure.CodeGen.Arm64
 
         private static void GenerateBitwiseNot(CodeGenContext context, Operation operation)
         {
-            Operand dest   = operation.Destination;
+            Operand dest = operation.Destination;
             Operand source = operation.GetSource(0);
 
             ValidateUnOp(dest, source);
@@ -330,7 +331,7 @@ namespace ARMeilleure.CodeGen.Arm64
 
         private static void GenerateByteSwap(CodeGenContext context, Operation operation)
         {
-            Operand dest   = operation.Destination;
+            Operand dest = operation.Destination;
             Operand source = operation.GetSource(0);
 
             ValidateUnOp(dest, source);
@@ -364,15 +365,15 @@ namespace ARMeilleure.CodeGen.Arm64
         {
             if (operation.SourcesCount == 5) // CompareAndSwap128 has 5 sources, compared to CompareAndSwap64/32's 3.
             {
-                Operand actualLow    = operation.GetDestination(0);
-                Operand actualHigh   = operation.GetDestination(1);
-                Operand temp0        = operation.GetDestination(2);
-                Operand temp1        = operation.GetDestination(3);
-                Operand address      = operation.GetSource(0);
-                Operand expectedLow  = operation.GetSource(1);
+                Operand actualLow = operation.GetDestination(0);
+                Operand actualHigh = operation.GetDestination(1);
+                Operand temp0 = operation.GetDestination(2);
+                Operand temp1 = operation.GetDestination(3);
+                Operand address = operation.GetSource(0);
+                Operand expectedLow = operation.GetSource(1);
                 Operand expectedHigh = operation.GetSource(2);
-                Operand desiredLow   = operation.GetSource(3);
-                Operand desiredHigh  = operation.GetSource(4);
+                Operand desiredLow = operation.GetSource(3);
+                Operand desiredHigh = operation.GetSource(4);
 
                 GenerateAtomicDcas(
                     context,
@@ -388,11 +389,11 @@ namespace ARMeilleure.CodeGen.Arm64
             }
             else
             {
-                Operand actual   = operation.GetDestination(0);
-                Operand result   = operation.GetDestination(1);
-                Operand address  = operation.GetSource(0);
+                Operand actual = operation.GetDestination(0);
+                Operand result = operation.GetDestination(1);
+                Operand address = operation.GetSource(0);
                 Operand expected = operation.GetSource(1);
-                Operand desired  = operation.GetSource(2);
+                Operand desired = operation.GetSource(2);
 
                 GenerateAtomicCas(context, address, expected, desired, actual, result, AccessSize.Auto);
             }
@@ -400,22 +401,22 @@ namespace ARMeilleure.CodeGen.Arm64
 
         private static void GenerateCompareAndSwap16(CodeGenContext context, Operation operation)
         {
-            Operand actual   = operation.GetDestination(0);
-            Operand result   = operation.GetDestination(1);
-            Operand address  = operation.GetSource(0);
+            Operand actual = operation.GetDestination(0);
+            Operand result = operation.GetDestination(1);
+            Operand address = operation.GetSource(0);
             Operand expected = operation.GetSource(1);
-            Operand desired  = operation.GetSource(2);
+            Operand desired = operation.GetSource(2);
 
             GenerateAtomicCas(context, address, expected, desired, actual, result, AccessSize.Hword);
         }
 
         private static void GenerateCompareAndSwap8(CodeGenContext context, Operation operation)
         {
-            Operand actual   = operation.GetDestination(0);
-            Operand result   = operation.GetDestination(1);
-            Operand address  = operation.GetSource(0);
+            Operand actual = operation.GetDestination(0);
+            Operand result = operation.GetDestination(1);
+            Operand address = operation.GetSource(0);
             Operand expected = operation.GetSource(1);
-            Operand desired  = operation.GetSource(2);
+            Operand desired = operation.GetSource(2);
 
             GenerateAtomicCas(context, address, expected, desired, actual, result, AccessSize.Byte);
         }
@@ -444,13 +445,13 @@ namespace ARMeilleure.CodeGen.Arm64
             Debug.Assert(dest.Type.IsInteger());
             Debug.Assert(src1.Type == OperandType.I32);
 
-            context.Assembler.Cmp (src1, Const(src1.Type, 0));
+            context.Assembler.Cmp(src1, Const(src1.Type, 0));
             context.Assembler.Csel(dest, src2, src3, ArmCondition.Ne);
         }
 
         private static void GenerateConvertI64ToI32(CodeGenContext context, Operation operation)
         {
-            Operand dest   = operation.Destination;
+            Operand dest = operation.Destination;
             Operand source = operation.GetSource(0);
 
             Debug.Assert(dest.Type == OperandType.I32 && source.Type == OperandType.I64);
@@ -460,7 +461,7 @@ namespace ARMeilleure.CodeGen.Arm64
 
         private static void GenerateConvertToFP(CodeGenContext context, Operation operation)
         {
-            Operand dest   = operation.Destination;
+            Operand dest = operation.Destination;
             Operand source = operation.GetSource(0);
 
             Debug.Assert(dest.Type == OperandType.FP32 || dest.Type == OperandType.FP64);
@@ -479,7 +480,7 @@ namespace ARMeilleure.CodeGen.Arm64
 
         private static void GenerateConvertToFPUI(CodeGenContext context, Operation operation)
         {
-            Operand dest   = operation.Destination;
+            Operand dest = operation.Destination;
             Operand source = operation.GetSource(0);
 
             Debug.Assert(dest.Type == OperandType.FP32 || dest.Type == OperandType.FP64);
@@ -491,7 +492,7 @@ namespace ARMeilleure.CodeGen.Arm64
 
         private static void GenerateCopy(CodeGenContext context, Operation operation)
         {
-            Operand dest   = operation.Destination;
+            Operand dest = operation.Destination;
             Operand source = operation.GetSource(0);
 
             EnsureSameType(dest, source);
@@ -523,7 +524,7 @@ namespace ARMeilleure.CodeGen.Arm64
 
         private static void GenerateCountLeadingZeros(CodeGenContext context, Operation operation)
         {
-            Operand dest   = operation.Destination;
+            Operand dest = operation.Destination;
             Operand source = operation.GetSource(0);
 
             EnsureSameType(dest, source);
@@ -535,9 +536,9 @@ namespace ARMeilleure.CodeGen.Arm64
 
         private static void GenerateDivide(CodeGenContext context, Operation operation)
         {
-            Operand dest     = operation.Destination;
+            Operand dest = operation.Destination;
             Operand dividend = operation.GetSource(0);
-            Operand divisor  = operation.GetSource(1);
+            Operand divisor = operation.GetSource(1);
 
             ValidateBinOp(dest, dividend, divisor);
 
@@ -553,9 +554,9 @@ namespace ARMeilleure.CodeGen.Arm64
 
         private static void GenerateDivideUI(CodeGenContext context, Operation operation)
         {
-            Operand dest     = operation.Destination;
+            Operand dest = operation.Destination;
             Operand dividend = operation.GetSource(0);
-            Operand divisor  = operation.GetSource(1);
+            Operand divisor = operation.GetSource(1);
 
             ValidateBinOp(dest, dividend, divisor);
 
@@ -564,7 +565,7 @@ namespace ARMeilleure.CodeGen.Arm64
 
         private static void GenerateLoad(CodeGenContext context, Operation operation)
         {
-            Operand value   = operation.Destination;
+            Operand value = operation.Destination;
             Operand address = operation.GetSource(0);
 
             context.Assembler.Ldr(value, address);
@@ -572,7 +573,7 @@ namespace ARMeilleure.CodeGen.Arm64
 
         private static void GenerateLoad16(CodeGenContext context, Operation operation)
         {
-            Operand value   = operation.Destination;
+            Operand value = operation.Destination;
             Operand address = operation.GetSource(0);
 
             Debug.Assert(value.Type.IsInteger());
@@ -582,7 +583,7 @@ namespace ARMeilleure.CodeGen.Arm64
 
         private static void GenerateLoad8(CodeGenContext context, Operation operation)
         {
-            Operand value   = operation.Destination;
+            Operand value = operation.Destination;
             Operand address = operation.GetSource(0);
 
             Debug.Assert(value.Type.IsInteger());
@@ -641,7 +642,7 @@ namespace ARMeilleure.CodeGen.Arm64
 
         private static void GenerateNegate(CodeGenContext context, Operation operation)
         {
-            Operand dest   = operation.Destination;
+            Operand dest = operation.Destination;
             Operand source = operation.GetSource(0);
 
             ValidateUnOp(dest, source);
@@ -728,7 +729,7 @@ namespace ARMeilleure.CodeGen.Arm64
 
         private static void GenerateSignExtend16(CodeGenContext context, Operation operation)
         {
-            Operand dest   = operation.Destination;
+            Operand dest = operation.Destination;
             Operand source = operation.GetSource(0);
 
             Debug.Assert(dest.Type.IsInteger() && source.Type.IsInteger());
@@ -738,7 +739,7 @@ namespace ARMeilleure.CodeGen.Arm64
 
         private static void GenerateSignExtend32(CodeGenContext context, Operation operation)
         {
-            Operand dest   = operation.Destination;
+            Operand dest = operation.Destination;
             Operand source = operation.GetSource(0);
 
             Debug.Assert(dest.Type.IsInteger() && source.Type.IsInteger());
@@ -748,7 +749,7 @@ namespace ARMeilleure.CodeGen.Arm64
 
         private static void GenerateSignExtend8(CodeGenContext context, Operation operation)
         {
-            Operand dest   = operation.Destination;
+            Operand dest = operation.Destination;
             Operand source = operation.GetSource(0);
 
             Debug.Assert(dest.Type.IsInteger() && source.Type.IsInteger());
@@ -758,7 +759,7 @@ namespace ARMeilleure.CodeGen.Arm64
 
         private static void GenerateFill(CodeGenContext context, Operation operation)
         {
-            Operand dest   = operation.Destination;
+            Operand dest = operation.Destination;
             Operand offset = operation.GetSource(0);
 
             Debug.Assert(offset.Kind == OperandKind.Constant);
@@ -799,7 +800,7 @@ namespace ARMeilleure.CodeGen.Arm64
 
         private static void GenerateStackAlloc(CodeGenContext context, Operation operation)
         {
-            Operand dest   = operation.Destination;
+            Operand dest = operation.Destination;
             Operand offset = operation.GetSource(0);
 
             Debug.Assert(offset.Kind == OperandKind.Constant);
@@ -811,7 +812,7 @@ namespace ARMeilleure.CodeGen.Arm64
 
         private static void GenerateStore(CodeGenContext context, Operation operation)
         {
-            Operand value   = operation.GetSource(1);
+            Operand value = operation.GetSource(1);
             Operand address = operation.GetSource(0);
 
             context.Assembler.Str(value, address);
@@ -819,7 +820,7 @@ namespace ARMeilleure.CodeGen.Arm64
 
         private static void GenerateStore16(CodeGenContext context, Operation operation)
         {
-            Operand value   = operation.GetSource(1);
+            Operand value = operation.GetSource(1);
             Operand address = operation.GetSource(0);
 
             Debug.Assert(value.Type.IsInteger());
@@ -829,7 +830,7 @@ namespace ARMeilleure.CodeGen.Arm64
 
         private static void GenerateStore8(CodeGenContext context, Operation operation)
         {
-            Operand value   = operation.GetSource(1);
+            Operand value = operation.GetSource(1);
             Operand address = operation.GetSource(0);
 
             Debug.Assert(value.Type.IsInteger());
@@ -876,7 +877,7 @@ namespace ARMeilleure.CodeGen.Arm64
 
         private static void GenerateVectorCreateScalar(CodeGenContext context, Operation operation)
         {
-            Operand dest   = operation.Destination;
+            Operand dest = operation.Destination;
             Operand source = operation.GetSource(0);
 
             if (dest != default)
@@ -1022,7 +1023,7 @@ namespace ARMeilleure.CodeGen.Arm64
 
         private static void GenerateVectorZeroUpper64(CodeGenContext context, Operation operation)
         {
-            Operand dest   = operation.Destination;
+            Operand dest = operation.Destination;
             Operand source = operation.GetSource(0);
 
             Debug.Assert(dest.Type == OperandType.V128 && source.Type == OperandType.V128);
@@ -1032,7 +1033,7 @@ namespace ARMeilleure.CodeGen.Arm64
 
         private static void GenerateVectorZeroUpper96(CodeGenContext context, Operation operation)
         {
-            Operand dest   = operation.Destination;
+            Operand dest = operation.Destination;
             Operand source = operation.GetSource(0);
 
             Debug.Assert(dest.Type == OperandType.V128 && source.Type == OperandType.V128);
@@ -1042,7 +1043,7 @@ namespace ARMeilleure.CodeGen.Arm64
 
         private static void GenerateZeroExtend16(CodeGenContext context, Operation operation)
         {
-            Operand dest   = operation.Destination;
+            Operand dest = operation.Destination;
             Operand source = operation.GetSource(0);
 
             Debug.Assert(dest.Type.IsInteger() && source.Type.IsInteger());
@@ -1052,7 +1053,7 @@ namespace ARMeilleure.CodeGen.Arm64
 
         private static void GenerateZeroExtend32(CodeGenContext context, Operation operation)
         {
-            Operand dest   = operation.Destination;
+            Operand dest = operation.Destination;
             Operand source = operation.GetSource(0);
 
             Debug.Assert(dest.Type.IsInteger() && source.Type.IsInteger());
@@ -1068,7 +1069,7 @@ namespace ARMeilleure.CodeGen.Arm64
 
         private static void GenerateZeroExtend8(CodeGenContext context, Operation operation)
         {
-            Operand dest   = operation.Destination;
+            Operand dest = operation.Destination;
             Operand source = operation.GetSource(0);
 
             Debug.Assert(dest.Type.IsInteger() && source.Type.IsInteger());
@@ -1078,7 +1079,7 @@ namespace ARMeilleure.CodeGen.Arm64
 
         private static UnwindInfo WritePrologue(CodeGenContext context)
         {
-            List<UnwindPushEntry> pushEntries = new List<UnwindPushEntry>();
+            List<UnwindPushEntry> pushEntries = new();
 
             Operand rsp = Register(SpRegister);
 
@@ -1568,11 +1569,13 @@ namespace ARMeilleure.CodeGen.Arm64
             Debug.Assert(op1.Type == op3.Type);
         }
 
+#pragma warning disable IDE0051 // Remove unused private member
         private static void EnsureSameType(Operand op1, Operand op2, Operand op3, Operand op4)
         {
             Debug.Assert(op1.Type == op2.Type);
             Debug.Assert(op1.Type == op3.Type);
             Debug.Assert(op1.Type == op4.Type);
         }
+#pragma warning restore IDE0051
     }
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/CodeGen/Arm64/CodeGeneratorIntrinsic.cs b/src/ARMeilleure/CodeGen/Arm64/CodeGeneratorIntrinsic.cs
index 1309404a..b8737055 100644
--- a/src/ARMeilleure/CodeGen/Arm64/CodeGeneratorIntrinsic.cs
+++ b/src/ARMeilleure/CodeGen/Arm64/CodeGeneratorIntrinsic.cs
@@ -688,4 +688,4 @@ namespace ARMeilleure.CodeGen.Arm64
             context.Assembler.WriteInstruction(instruction, rd, rn);
         }
     }
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/CodeGen/Arm64/HardwareCapabilities.cs b/src/ARMeilleure/CodeGen/Arm64/HardwareCapabilities.cs
index 99ff299e..86afc2b4 100644
--- a/src/ARMeilleure/CodeGen/Arm64/HardwareCapabilities.cs
+++ b/src/ARMeilleure/CodeGen/Arm64/HardwareCapabilities.cs
@@ -1,7 +1,4 @@
 using System;
-using System.Linq;
-using System.Reflection;
-using System.Runtime.CompilerServices;
 using System.Runtime.InteropServices;
 using System.Runtime.Intrinsics.Arm;
 using System.Runtime.Versioning;
@@ -35,7 +32,7 @@ namespace ARMeilleure.CodeGen.Arm64
             }
         }
 
-#region Linux
+        #region Linux
 
         private const ulong AT_HWCAP = 16;
         private const ulong AT_HWCAP2 = 26;
@@ -46,88 +43,88 @@ namespace ARMeilleure.CodeGen.Arm64
         [Flags]
         public enum LinuxFeatureFlagsHwCap : ulong
         {
-            Fp        = 1 << 0,
-            Asimd     = 1 << 1,
-            Evtstrm   = 1 << 2,
-            Aes       = 1 << 3,
-            Pmull     = 1 << 4,
-            Sha1      = 1 << 5,
-            Sha2      = 1 << 6,
-            Crc32     = 1 << 7,
-            Atomics   = 1 << 8,
-            FpHp      = 1 << 9,
-            AsimdHp   = 1 << 10,
-            CpuId     = 1 << 11,
-            AsimdRdm  = 1 << 12,
-            Jscvt     = 1 << 13,
-            Fcma      = 1 << 14,
-            Lrcpc     = 1 << 15,
-            DcpOp     = 1 << 16,
-            Sha3      = 1 << 17,
-            Sm3       = 1 << 18,
-            Sm4       = 1 << 19,
-            AsimdDp   = 1 << 20,
-            Sha512    = 1 << 21,
-            Sve       = 1 << 22,
-            AsimdFhm  = 1 << 23,
-            Dit       = 1 << 24,
-            Uscat     = 1 << 25,
-            Ilrcpc    = 1 << 26,
-            FlagM     = 1 << 27,
-            Ssbs      = 1 << 28,
-            Sb        = 1 << 29,
-            Paca      = 1 << 30,
-            Pacg      = 1UL << 31
+            Fp = 1 << 0,
+            Asimd = 1 << 1,
+            Evtstrm = 1 << 2,
+            Aes = 1 << 3,
+            Pmull = 1 << 4,
+            Sha1 = 1 << 5,
+            Sha2 = 1 << 6,
+            Crc32 = 1 << 7,
+            Atomics = 1 << 8,
+            FpHp = 1 << 9,
+            AsimdHp = 1 << 10,
+            CpuId = 1 << 11,
+            AsimdRdm = 1 << 12,
+            Jscvt = 1 << 13,
+            Fcma = 1 << 14,
+            Lrcpc = 1 << 15,
+            DcpOp = 1 << 16,
+            Sha3 = 1 << 17,
+            Sm3 = 1 << 18,
+            Sm4 = 1 << 19,
+            AsimdDp = 1 << 20,
+            Sha512 = 1 << 21,
+            Sve = 1 << 22,
+            AsimdFhm = 1 << 23,
+            Dit = 1 << 24,
+            Uscat = 1 << 25,
+            Ilrcpc = 1 << 26,
+            FlagM = 1 << 27,
+            Ssbs = 1 << 28,
+            Sb = 1 << 29,
+            Paca = 1 << 30,
+            Pacg = 1UL << 31,
         }
 
         [Flags]
         public enum LinuxFeatureFlagsHwCap2 : ulong
         {
-            Dcpodp      = 1 << 0,
-            Sve2        = 1 << 1,
-            SveAes      = 1 << 2,
-            SvePmull    = 1 << 3,
-            SveBitperm  = 1 << 4,
-            SveSha3     = 1 << 5,
-            SveSm4      = 1 << 6,
-            FlagM2      = 1 << 7,
-            Frint       = 1 << 8,
-            SveI8mm     = 1 << 9,
-            SveF32mm    = 1 << 10,
-            SveF64mm    = 1 << 11,
-            SveBf16     = 1 << 12,
-            I8mm        = 1 << 13,
-            Bf16        = 1 << 14,
-            Dgh         = 1 << 15,
-            Rng         = 1 << 16,
-            Bti         = 1 << 17,
-            Mte         = 1 << 18,
-            Ecv         = 1 << 19,
-            Afp         = 1 << 20,
-            Rpres       = 1 << 21,
-            Mte3        = 1 << 22,
-            Sme         = 1 << 23,
-            Sme_i16i64  = 1 << 24,
-            Sme_f64f64  = 1 << 25,
-            Sme_i8i32   = 1 << 26,
-            Sme_f16f32  = 1 << 27,
-            Sme_b16f32  = 1 << 28,
-            Sme_f32f32  = 1 << 29,
-            Sme_fa64    = 1 << 30,
-            Wfxt        = 1UL << 31,
-            Ebf16       = 1UL << 32,
-            Sve_Ebf16   = 1UL << 33,
-            Cssc        = 1UL << 34,
-            Rprfm       = 1UL << 35,
-            Sve2p1      = 1UL << 36
+            Dcpodp = 1 << 0,
+            Sve2 = 1 << 1,
+            SveAes = 1 << 2,
+            SvePmull = 1 << 3,
+            SveBitperm = 1 << 4,
+            SveSha3 = 1 << 5,
+            SveSm4 = 1 << 6,
+            FlagM2 = 1 << 7,
+            Frint = 1 << 8,
+            SveI8mm = 1 << 9,
+            SveF32mm = 1 << 10,
+            SveF64mm = 1 << 11,
+            SveBf16 = 1 << 12,
+            I8mm = 1 << 13,
+            Bf16 = 1 << 14,
+            Dgh = 1 << 15,
+            Rng = 1 << 16,
+            Bti = 1 << 17,
+            Mte = 1 << 18,
+            Ecv = 1 << 19,
+            Afp = 1 << 20,
+            Rpres = 1 << 21,
+            Mte3 = 1 << 22,
+            Sme = 1 << 23,
+            Sme_i16i64 = 1 << 24,
+            Sme_f64f64 = 1 << 25,
+            Sme_i8i32 = 1 << 26,
+            Sme_f16f32 = 1 << 27,
+            Sme_b16f32 = 1 << 28,
+            Sme_f32f32 = 1 << 29,
+            Sme_fa64 = 1 << 30,
+            Wfxt = 1UL << 31,
+            Ebf16 = 1UL << 32,
+            Sve_Ebf16 = 1UL << 33,
+            Cssc = 1UL << 34,
+            Rprfm = 1UL << 35,
+            Sve2p1 = 1UL << 36,
         }
 
         public static LinuxFeatureFlagsHwCap LinuxFeatureInfoHwCap { get; } = 0;
         public static LinuxFeatureFlagsHwCap2 LinuxFeatureInfoHwCap2 { get; } = 0;
 
-#endregion
+        #endregion
 
-#region macOS
+        #region macOS
 
         [LibraryImport("libSystem.dylib", SetLastError = true)]
         private static unsafe partial int sysctlbyname([MarshalAs(UnmanagedType.LPStr)] string name, out int oldValue, ref ulong oldSize, IntPtr newValue, ulong newValueSize);
@@ -143,7 +140,7 @@ namespace ARMeilleure.CodeGen.Arm64
             return false;
         }
 
-        private static string[] _sysctlNames = new string[]
+        private static readonly string[] _sysctlNames = new string[]
         {
             "hw.optional.floatingpoint",
             "hw.optional.AdvSIMD",
@@ -153,26 +150,26 @@ namespace ARMeilleure.CodeGen.Arm64
             "hw.optional.arm.FEAT_LSE",
             "hw.optional.armv8_crc32",
             "hw.optional.arm.FEAT_SHA1",
-            "hw.optional.arm.FEAT_SHA256"
+            "hw.optional.arm.FEAT_SHA256",
         };
 
         [Flags]
         public enum MacOsFeatureFlags
         {
-            Fp      = 1 << 0,
+            Fp = 1 << 0,
             AdvSimd = 1 << 1,
-            Fp16    = 1 << 2,
-            Aes     = 1 << 3,
-            Pmull   = 1 << 4,
-            Lse     = 1 << 5,
-            Crc32   = 1 << 6,
-            Sha1    = 1 << 7,
-            Sha256  = 1 << 8
+            Fp16 = 1 << 2,
+            Aes = 1 << 3,
+            Pmull = 1 << 4,
+            Lse = 1 << 5,
+            Crc32 = 1 << 6,
+            Sha1 = 1 << 7,
+            Sha256 = 1 << 8,
         }
 
         public static MacOsFeatureFlags MacOsFeatureInfo { get; } = 0;
 
-#endregion
+        #endregion
 
         public static bool SupportsAdvSimd => LinuxFeatureInfoHwCap.HasFlag(LinuxFeatureFlagsHwCap.Asimd) || MacOsFeatureInfo.HasFlag(MacOsFeatureFlags.AdvSimd);
         public static bool SupportsAes => LinuxFeatureInfoHwCap.HasFlag(LinuxFeatureFlagsHwCap.Aes) || MacOsFeatureInfo.HasFlag(MacOsFeatureFlags.Aes);
diff --git a/src/ARMeilleure/CodeGen/Arm64/IntrinsicInfo.cs b/src/ARMeilleure/CodeGen/Arm64/IntrinsicInfo.cs
index 8695db90..956fc778 100644
--- a/src/ARMeilleure/CodeGen/Arm64/IntrinsicInfo.cs
+++ b/src/ARMeilleure/CodeGen/Arm64/IntrinsicInfo.cs
@@ -1,8 +1,8 @@
 namespace ARMeilleure.CodeGen.Arm64
 {
-    struct IntrinsicInfo
+    readonly struct IntrinsicInfo
     {
-        public uint          Inst { get; }
+        public uint Inst { get; }
         public IntrinsicType Type { get; }
 
         public IntrinsicInfo(uint inst, IntrinsicType type)
@@ -11,4 +11,4 @@ namespace ARMeilleure.CodeGen.Arm64
             Type = type;
         }
     }
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/CodeGen/Arm64/IntrinsicTable.cs b/src/ARMeilleure/CodeGen/Arm64/IntrinsicTable.cs
index c2bd0bd5..dbd5bdd1 100644
--- a/src/ARMeilleure/CodeGen/Arm64/IntrinsicTable.cs
+++ b/src/ARMeilleure/CodeGen/Arm64/IntrinsicTable.cs
@@ -5,12 +5,13 @@ namespace ARMeilleure.CodeGen.Arm64
 {
     static class IntrinsicTable
     {
-        private static IntrinsicInfo[] _intrinTable;
+        private static readonly IntrinsicInfo[] _intrinTable;
 
         static IntrinsicTable()
         {
             _intrinTable = new IntrinsicInfo[EnumUtils.GetCount(typeof(Intrinsic))];
 
+#pragma warning disable IDE0055 // Disable formatting
             Add(Intrinsic.Arm64AbsS,          new IntrinsicInfo(0x5e20b800u, IntrinsicType.ScalarUnary));
             Add(Intrinsic.Arm64AbsV,          new IntrinsicInfo(0x0e20b800u, IntrinsicType.VectorUnary));
             Add(Intrinsic.Arm64AddhnV,        new IntrinsicInfo(0x0e204000u, IntrinsicType.VectorTernaryRd));
@@ -448,6 +449,7 @@ namespace ARMeilleure.CodeGen.Arm64
             Add(Intrinsic.Arm64XtnV,          new IntrinsicInfo(0x0e212800u, IntrinsicType.VectorUnary));
             Add(Intrinsic.Arm64Zip1V,         new IntrinsicInfo(0x0e003800u, IntrinsicType.VectorBinary));
             Add(Intrinsic.Arm64Zip2V,         new IntrinsicInfo(0x0e007800u, IntrinsicType.VectorBinary));
+#pragma warning restore IDE0055
         }
 
         private static void Add(Intrinsic intrin, IntrinsicInfo info)
@@ -460,4 +462,4 @@ namespace ARMeilleure.CodeGen.Arm64
             return _intrinTable[(int)intrin];
         }
     }
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/CodeGen/Arm64/IntrinsicType.cs b/src/ARMeilleure/CodeGen/Arm64/IntrinsicType.cs
index df61ea1e..7538575c 100644
--- a/src/ARMeilleure/CodeGen/Arm64/IntrinsicType.cs
+++ b/src/ARMeilleure/CodeGen/Arm64/IntrinsicType.cs
@@ -55,6 +55,6 @@ namespace ARMeilleure.CodeGen.Arm64
         VectorTernaryShrRd,
 
         GetRegister,
-        SetRegister
+        SetRegister,
     }
-}
\ No newline at end of file
+}
diff --git a/src/ARMeilleure/CodeGen/Arm64/PreAllocator.cs b/src/ARMeilleure/CodeGen/Arm64/PreAllocator.cs
index 74f80e0f..f66bb66e 100644
--- a/src/ARMeilleure/CodeGen/Arm64/PreAllocator.cs
+++ b/src/ARMeilleure/CodeGen/Arm64/PreAllocator.cs
@@ -1,4 +1,3 @@
-using ARMeilleure.CodeGen.RegisterAllocators;
 using ARMeilleure.IntermediateRepresentation;
 using ARMeilleure.Translation;
 using System;
@@ -31,7 +30,7 @@ namespace ARMeilleure.CodeGen.Arm64
             }
         }
 
-        public static void RunPass(CompilerContext cctx, StackAllocator stackAlloc, out int maxCallArgs)
+        public static void RunPass(CompilerContext cctx, out int maxCallArgs)
         {
             maxCallArgs = -1;
 
@@ -41,7 +40,7 @@ namespace ARMeilleure.CodeGen.Arm64
 
             for (BasicBlock block = cctx.Cfg.Blocks.First; block != null; block = block.ListNext)
             {
-                ConstantDict constants = new ConstantDict();
+                ConstantDict constants = new();
 
                 Operation nextNode;
 
@@ -92,7 +91,7 @@ namespace ARMeilleure.CodeGen.Arm64
                             InsertReturnCopy(block.Operations, node);
                             break;
                         case Instruction.Tailcall:
-                            InsertTailcallCopies(constants, block.Operations, stackAlloc, node, node);
+                            InsertTailcallCopies(constants, block.Operations, node, node);
                             break;
                     }
                 }
@@ -138,10 +137,7 @@ namespace ARMeilleure.CodeGen.Arm64
                     {
                         src2 = node.GetSource(1);
 
-                        Operand temp = src1;
-
-                        src1 = src2;
-                        src2 = temp;
+                        (src2, src1) = (src1, src2);
 
                         node.SetSource(0, src1);
                         node.SetSource(1, src2);
@@ -265,9 +261,9 @@ namespace ARMeilleure.CodeGen.Arm64
 
             Operand dest = operation.Destination;
 
-            List<Operand> sources = new List<Operand>
+            List<Operand> sources = new()
             {
-                operation.GetSource(0)
+                operation.GetSource(0),
             };
 
             int argsCount = operation.SourcesCount - 1;
@@ -302,10 +298,10 @@ namespace ARMeilleure.CodeGen.Arm64
                 if (source.Type == OperandType.V128 && passOnReg)
                 {
                     // V128 is a struct, we pass each half on a GPR if possible.
-                    Operand argReg  = Gpr(CallingConvention.GetIntArgumentRegister(intCount++), OperandType.I64);
+                    Operand argReg = Gpr(CallingConvention.GetIntArgumentRegister(intCount++), OperandType.I64);
                     Operand argReg2 = Gpr(CallingConvention.GetIntArgumentRegister(intCount++), OperandType.I64);
 
-                    nodes.AddBefore(node, Operation(Instruction.VectorExtract, argReg,  source, Const(0)));
+                    nodes.AddBefore(node, Operation(Instruction.VectorExtract, argReg, source, Const(0)));
                     nodes.AddBefore(node, Operation(Instruction.VectorExtract, argReg2, source, Const(1)));
 
                     continue;
@@ -339,7 +335,7 @@ namespace ARMeilleure.CodeGen.Arm64
             {
                 if (dest.Type == OperandType.V128)
                 {
-                    Operand retLReg = Gpr(CallingConvention.GetIntReturnRegister(),     OperandType.I64);
+                    Operand retLReg = Gpr(CallingConvention.GetIntReturnRegister(), OperandType.I64);
                     Operand retHReg = Gpr(CallingConvention.GetIntReturnRegisterHigh(), OperandType.I64);
 
                     node = nodes.AddAfter(node, Operation(Instruction.VectorCreateScalar, dest, retLReg));
@@ -364,16 +360,14 @@ namespace ARMeilleure.CodeGen.Arm64
             operation.SetSources(sources.ToArray());
         }
 
-        private static void InsertTailcallCopies(
-            ConstantDict constants,
+        private static void InsertTailcallCopies(ConstantDict constants,
             IntrusiveList<Operation> nodes,
-            StackAllocator stackAlloc,
             Operation node,
             Operation operation)
         {
-            List<Operand> sources = new List<Operand>
+            List<Operand> sources = new()
             {
-                operation.GetSource(0)
+                operation.GetSource(0),
             };
 
             int argsCount = operation.SourcesCount - 1;
@@ -403,7 +397,7 @@ namespace ARMeilleure.CodeGen.Arm64
                 if (source.Type == OperandType.V128 && passOnReg)
                 {
                     // V128 is a struct, we pass each half on a GPR if possible.
-                    Operand argReg  = Gpr(CallingConvention.GetIntArgumentRegister(intCount++), OperandType.I64);
+                    Operand argReg = Gpr(CallingConvention.GetIntArgumentRegister(intCount++), OperandType.I64);
                     Operand argReg2 = Gpr(CallingConvention.GetIntArgumentRegister(intCount++), OperandType.I64);
 
                     nodes.AddBefore(node, Operation(Instruction.VectorExtract, argReg, source, Const(0)));
@@ -519,7 +513,7 @@ namespace ARMeilleure.CodeGen.Arm64
 
             if (source.Type == OperandType.V128)
             {
-                Operand retLReg = Gpr(CallingConvention.GetIntReturnRegister(),     OperandType.I64);
+                Operand retLReg = Gpr(CallingConvention.GetIntReturnRegister(), OperandType.I64);
                 Operand retHReg = Gpr(CallingConvention.GetIntReturnRegisterHigh(), OperandType.I64);
 
                 nodes.AddBefore(node, Operation(Instruction.VectorExtract, retLReg, source, Const(0)));