Add SSAT, SSAT16, USAT and USAT16 ARM32 instructions (#954)

* Implement SMULWB, SMULWT, SMLAWB, SMLAWT, and add tests for some multiply instructions

* Improve test descriptions

* Rename SMULH to SMUL__

* Add SSAT, SSAT16, USAT and USAT16 ARM32 instructions

* Fix new tests

* Replace AND 0xFFFF with 16-bits zero extension (more efficient)

3 files changed, 197 insertions, 1 deletions

diff --git a/Ryujinx.Tests/Cpu/CpuTest32.cs b/Ryujinx.Tests/Cpu/CpuTest32.cs
index ed1d23d3..a039d280 100644
--- a/Ryujinx.Tests/Cpu/CpuTest32.cs
+++ b/Ryujinx.Tests/Cpu/CpuTest32.cs
@@ -348,6 +348,7 @@ namespace Ryujinx.Tests.Cpu
 
             Assert.That((int)_context.Fpcr | ((int)_context.Fpsr & (int)fpsrMask), Is.EqualTo(_unicornEmu.Fpscr));
 
+            Assert.That(_context.GetPstateFlag(PState.QFlag), Is.EqualTo(_unicornEmu.QFlag));
             Assert.That(_context.GetPstateFlag(PState.VFlag), Is.EqualTo(_unicornEmu.OverflowFlag));
             Assert.That(_context.GetPstateFlag(PState.CFlag), Is.EqualTo(_unicornEmu.CarryFlag));
             Assert.That(_context.GetPstateFlag(PState.ZFlag), Is.EqualTo(_unicornEmu.ZeroFlag));
@@ -358,7 +359,7 @@ namespace Ryujinx.Tests.Cpu
                 byte[] meilleureMem = _memory.ReadBytes((long)(0x2000), _size);
                 byte[] unicornMem = _unicornEmu.MemoryRead((ulong)(0x2000), (ulong)_size);
 
-                for (int i = 0; i < _size; i++) 
+                for (int i = 0; i < _size; i++)
                 {
                     Assert.AreEqual(meilleureMem[i], unicornMem[i]);
                 }
diff --git a/Ryujinx.Tests/Cpu/CpuTestAlu32.cs b/Ryujinx.Tests/Cpu/CpuTestAlu32.cs
index 145417ae..c21bbe10 100644
--- a/Ryujinx.Tests/Cpu/CpuTestAlu32.cs
+++ b/Ryujinx.Tests/Cpu/CpuTestAlu32.cs
@@ -11,6 +11,26 @@ namespace Ryujinx.Tests.Cpu
 #if Alu32
 
 #region "ValueSource (Opcodes)"
+        private static uint[] _Ssat_Usat_()
+        {
+            return new uint[]
+            {
+                0xe6a00010u, // SSAT R0, #1, R0, LSL #0
+                0xe6a00050u, // SSAT R0, #1, R0, ASR #32
+                0xe6e00010u, // USAT R0, #0, R0, LSL #0
+                0xe6e00050u  // USAT R0, #0, R0, ASR #32
+            };
+        }
+
+        private static uint[] _Ssat16_Usat16_()
+        {
+            return new uint[]
+            {
+                0xe6a00f30u, // SSAT16 R0, #1, R0
+                0xe6e00f30u, // USAT16 R0, #0, R0
+            };
+        }
+
         private static uint[] _Lsr_Lsl_Asr_Ror_()
         {
             return new uint[]
@@ -56,6 +76,41 @@ namespace Ryujinx.Tests.Cpu
 
             CompareAgainstUnicorn();
         }
+
+        [Test, Pairwise]
+        public void Ssat_Usat([ValueSource("_Ssat_Usat_")] uint opcode,
+                              [Values(0u, 0xdu)] uint rd,
+                              [Values(1u, 0xdu)] uint rn,
+                              [Values(0u, 7u, 8u, 0xfu, 0x10u, 0x1fu)] uint sat,
+                              [Values(0u, 7u, 8u, 0xfu, 0x10u, 0x1fu)] uint shift,
+                              [Values(0x00000000u, 0x7FFFFFFFu,
+                                      0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn)
+        {
+            opcode |= ((rn & 15) << 0) | ((shift & 31) << 7) | ((rd & 15) << 12) | ((sat & 31) << 16);
+
+            uint w31 = TestContext.CurrentContext.Random.NextUInt();
+
+            SingleOpcode(opcode, r1: wn, sp: w31);
+
+            CompareAgainstUnicorn();
+        }
+
+        [Test, Pairwise]
+        public void Ssat16_Usat16([ValueSource("_Ssat16_Usat16_")] uint opcode,
+                                  [Values(0u, 0xdu)] uint rd,
+                                  [Values(1u, 0xdu)] uint rn,
+                                  [Values(0u, 7u, 8u, 0xfu)] uint sat,
+                                  [Values(0x00000000u, 0x7FFFFFFFu,
+                                          0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn)
+        {
+            opcode |= ((rn & 15) << 0) | ((rd & 15) << 12) | ((sat & 15) << 16);
+
+            uint w31 = TestContext.CurrentContext.Random.NextUInt();
+
+            SingleOpcode(opcode, r1: wn, sp: w31);
+
+            CompareAgainstUnicorn();
+        }
 #endif
     }
 }
diff --git a/Ryujinx.Tests/Cpu/CpuTestMul32.cs b/Ryujinx.Tests/Cpu/CpuTestMul32.cs
new file mode 100644
index 00000000..4bdb2ae2
--- /dev/null
+++ b/Ryujinx.Tests/Cpu/CpuTestMul32.cs
@@ -0,0 +1,140 @@
+#define Mul32
+
+using NUnit.Framework;
+using System;
+
+namespace Ryujinx.Tests.Cpu
+{
+    [Category("Mul32")]
+    public sealed class CpuTestMul32 : CpuTest32
+    {
+#if Mul32
+
+#region "ValueSource (Opcodes)"
+        private static uint[] _Smlabb_Smlabt_Smlatb_Smlatt_()
+        {
+            return new uint[]
+            {
+                0xe1000080u, // SMLABB R0, R0, R0, R0
+                0xe10000C0u, // SMLABT R0, R0, R0, R0
+                0xe10000A0u, // SMLATB R0, R0, R0, R0
+                0xe10000E0u, // SMLATT R0, R0, R0, R0
+            };
+        }
+
+        private static uint[] _Smlawb_Smlawt_()
+        {
+            return new uint[]
+            {
+                0xe1200080u, // SMLAWB R0, R0, R0, R0
+                0xe12000C0u, // SMLAWT R0, R0, R0, R0
+            };
+        }
+
+        private static uint[] _Smulbb_Smulbt_Smultb_Smultt_()
+        {
+            return new uint[]
+            {
+                0xe1600080u, // SMULBB R0, R0, R0
+                0xe16000C0u, // SMULBT R0, R0, R0
+                0xe16000A0u, // SMULTB R0, R0, R0
+                0xe16000E0u, // SMULTT R0, R0, R0
+            };
+        }
+
+        private static uint[] _Smulwb_Smulwt_()
+        {
+            return new uint[]
+            {
+                0xe12000a0u, // SMULWB R0, R0, R0
+                0xe12000e0u, // SMULWT R0, R0, R0
+            };
+        }
+#endregion
+
+        private const int RndCnt = 2;
+
+        [Test, Pairwise, Description("SMLA<x><y> <Rd>, <Rn>, <Rm>, <Ra>")]
+        public void Smla___32bit([ValueSource("_Smlabb_Smlabt_Smlatb_Smlatt_")] uint opcode,
+                                 [Values(0u, 0xdu)] uint rn,
+                                 [Values(1u, 0xdu)] uint rm,
+                                 [Values(2u, 0xdu)] uint ra,
+                                 [Values(3u, 0xdu)] uint rd,
+                                 [Values(0x00000000u, 0x7FFFFFFFu,
+                                         0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
+                                 [Values(0x00000000u, 0x7FFFFFFFu,
+                                         0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm,
+                                 [Values(0x00000000u, 0x7FFFFFFFu,
+                                         0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wa)
+        {
+            opcode |= ((rn & 15) << 0) | ((rm & 15) << 8) | ((ra & 15) << 12) | ((rd & 15) << 16);
+
+            uint w31 = TestContext.CurrentContext.Random.NextUInt();
+
+            SingleOpcode(opcode, r0: wn, r1: wm, r2: wa, sp: w31);
+
+            CompareAgainstUnicorn();
+        }
+
+        [Test, Pairwise, Description("SMLAW<x> <Rd>, <Rn>, <Rm>, <Ra>")]
+        public void Smlaw__32bit([ValueSource("_Smlawb_Smlawt_")] uint opcode,
+                                 [Values(0u, 0xdu)] uint rn,
+                                 [Values(1u, 0xdu)] uint rm,
+                                 [Values(2u, 0xdu)] uint ra,
+                                 [Values(3u, 0xdu)] uint rd,
+                                 [Values(0x00000000u, 0x7FFFFFFFu,
+                                         0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
+                                 [Values(0x00000000u, 0x7FFFFFFFu,
+                                         0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm,
+                                 [Values(0x00000000u, 0x7FFFFFFFu,
+                                         0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wa)
+        {
+            opcode |= ((rn & 15) << 0) | ((rm & 15) << 8) | ((ra & 15) << 12) | ((rd & 15) << 16);
+
+            uint w31 = TestContext.CurrentContext.Random.NextUInt();
+
+            SingleOpcode(opcode, r0: wn, r1: wm, r2: wa, sp: w31);
+
+            CompareAgainstUnicorn();
+        }
+
+        [Test, Pairwise, Description("SMUL<x><y> <Rd>, <Rn>, <Rm>")]
+        public void Smul___32bit([ValueSource("_Smulbb_Smulbt_Smultb_Smultt_")] uint opcode,
+                                 [Values(0u, 0xdu)] uint rn,
+                                 [Values(1u, 0xdu)] uint rm,
+                                 [Values(2u, 0xdu)] uint rd,
+                                 [Values(0x00000000u, 0x7FFFFFFFu,
+                                         0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
+                                 [Values(0x00000000u, 0x7FFFFFFFu,
+                                         0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm)
+        {
+            opcode |= ((rn & 15) << 0) | ((rm & 15) << 8) | ((rd & 15) << 16);
+
+            uint w31 = TestContext.CurrentContext.Random.NextUInt();
+
+            SingleOpcode(opcode, r0: wn, r1: wm, sp: w31);
+
+            CompareAgainstUnicorn();
+        }
+
+        [Test, Pairwise, Description("SMULW<x> <Rd>, <Rn>, <Rm>")]
+        public void Smulw__32bit([ValueSource("_Smulwb_Smulwt_")] uint opcode,
+                                 [Values(0u, 0xdu)] uint rn,
+                                 [Values(1u, 0xdu)] uint rm,
+                                 [Values(2u, 0xdu)] uint rd,
+                                 [Values(0x00000000u, 0x7FFFFFFFu,
+                                         0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wn,
+                                 [Values(0x00000000u, 0x7FFFFFFFu,
+                                         0x80000000u, 0xFFFFFFFFu)] [Random(RndCnt)] uint wm)
+        {
+            opcode |= ((rn & 15) << 0) | ((rm & 15) << 8) | ((rd & 15) << 16);
+
+            uint w31 = TestContext.CurrentContext.Random.NextUInt();
+
+            SingleOpcode(opcode, r0: wn, r1: wm, sp: w31);
+
+            CompareAgainstUnicorn();
+        }
+#endif
+    }
+}