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| author | gdkchan <gab.dark.100@gmail.com> | 2020-03-10 02:17:30 -0300 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-03-10 16:17:30 +1100 |
| commit | 89ccec197ec9a5db2bb308ef3e9178910d1ab7a8 (patch) | |
| tree | 3f487a86d3495feefd904d4cd7195d9c798c008b /Ryujinx.Tests | |
| parent | 08c0e3829bc96932d386de18647bde2768fe26ed (diff) | |
Implement VMOVL and VORR.I32 AArch32 SIMD instructions (#960)
* Implement VMOVL and VORR.I32 AArch32 SIMD instructions
* Rename <dt> to <size> on test description
* Rename Widen to Long and improve VMOVL implementation a bit
Diffstat (limited to 'Ryujinx.Tests')
| -rw-r--r-- | Ryujinx.Tests/Cpu/CpuTestSimdLogical32.cs | 28 | ||||
| -rw-r--r-- | Ryujinx.Tests/Cpu/CpuTestSimdMov32.cs | 30 |
2 files changed, 58 insertions, 0 deletions
diff --git a/Ryujinx.Tests/Cpu/CpuTestSimdLogical32.cs b/Ryujinx.Tests/Cpu/CpuTestSimdLogical32.cs index dfbd3b0b..459127de 100644 --- a/Ryujinx.Tests/Cpu/CpuTestSimdLogical32.cs +++ b/Ryujinx.Tests/Cpu/CpuTestSimdLogical32.cs @@ -56,6 +56,34 @@ namespace Ryujinx.Tests.Cpu CompareAgainstUnicorn(); } + + [Test, Pairwise, Description("VORR.I32 <Vd>, #<imm>")] + public void Vorr_II([Range(0u, 4u)] uint rd, + [Random(RndCnt)] ulong z, + [Random(RndCnt)] byte imm, + [Values(0u, 1u, 2u, 3u)] uint cMode, + [Values] bool q) + { + uint opcode = 0xf2800110u; // VORR.I32 D0, #0 + + if (q) + { + opcode |= 1 << 6; + rd <<= 1; + } + + opcode |= (uint)(imm & 0xf) << 0; + opcode |= (uint)(imm & 0x70) << 12; + opcode |= (uint)(imm & 0x80) << 17; + opcode |= (cMode & 0x3) << 9; + opcode |= ((rd & 0xf) << 12) | ((rd & 0x10) << 18); + + V128 v0 = MakeVectorE0E1(z, z); + + SingleOpcode(opcode, v0: v0); + + CompareAgainstUnicorn(); + } #endif } } diff --git a/Ryujinx.Tests/Cpu/CpuTestSimdMov32.cs b/Ryujinx.Tests/Cpu/CpuTestSimdMov32.cs index 13d61078..8c9627ce 100644 --- a/Ryujinx.Tests/Cpu/CpuTestSimdMov32.cs +++ b/Ryujinx.Tests/Cpu/CpuTestSimdMov32.cs @@ -228,6 +228,36 @@ namespace Ryujinx.Tests.Cpu CompareAgainstUnicorn(); } + [Test, Pairwise, Description("VMOVL.<size> <Qd>, <Dm>")] + public void Vmovl([Values(0u, 1u, 2u, 3u)] uint vm, + [Values(0u, 2u, 4u, 6u)] uint vd, + [Values(1u, 2u, 4u)] uint imm3H, + [Values] bool u) + { + // This is not VMOVL because imm3H = 0, but once + // we shift in the imm3H value it turns into VMOVL. + uint opcode = 0xf2800a10u; // VMOV.I16 D0, #0 + + opcode |= (vm & 0x10) << 1; + opcode |= (vm & 0xf); + opcode |= (vd & 0x10) << 18; + opcode |= (vd & 0xf) << 12; + opcode |= (imm3H & 0x7) << 19; + if (u) + { + opcode |= 1 << 24; + } + + V128 v0 = new V128(TestContext.CurrentContext.Random.NextULong(), TestContext.CurrentContext.Random.NextULong()); + V128 v1 = new V128(TestContext.CurrentContext.Random.NextULong(), TestContext.CurrentContext.Random.NextULong()); + V128 v2 = new V128(TestContext.CurrentContext.Random.NextULong(), TestContext.CurrentContext.Random.NextULong()); + V128 v3 = new V128(TestContext.CurrentContext.Random.NextULong(), TestContext.CurrentContext.Random.NextULong()); + + SingleOpcode(opcode, v0: v0, v1: v1, v2: v2, v3: v3); + + CompareAgainstUnicorn(); + } + [Test, Pairwise, Description("VTRN.<size> <Vd>, <Vm>")] public void Vtrn([Values(0u, 1u, 2u, 3u)] uint vm, [Values(0u, 1u, 2u, 3u)] uint vd, |