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| author | sharmander <saldabain.dev@gmail.com> | 2020-12-07 19:04:01 -0500 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-12-07 21:04:01 -0300 |
| commit | 36f6bbf5b9082193abb33b26e654ce973ed0ee83 (patch) | |
| tree | 449fbcf3c45554acdd1398ad16fdfe649c11ee32 /Ryujinx.Tests | |
| parent | 567ea726e173040ae931a37bc85fd6cd92b69363 (diff) | |
CPU: Implement VFNMA.F32 | F.64 (#1783)
* Implement VFNMA.F<32/64>
* Update PTC Version
* Update Implementation & Renames & Correct Order
* Fix alignment
* Update implementation to not trigger assert
* Actually use the intrinsic that makes sense :)
Diffstat (limited to 'Ryujinx.Tests')
| -rw-r--r-- | Ryujinx.Tests/Cpu/CpuTestSimdReg32.cs | 35 |
1 files changed, 35 insertions, 0 deletions
diff --git a/Ryujinx.Tests/Cpu/CpuTestSimdReg32.cs b/Ryujinx.Tests/Cpu/CpuTestSimdReg32.cs index 1b9b38ab..dc5903d5 100644 --- a/Ryujinx.Tests/Cpu/CpuTestSimdReg32.cs +++ b/Ryujinx.Tests/Cpu/CpuTestSimdReg32.cs @@ -293,6 +293,41 @@ namespace Ryujinx.Tests.Cpu CompareAgainstUnicorn(fpsrMask: Fpsr.Nzcv); } + [Test, Pairwise, Description("VFNMA.F<size> <Vd>, <Vn>, <Vm>")] + public void Vfnma([Values(0u, 1u)] uint rd, + [Values(0u, 1u)] uint rn, + [Values(0u, 1u)] uint rm, + [Values(2u, 3u)] uint size, + [ValueSource("_2S_F_")] ulong z, + [ValueSource("_2S_F_")] ulong a, + [ValueSource("_2S_F_")] ulong b) + { + uint opcode = 0xe900840; + + if (size == 2) + { + opcode |= (((rm & 0x1) << 5) | (rm & 0x1e) >> 1); + opcode |= (((rd & 0x1) << 22) | (rd & 0x1e) << 11); + opcode |= (((rn & 0x1) << 7) | (rn & 0x1e) >> 15); + + } + else + { + opcode |= (((rm & 0x10) << 1) | (rm & 0xf) << 0); + opcode |= (((rd & 0x10) << 18) | (rd & 0xf) << 12); + opcode |= (((rn & 0x10) << 3) | (rn & 0xf) << 16); + } + + opcode |= ((size & 3) << 8); + + V128 v0 = MakeVectorE0E1(z, z); + V128 v1 = MakeVectorE0E1(a, z); + V128 v2 = MakeVectorE0E1(b, z); + + SingleOpcode(opcode, v0: v0, v1: v1, v2: v2); + CompareAgainstUnicorn(); + } + [Test, Pairwise, Description("VFNMS.F<size> <Vd>, <Vn>, <Vm>")] public void Vfnms([Values(0u, 1u)] uint rd, [Values(0u, 1u)] uint rn, |