Fix/Add 1+12 [Saturating] [Rounded] Shift Right Narrow (imm.) Instructions; add 14 Tests. Add 6 Tests for PR#405. Add 2 Tests for PR#412. (#409)

* Update AOpCodeTable.cs

* Update AInstEmitSimdShift.cs

* Update CpuTestSimdShImm.cs

* Update AInstEmitSimdArithmetic.cs

* Update AInstEmitSimdHelper.cs

* Create CpuTestSimdIns.cs

* Update CpuTest.cs

* Update CpuTestSimd.cs

* Update CpuTestSimdReg.cs

* Update CpuTest.cs

* Update CpuTestSimd.cs

* Update CpuTestSimdReg.cs

* Update CpuTestSimd.cs

* Update CpuTestSimdReg.cs

* Update CpuTest.cs

* Update CpuTestSimdReg.cs

* Update CpuTestSimd.cs

1 files changed, 318 insertions, 0 deletions

diff --git a/Ryujinx.Tests/Cpu/CpuTestSimdShImm.cs b/Ryujinx.Tests/Cpu/CpuTestSimdShImm.cs
index 77285222..edc50d4d 100644
--- a/Ryujinx.Tests/Cpu/CpuTestSimdShImm.cs
+++ b/Ryujinx.Tests/Cpu/CpuTestSimdShImm.cs
@@ -20,6 +20,18 @@ namespace Ryujinx.Tests.Cpu
                                  0x8000000000000000ul, 0xFFFFFFFFFFFFFFFFul };
         }
 
+        private static ulong[] _1H_()
+        {
+            return new ulong[] { 0x0000000000000000ul, 0x0000000000007FFFul,
+                                 0x0000000000008000ul, 0x000000000000FFFFul };
+        }
+
+        private static ulong[] _1S_()
+        {
+            return new ulong[] { 0x0000000000000000ul, 0x000000007FFFFFFFul,
+                                 0x0000000080000000ul, 0x00000000FFFFFFFFul };
+        }
+
         private static ulong[] _2S_()
         {
             return new ulong[] { 0x0000000000000000ul, 0x7FFFFFFF7FFFFFFFul,
@@ -114,6 +126,111 @@ namespace Ryujinx.Tests.Cpu
                 0x6F401400u  // USRA  V0.2D, V0.2D, #64
             };
         }
+
+        private static uint[] _ShrImmNarrow_V_8H8B_8H16B_()
+        {
+            return new uint[]
+            {
+                0x0F088C00u, // RSHRN V0.8B, V0.8H, #8
+                0x0F088400u  // SHRN  V0.8B, V0.8H, #8
+            };
+        }
+
+        private static uint[] _ShrImmNarrow_V_4S4H_4S8H_()
+        {
+            return new uint[]
+            {
+                0x0F108C00u, // RSHRN V0.4H, V0.4S, #16
+                0x0F108400u  // SHRN  V0.4H, V0.4S, #16
+            };
+        }
+
+        private static uint[] _ShrImmNarrow_V_2D2S_2D4S_()
+        {
+            return new uint[]
+            {
+                0x0F208C00u, // RSHRN V0.2S, V0.2D, #32
+                0x0F208400u  // SHRN  V0.2S, V0.2D, #32
+            };
+        }
+
+        private static uint[] _ShrImmSaturatingNarrow_S_HB_()
+        {
+            return new uint[]
+            {
+                0x5F089C00u, // SQRSHRN  B0, H0, #8
+                0x7F089C00u, // UQRSHRN  B0, H0, #8
+                0x7F088C00u, // SQRSHRUN B0, H0, #8
+                0x5F089400u, // SQSHRN   B0, H0, #8
+                0x7F089400u, // UQSHRN   B0, H0, #8
+                0x7F088400u  // SQSHRUN  B0, H0, #8
+            };
+        }
+
+        private static uint[] _ShrImmSaturatingNarrow_S_SH_()
+        {
+            return new uint[]
+            {
+                0x5F109C00u, // SQRSHRN  H0, S0, #16
+                0x7F109C00u, // UQRSHRN  H0, S0, #16
+                0x7F108C00u, // SQRSHRUN H0, S0, #16
+                0x5F109400u, // SQSHRN   H0, S0, #16
+                0x7F109400u, // UQSHRN   H0, S0, #16
+                0x7F108400u  // SQSHRUN  H0, S0, #16
+            };
+        }
+
+        private static uint[] _ShrImmSaturatingNarrow_S_DS_()
+        {
+            return new uint[]
+            {
+                0x5F209C00u, // SQRSHRN  S0, D0, #32
+                0x7F209C00u, // UQRSHRN  S0, D0, #32
+                0x7F208C00u, // SQRSHRUN S0, D0, #32
+                0x5F209400u, // SQSHRN   S0, D0, #32
+                0x7F209400u, // UQSHRN   S0, D0, #32
+                0x7F208400u  // SQSHRUN  S0, D0, #32
+            };
+        }
+
+        private static uint[] _ShrImmSaturatingNarrow_V_8H8B_8H16B_()
+        {
+            return new uint[]
+            {
+                0x0F089C00u, // SQRSHRN  V0.8B, V0.8H, #8
+                0x2F089C00u, // UQRSHRN  V0.8B, V0.8H, #8
+                0x2F088C00u, // SQRSHRUN V0.8B, V0.8H, #8
+                0x0F089400u, // SQSHRN   V0.8B, V0.8H, #8
+                0x2F089400u, // UQSHRN   V0.8B, V0.8H, #8
+                0x2F088400u  // SQSHRUN  V0.8B, V0.8H, #8
+            };
+        }
+
+        private static uint[] _ShrImmSaturatingNarrow_V_4S4H_4S8H_()
+        {
+            return new uint[]
+            {
+                0x0F109C00u, // SQRSHRN  V0.4H, V0.4S, #16
+                0x2F109C00u, // UQRSHRN  V0.4H, V0.4S, #16
+                0x2F108C00u, // SQRSHRUN V0.4H, V0.4S, #16
+                0x0F109400u, // SQSHRN   V0.4H, V0.4S, #16
+                0x2F109400u, // UQSHRN   V0.4H, V0.4S, #16
+                0x2F108400u  // SQSHRUN  V0.4H, V0.4S, #16
+            };
+        }
+
+        private static uint[] _ShrImmSaturatingNarrow_V_2D2S_2D4S_()
+        {
+            return new uint[]
+            {
+                0x0F209C00u, // SQRSHRN  V0.2S, V0.2D, #32
+                0x2F209C00u, // UQRSHRN  V0.2S, V0.2D, #32
+                0x2F208C00u, // SQRSHRUN V0.2S, V0.2D, #32
+                0x0F209400u, // SQSHRN   V0.2S, V0.2D, #32
+                0x2F209400u, // UQSHRN   V0.2S, V0.2D, #32
+                0x2F208400u  // SQSHRUN  V0.2S, V0.2D, #32
+            };
+        }
 #endregion
 
         private const int RndCnt = 2;
@@ -339,6 +456,207 @@ namespace Ryujinx.Tests.Cpu
 
             CompareAgainstUnicorn();
         }
+
+        [Test, Pairwise]
+        public void ShrImmNarrow_V_8H8B_8H16B([ValueSource("_ShrImmNarrow_V_8H8B_8H16B_")] uint Opcodes,
+                                              [Values(0u)]     uint Rd,
+                                              [Values(1u, 0u)] uint Rn,
+                                              [ValueSource("_4H_")] [Random(RndCnt)] ulong Z,
+                                              [ValueSource("_4H_")] [Random(RndCnt)] ulong A,
+                                              [Range(1u, 8u)] uint Shift,
+                                              [Values(0b0u, 0b1u)] uint Q) // <8H8B, 8H16B>
+        {
+            uint ImmHB = (16 - Shift) & 0x7F;
+
+            Opcodes |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
+            Opcodes |= (ImmHB << 16);
+            Opcodes |= ((Q & 1) << 30);
+
+            Vector128<float> V0 = MakeVectorE0E1(Z, Z);
+            Vector128<float> V1 = MakeVectorE0E1(A, A);
+
+            AThreadState ThreadState = SingleOpcode(Opcodes, V0: V0, V1: V1);
+
+            CompareAgainstUnicorn();
+        }
+
+        [Test, Pairwise]
+        public void ShrImmNarrow_V_4S4H_4S8H([ValueSource("_ShrImmNarrow_V_4S4H_4S8H_")] uint Opcodes,
+                                             [Values(0u)]     uint Rd,
+                                             [Values(1u, 0u)] uint Rn,
+                                             [ValueSource("_2S_")] [Random(RndCnt)] ulong Z,
+                                             [ValueSource("_2S_")] [Random(RndCnt)] ulong A,
+                                             [Range(1u, 16u)] uint Shift,
+                                             [Values(0b0u, 0b1u)] uint Q) // <4S4H, 4S8H>
+        {
+            uint ImmHB = (32 - Shift) & 0x7F;
+
+            Opcodes |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
+            Opcodes |= (ImmHB << 16);
+            Opcodes |= ((Q & 1) << 30);
+
+            Vector128<float> V0 = MakeVectorE0E1(Z, Z);
+            Vector128<float> V1 = MakeVectorE0E1(A, A);
+
+            AThreadState ThreadState = SingleOpcode(Opcodes, V0: V0, V1: V1);
+
+            CompareAgainstUnicorn();
+        }
+
+        [Test, Pairwise]
+        public void ShrImmNarrow_V_2D2S_2D4S([ValueSource("_ShrImmNarrow_V_2D2S_2D4S_")] uint Opcodes,
+                                             [Values(0u)]     uint Rd,
+                                             [Values(1u, 0u)] uint Rn,
+                                             [ValueSource("_1D_")] [Random(RndCnt)] ulong Z,
+                                             [ValueSource("_1D_")] [Random(RndCnt)] ulong A,
+                                             [Range(1u, 32u)] uint Shift,
+                                             [Values(0b0u, 0b1u)] uint Q) // <2D2S, 2D4S>
+        {
+            uint ImmHB = (64 - Shift) & 0x7F;
+
+            Opcodes |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
+            Opcodes |= (ImmHB << 16);
+            Opcodes |= ((Q & 1) << 30);
+
+            Vector128<float> V0 = MakeVectorE0E1(Z, Z);
+            Vector128<float> V1 = MakeVectorE0E1(A, A);
+
+            AThreadState ThreadState = SingleOpcode(Opcodes, V0: V0, V1: V1);
+
+            CompareAgainstUnicorn();
+        }
+
+        [Test, Pairwise]
+        public void ShrImmSaturatingNarrow_S_HB([ValueSource("_ShrImmSaturatingNarrow_S_HB_")] uint Opcodes,
+                                                [Values(0u)]     uint Rd,
+                                                [Values(1u, 0u)] uint Rn,
+                                                [ValueSource("_1H_")] [Random(RndCnt)] ulong Z,
+                                                [ValueSource("_1H_")] [Random(RndCnt)] ulong A,
+                                                [Range(1u, 8u)] uint Shift)
+        {
+            uint ImmHB = (16 - Shift) & 0x7F;
+
+            Opcodes |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
+            Opcodes |= (ImmHB << 16);
+
+            Vector128<float> V0 = MakeVectorE0E1(Z, Z);
+            Vector128<float> V1 = MakeVectorE0(A);
+
+            AThreadState ThreadState = SingleOpcode(Opcodes, V0: V0, V1: V1);
+
+            CompareAgainstUnicorn(FpsrMask: FPSR.QC);
+        }
+
+        [Test, Pairwise]
+        public void ShrImmSaturatingNarrow_S_SH([ValueSource("_ShrImmSaturatingNarrow_S_SH_")] uint Opcodes,
+                                                [Values(0u)]     uint Rd,
+                                                [Values(1u, 0u)] uint Rn,
+                                                [ValueSource("_1S_")] [Random(RndCnt)] ulong Z,
+                                                [ValueSource("_1S_")] [Random(RndCnt)] ulong A,
+                                                [Range(1u, 16u)] uint Shift)
+        {
+            uint ImmHB = (32 - Shift) & 0x7F;
+
+            Opcodes |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
+            Opcodes |= (ImmHB << 16);
+
+            Vector128<float> V0 = MakeVectorE0E1(Z, Z);
+            Vector128<float> V1 = MakeVectorE0(A);
+
+            AThreadState ThreadState = SingleOpcode(Opcodes, V0: V0, V1: V1);
+
+            CompareAgainstUnicorn(FpsrMask: FPSR.QC);
+        }
+
+        [Test, Pairwise]
+        public void ShrImmSaturatingNarrow_S_DS([ValueSource("_ShrImmSaturatingNarrow_S_DS_")] uint Opcodes,
+                                                [Values(0u)]     uint Rd,
+                                                [Values(1u, 0u)] uint Rn,
+                                                [ValueSource("_1D_")] [Random(RndCnt)] ulong Z,
+                                                [ValueSource("_1D_")] [Random(RndCnt)] ulong A,
+                                                [Range(1u, 32u)] uint Shift)
+        {
+            uint ImmHB = (64 - Shift) & 0x7F;
+
+            Opcodes |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
+            Opcodes |= (ImmHB << 16);
+
+            Vector128<float> V0 = MakeVectorE0E1(Z, Z);
+            Vector128<float> V1 = MakeVectorE0(A);
+
+            AThreadState ThreadState = SingleOpcode(Opcodes, V0: V0, V1: V1);
+
+            CompareAgainstUnicorn(FpsrMask: FPSR.QC);
+        }
+
+        [Test, Pairwise]
+        public void ShrImmSaturatingNarrow_V_8H8B_8H16B([ValueSource("_ShrImmSaturatingNarrow_V_8H8B_8H16B_")] uint Opcodes,
+                                                        [Values(0u)]     uint Rd,
+                                                        [Values(1u, 0u)] uint Rn,
+                                                        [ValueSource("_4H_")] [Random(RndCnt)] ulong Z,
+                                                        [ValueSource("_4H_")] [Random(RndCnt)] ulong A,
+                                                        [Range(1u, 8u)] uint Shift,
+                                                        [Values(0b0u, 0b1u)] uint Q) // <8H8B, 8H16B>
+        {
+            uint ImmHB = (16 - Shift) & 0x7F;
+
+            Opcodes |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
+            Opcodes |= (ImmHB << 16);
+            Opcodes |= ((Q & 1) << 30);
+
+            Vector128<float> V0 = MakeVectorE0E1(Z, Z);
+            Vector128<float> V1 = MakeVectorE0(A);
+
+            AThreadState ThreadState = SingleOpcode(Opcodes, V0: V0, V1: V1);
+
+            CompareAgainstUnicorn(FpsrMask: FPSR.QC);
+        }
+
+        [Test, Pairwise]
+        public void ShrImmSaturatingNarrow_V_4S4H_4S8H([ValueSource("_ShrImmSaturatingNarrow_V_4S4H_4S8H_")] uint Opcodes,
+                                                       [Values(0u)]     uint Rd,
+                                                       [Values(1u, 0u)] uint Rn,
+                                                       [ValueSource("_2S_")] [Random(RndCnt)] ulong Z,
+                                                       [ValueSource("_2S_")] [Random(RndCnt)] ulong A,
+                                                       [Range(1u, 16u)] uint Shift,
+                                                       [Values(0b0u, 0b1u)] uint Q) // <4S4H, 4S8H>
+        {
+            uint ImmHB = (32 - Shift) & 0x7F;
+
+            Opcodes |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
+            Opcodes |= (ImmHB << 16);
+            Opcodes |= ((Q & 1) << 30);
+
+            Vector128<float> V0 = MakeVectorE0E1(Z, Z);
+            Vector128<float> V1 = MakeVectorE0(A);
+
+            AThreadState ThreadState = SingleOpcode(Opcodes, V0: V0, V1: V1);
+
+            CompareAgainstUnicorn(FpsrMask: FPSR.QC);
+        }
+
+        [Test, Pairwise]
+        public void ShrImmSaturatingNarrow_V_2D2S_2D4S([ValueSource("_ShrImmSaturatingNarrow_V_2D2S_2D4S_")] uint Opcodes,
+                                                       [Values(0u)]     uint Rd,
+                                                       [Values(1u, 0u)] uint Rn,
+                                                       [ValueSource("_1D_")] [Random(RndCnt)] ulong Z,
+                                                       [ValueSource("_1D_")] [Random(RndCnt)] ulong A,
+                                                       [Range(1u, 32u)] uint Shift,
+                                                       [Values(0b0u, 0b1u)] uint Q) // <2D2S, 2D4S>
+        {
+            uint ImmHB = (64 - Shift) & 0x7F;
+
+            Opcodes |= ((Rn & 31) << 5) | ((Rd & 31) << 0);
+            Opcodes |= (ImmHB << 16);
+            Opcodes |= ((Q & 1) << 30);
+
+            Vector128<float> V0 = MakeVectorE0E1(Z, Z);
+            Vector128<float> V1 = MakeVectorE0(A);
+
+            AThreadState ThreadState = SingleOpcode(Opcodes, V0: V0, V1: V1);
+
+            CompareAgainstUnicorn(FpsrMask: FPSR.QC);
+        }
 #endif
     }
 }