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| author | LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com> | 2019-06-30 01:02:48 +0200 |
|---|---|---|
| committer | gdkchan <gab.dark.100@gmail.com> | 2019-06-29 20:02:48 -0300 |
| commit | 10c74182babaf8cf6bedaeffd64c3109df4ea816 (patch) | |
| tree | ee55c64d3a022e322f995e129187251583027aae /Ryujinx.Tests/Cpu/CpuTestSimdRegElem.cs | |
| parent | ba86a5d7f3aa0127c4732c739af3f6086fb6acd9 (diff) | |
Implement the remaining tests for Simd and Fp instructions of data processing type. Small opts. for Fmov_Ftoi/1 & Fmov_Itof/1 Insts. (#709)
* Update CpuTestSimdShImm.cs
* Update OpCodeTable.cs
* Update CpuTestSimdReg.cs
* Add Ins_Gp & Ins_V Tests.
Improve Smov_S & Umov_S Tests.
* Add Bic_Vi & Orr_Vi Tests.
* OpTable Fixes for Bic_Vi & Orr_Vi Insts.
* Add Saddlv_V & Uaddlv_V Tests.
* Nit.
* Add Smull_V & Umull_V Tests.
Improve Simd Permute Tests.
* Nit.
* Add Fcsel_S Test.
* Add Fnmadd_S, Fnmsub_S & Fnmul_S Tests.
* Fmov_V -> Fmov_Vi
* OpTable Fixes for Fmov_Si & Fmov_Vi Insts.
* Add Fmov_Vi Test.
* Add Fmov_S Test.
* Add Fmov_Si Test.
Add new test category SimdFmov.
* Nit.
* OpTable Fixes for Fmov_Ftoi/1 & Fmov_Itof/1 Insts.
* Small opts. for Fmov_Ftoi/1 & Fmov_Itof/1 Insts.
Small simpl. for Smov_S Inst.
Remove unnecessary method EmitIntZeroUpperIfNeeded.
* Add Fmov_Ftoi/1 & Fmov_Itof/1 Tests.
Diffstat (limited to 'Ryujinx.Tests/Cpu/CpuTestSimdRegElem.cs')
| -rw-r--r-- | Ryujinx.Tests/Cpu/CpuTestSimdRegElem.cs | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/Ryujinx.Tests/Cpu/CpuTestSimdRegElem.cs b/Ryujinx.Tests/Cpu/CpuTestSimdRegElem.cs index 7fc593a8..64f9bc6c 100644 --- a/Ryujinx.Tests/Cpu/CpuTestSimdRegElem.cs +++ b/Ryujinx.Tests/Cpu/CpuTestSimdRegElem.cs @@ -73,7 +73,8 @@ namespace Ryujinx.Tests.Cpu } #endregion - private const int RndCnt = 2; + private const int RndCnt = 2; + private const int RndCntIndex = 2; [Test, Pairwise] public void Mla_Mls_Mul_Ve_4H_8H([ValueSource("_Mla_Mls_Mul_Ve_4H_8H_")] uint opcodes, @@ -83,7 +84,7 @@ namespace Ryujinx.Tests.Cpu [ValueSource("_4H_")] [Random(RndCnt)] ulong z, [ValueSource("_4H_")] [Random(RndCnt)] ulong a, [ValueSource("_4H_")] [Random(RndCnt)] ulong b, - [Values(0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u)] uint index, + [Values(0u, 7u)] [Random(1u, 6u, RndCntIndex)] uint index, [Values(0b0u, 0b1u)] uint q) // <4H, 8H> { uint h = (index >> 2) & 1; @@ -138,7 +139,7 @@ namespace Ryujinx.Tests.Cpu [ValueSource("_4H_")] [Random(RndCnt)] ulong z, [ValueSource("_4H_")] [Random(RndCnt)] ulong a, [ValueSource("_4H_")] [Random(RndCnt)] ulong b, - [Values(0u, 1u, 2u, 3u, 4u, 5u, 6u, 7u)] uint index, + [Values(0u, 7u)] [Random(1u, 6u, RndCntIndex)] uint index, [Values(0b0u, 0b1u)] uint q) // <4H4S, 8H4S> { uint h = (index >> 2) & 1; |