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| author | LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com> | 2020-08-08 17:18:51 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-08-08 17:18:51 +0200 |
| commit | e36e97c64d7b973fbbc3ac92e9f115d74a4d9e2d (patch) | |
| tree | 80bdb45273e6bbc0d862276bdb6f6551b0a2541d /Ryujinx.Tests/Cpu/CpuTestSimdReg32.cs | |
| parent | 8d59ad88b4d59ef6ad26b9a747dc871fd1f1007a (diff) | |
CPU: This PR fixes Fpscr, among other things. (#1433)
* CPU: This PR fixes Fpscr, among other things.
* Add Fpscr.Qc = 1 if sat. for Vqrshrn & Vqrshrun.
* Fix Vcmp & Vcmpe opcode table.
* Revert "Fix Vcmp & Vcmpe opcode table."
This reverts commit c117d9410d693185ff5f8ee8e457ffbfb2027dd5.
* Address PR feedbacks.
Diffstat (limited to 'Ryujinx.Tests/Cpu/CpuTestSimdReg32.cs')
| -rw-r--r-- | Ryujinx.Tests/Cpu/CpuTestSimdReg32.cs | 9 |
1 files changed, 2 insertions, 7 deletions
diff --git a/Ryujinx.Tests/Cpu/CpuTestSimdReg32.cs b/Ryujinx.Tests/Cpu/CpuTestSimdReg32.cs index 866f50a9..92ad329f 100644 --- a/Ryujinx.Tests/Cpu/CpuTestSimdReg32.cs +++ b/Ryujinx.Tests/Cpu/CpuTestSimdReg32.cs @@ -286,16 +286,11 @@ namespace Ryujinx.Tests.Cpu V128 v1 = MakeVectorE0(a); V128 v2 = MakeVectorE0(b); - bool v = TestContext.CurrentContext.Random.NextBool(); - bool c = TestContext.CurrentContext.Random.NextBool(); - bool z = TestContext.CurrentContext.Random.NextBool(); - bool n = TestContext.CurrentContext.Random.NextBool(); - int fpscr = (int)(TestContext.CurrentContext.Random.NextUInt(0xf) << 28); - SingleOpcode(opcode, v1: v1, v2: v2, overflow: v, carry: c, zero: z, negative: n, fpscr: fpscr, copyFpFlags: true); + SingleOpcode(opcode, v1: v1, v2: v2, fpscr: fpscr); - CompareAgainstUnicorn(); + CompareAgainstUnicorn(fpsrMask: Fpsr.Nzcv); } [Test, Pairwise, Description("VMLSL.<type><size> <Vd>, <Vn>, <Vm>")] |