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| author | LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com> | 2018-12-02 01:34:43 +0100 |
|---|---|---|
| committer | gdkchan <gab.dark.100@gmail.com> | 2018-12-01 22:34:43 -0200 |
| commit | ad00fd02442cf9c0f00c4562635738042b521efa (patch) | |
| tree | cf1e9607e41f616d2c0ad171406fc1d271d45456 /Ryujinx.Tests/Cpu/CpuTestSimdReg.cs | |
| parent | 9b22e8af5ee3e0896fc5f464022579ef0713e504 (diff) | |
Fix Sshl_V; Add S/Uqrshl_V, S/Uqshl_V, S/Urshl_V; Add Tests. (#516)
* Update OpCodeTable.cs
* Update InstEmitSimdShift.cs
* Update SoftFallback.cs
* Update CpuTestSimdReg.cs
* Nit.
* Update SoftFallback.cs
* Update Optimizations.cs
* Update InstEmitSimdLogical.cs
* Update InstEmitSimdArithmetic.cs
Diffstat (limited to 'Ryujinx.Tests/Cpu/CpuTestSimdReg.cs')
| -rw-r--r-- | Ryujinx.Tests/Cpu/CpuTestSimdReg.cs | 74 |
1 files changed, 74 insertions, 0 deletions
diff --git a/Ryujinx.Tests/Cpu/CpuTestSimdReg.cs b/Ryujinx.Tests/Cpu/CpuTestSimdReg.cs index d43447a7..cceb8b10 100644 --- a/Ryujinx.Tests/Cpu/CpuTestSimdReg.cs +++ b/Ryujinx.Tests/Cpu/CpuTestSimdReg.cs @@ -420,6 +420,36 @@ namespace Ryujinx.Tests.Cpu }; } + private static uint[] _ShlReg_V_8B_4H_2S_() + { + return new uint[] + { + 0x0E205C00u, // SQRSHL V0.8B, V0.8B, V0.8B + 0x0E204C00u, // SQSHL V0.8B, V0.8B, V0.8B + 0x0E205400u, // SRSHL V0.8B, V0.8B, V0.8B + 0x0E204400u, // SSHL V0.8B, V0.8B, V0.8B + 0x2E205C00u, // UQRSHL V0.8B, V0.8B, V0.8B + 0x2E204C00u, // UQSHL V0.8B, V0.8B, V0.8B + 0x2E205400u, // URSHL V0.8B, V0.8B, V0.8B + 0x2E204400u // USHL V0.8B, V0.8B, V0.8B + }; + } + + private static uint[] _ShlReg_V_16B_8H_4S_2D_() + { + return new uint[] + { + 0x4E205C00u, // SQRSHL V0.16B, V0.16B, V0.16B + 0x4E204C00u, // SQSHL V0.16B, V0.16B, V0.16B + 0x4E205400u, // SRSHL V0.16B, V0.16B, V0.16B + 0x4E204400u, // SSHL V0.16B, V0.16B, V0.16B + 0x6E205C00u, // UQRSHL V0.16B, V0.16B, V0.16B + 0x6E204C00u, // UQSHL V0.16B, V0.16B, V0.16B + 0x6E205400u, // URSHL V0.16B, V0.16B, V0.16B + 0x6E204400u // USHL V0.16B, V0.16B, V0.16B + }; + } + private static uint[] _U_Max_Min_P_V_() { return new uint[] @@ -2602,6 +2632,50 @@ namespace Ryujinx.Tests.Cpu CompareAgainstUnicorn(); } + [Test, Pairwise] + public void ShlReg_V_8B_4H_2S([ValueSource("_ShlReg_V_8B_4H_2S_")] uint opcodes, + [Values(0u)] uint rd, + [Values(1u, 0u)] uint rn, + [Values(2u, 0u)] uint rm, + [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong z, + [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong a, + [ValueSource("_8B4H2S_")] [Random(0ul, 255ul, RndCnt)] ulong b, + [Values(0b00u, 0b01u, 0b10u)] uint size) // <8B, 4H, 2S> + { + opcodes |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0); + opcodes |= ((size & 3) << 22); + + Vector128<float> v0 = MakeVectorE0E1(z, z); + Vector128<float> v1 = MakeVectorE0(a); + Vector128<float> v2 = MakeVectorE0(b); + + SingleOpcode(opcodes, v0: v0, v1: v1, v2: v2); + + CompareAgainstUnicorn(fpsrMask: Fpsr.Qc); + } + + [Test, Pairwise] + public void ShlReg_V_16B_8H_4S_2D([ValueSource("_ShlReg_V_16B_8H_4S_2D_")] uint opcodes, + [Values(0u)] uint rd, + [Values(1u, 0u)] uint rn, + [Values(2u, 0u)] uint rm, + [ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong z, + [ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong a, + [ValueSource("_8B4H2S1D_")] [Random(0ul, 255ul, RndCnt)] ulong b, + [Values(0b00u, 0b01u, 0b10u, 0b11u)] uint size) // <16B, 8H, 4S, 2D> + { + opcodes |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0); + opcodes |= ((size & 3) << 22); + + Vector128<float> v0 = MakeVectorE0E1(z, z); + Vector128<float> v1 = MakeVectorE0E1(a, a); + Vector128<float> v2 = MakeVectorE0E1(b, b); + + SingleOpcode(opcodes, v0: v0, v1: v1, v2: v2); + + CompareAgainstUnicorn(fpsrMask: Fpsr.Qc); + } + [Test, Pairwise, Description("SSUBL{2} <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Tb>")] public void Ssubl_V_8B8H_4H4S_2S2D([Values(0u)] uint rd, [Values(1u, 0u)] uint rn, |