Add Fmax/minv_V & S/Ushl_S Inst.s with Tests. Fix Maxps/d & Minps/d d… (#1335)

* Add Fmax/minv_V & S/Ushl_S Inst.s with Tests. Fix Maxps/d & Minps/d double zero sign handling. Allows better handling of NaNs.

* Optimized EmitSse2VectorIsNaNOpF() for multiple uses per opF.

1 files changed, 45 insertions, 12 deletions

diff --git a/Ryujinx.Tests/Cpu/CpuTestSimdReg.cs b/Ryujinx.Tests/Cpu/CpuTestSimdReg.cs
index a5458382..828c1bf9 100644
--- a/Ryujinx.Tests/Cpu/CpuTestSimdReg.cs
+++ b/Ryujinx.Tests/Cpu/CpuTestSimdReg.cs
@@ -373,12 +373,14 @@ namespace Ryujinx.Tests.Cpu
         {
             return new uint[]
             {
-                0x0E20F400u, // FMAX   V0.2S, V0.2S, V0.2S
-                0x0E20C400u, // FMAXNM V0.2S, V0.2S, V0.2S
-                0x2E20F400u, // FMAXP  V0.2S, V0.2S, V0.2S
-                0x0EA0F400u, // FMIN   V0.2S, V0.2S, V0.2S
-                0x0EA0C400u, // FMINNM V0.2S, V0.2S, V0.2S
-                0x2EA0F400u  // FMINP  V0.2S, V0.2S, V0.2S
+                0x0E20F400u, // FMAX    V0.2S, V0.2S, V0.2S
+                0x0E20C400u, // FMAXNM  V0.2S, V0.2S, V0.2S
+                0x2E20C400u, // FMAXNMP V0.2S, V0.2S, V0.2S
+                0x2E20F400u, // FMAXP   V0.2S, V0.2S, V0.2S
+                0x0EA0F400u, // FMIN    V0.2S, V0.2S, V0.2S
+                0x0EA0C400u, // FMINNM  V0.2S, V0.2S, V0.2S
+                0x2EA0C400u, // FMINNMP V0.2S, V0.2S, V0.2S
+                0x2EA0F400u  // FMINP   V0.2S, V0.2S, V0.2S
             };
         }
 
@@ -386,12 +388,14 @@ namespace Ryujinx.Tests.Cpu
         {
             return new uint[]
             {
-                0x4E60F400u, // FMAX   V0.2D, V0.2D, V0.2D
-                0x4E60C400u, // FMAXNM V0.2D, V0.2D, V0.2D
-                0x6E60F400u, // FMAXP  V0.2D, V0.2D, V0.2D
-                0x4EE0F400u, // FMIN   V0.2D, V0.2D, V0.2D
-                0x4EE0C400u, // FMINNM V0.2D, V0.2D, V0.2D
-                0x6EE0F400u  // FMINP  V0.2D, V0.2D, V0.2D
+                0x4E60F400u, // FMAX    V0.2D, V0.2D, V0.2D
+                0x4E60C400u, // FMAXNM  V0.2D, V0.2D, V0.2D
+                0x6E60C400u, // FMAXNMP V0.2D, V0.2D, V0.2D
+                0x6E60F400u, // FMAXP   V0.2D, V0.2D, V0.2D
+                0x4EE0F400u, // FMIN    V0.2D, V0.2D, V0.2D
+                0x4EE0C400u, // FMINNM  V0.2D, V0.2D, V0.2D
+                0x6EE0C400u, // FMINNMP V0.2D, V0.2D, V0.2D
+                0x6EE0F400u  // FMINP   V0.2D, V0.2D, V0.2D
             };
         }
 
@@ -531,6 +535,15 @@ namespace Ryujinx.Tests.Cpu
             };
         }
 
+        private static uint[] _ShlReg_S_D_()
+        {
+            return new uint[]
+            {
+                0x5EE04400u, // SSHL D0, D0, D0
+                0x7EE04400u  // USHL D0, D0, D0
+            };
+        }
+
         private static uint[] _ShlReg_V_8B_4H_2S_()
         {
             return new uint[]
@@ -2821,6 +2834,26 @@ namespace Ryujinx.Tests.Cpu
         }
 
         [Test, Pairwise]
+        public void ShlReg_S_D([ValueSource("_ShlReg_S_D_")] uint opcodes,
+                               [Values(0u)]     uint rd,
+                               [Values(1u, 0u)] uint rn,
+                               [Values(2u, 0u)] uint rm,
+                               [ValueSource("_1D_")] [Random(RndCnt)] ulong z,
+                               [ValueSource("_1D_")] [Random(RndCnt)] ulong a,
+                               [ValueSource("_1D_")] [Random(0ul, 255ul, RndCnt)] ulong b)
+        {
+            opcodes |= ((rm & 31) << 16) | ((rn & 31) << 5) | ((rd & 31) << 0);
+
+            V128 v0 = MakeVectorE0E1(z, z);
+            V128 v1 = MakeVectorE0(a);
+            V128 v2 = MakeVectorE0(b);
+
+            SingleOpcode(opcodes, v0: v0, v1: v1, v2: v2);
+
+            CompareAgainstUnicorn(fpsrMask: Fpsr.Qc);
+        }
+
+        [Test, Pairwise]
         public void ShlReg_V_8B_4H_2S([ValueSource("_ShlReg_V_8B_4H_2S_")] uint opcodes,
                                       [Values(0u)]     uint rd,
                                       [Values(1u, 0u)] uint rn,