Add SHADD, SHSUB, UHSUB, SRHADD, URHADD, instructions; add 12 Tests. (#380)

* Update AOpCodeTable.cs

* Update AInstEmitSimdArithmetic.cs

* Update Instructions.cs

* Update CpuTestSimdReg.cs

* Update CpuTest.cs

* Update CpuTestSimd.cs

* Update CpuTestSimdCrypto.cs

1 files changed, 400 insertions, 28 deletions

diff --git a/Ryujinx.Tests/Cpu/CpuTestSimdReg.cs b/Ryujinx.Tests/Cpu/CpuTestSimdReg.cs
index 9aa93856..2ca91b37 100644
--- a/Ryujinx.Tests/Cpu/CpuTestSimdReg.cs
+++ b/Ryujinx.Tests/Cpu/CpuTestSimdReg.cs
@@ -1690,8 +1690,8 @@ namespace Ryujinx.Tests.Cpu
                                                  [Values(1u, 0u)] uint Rn,
                                                  [Values(2u, 0u)] uint Rm,
                                                  [ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z,
-                                                 [ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong A,
-                                                 [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong B,
+                                                 [ValueSource("_4H2S1D_")]   [Random(RndCnt)] ulong A,
+                                                 [ValueSource("_8B4H2S_")]   [Random(RndCnt)] ulong B,
                                                  [Values(0b00u, 0b01u, 0b10u)] uint size) // <8B8H8H, 4H4S4S, 2S2D2D>
         {
             uint Opcode = 0x0E201000; // SADDW V0.8H, V0.8H, V0.8B
@@ -1721,8 +1721,8 @@ namespace Ryujinx.Tests.Cpu
                                                   [Values(1u, 0u)] uint Rn,
                                                   [Values(2u, 0u)] uint Rm,
                                                   [ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z,
-                                                  [ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong A,
-                                                  [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong B,
+                                                  [ValueSource("_4H2S1D_")]   [Random(RndCnt)] ulong A,
+                                                  [ValueSource("_8B4H2S_")]   [Random(RndCnt)] ulong B,
                                                   [Values(0b00u, 0b01u, 0b10u)] uint size) // <16B8H8H, 8H4S4S, 4S2D2D>
         {
             uint Opcode = 0x4E201000; // SADDW2 V0.8H, V0.8H, V0.16B
@@ -1747,13 +1747,13 @@ namespace Ryujinx.Tests.Cpu
             });
         }
 
-        [Test, Explicit, Description("SHA256H <Qd>, <Qn>, <Vm>.4S")] // 2916 tests.
+        [Test, Pairwise, Description("SHA256H <Qd>, <Qn>, <Vm>.4S")]
         public void Sha256h_V([Values(0u)]     uint Rd,
                               [Values(1u, 0u)] uint Rn,
                               [Values(2u, 0u)] uint Rm,
-                              [Random(3)] ulong Z0, [Random(3)] ulong Z1,
-                              [Random(3)] ulong A0, [Random(3)] ulong A1,
-                              [Random(3)] ulong B0, [Random(3)] ulong B1)
+                              [Random(RndCnt / 2)] ulong Z0, [Random(RndCnt / 2)] ulong Z1,
+                              [Random(RndCnt / 2)] ulong A0, [Random(RndCnt / 2)] ulong A1,
+                              [Random(RndCnt / 2)] ulong B0, [Random(RndCnt / 2)] ulong B1)
         {
             uint Opcode = 0x5E004000; // SHA256H Q0, Q0, V0.4S
             Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
@@ -1784,13 +1784,13 @@ namespace Ryujinx.Tests.Cpu
             });
         }
 
-        [Test, Explicit, Description("SHA256H2 <Qd>, <Qn>, <Vm>.4S")] // 2916 tests.
+        [Test, Pairwise, Description("SHA256H2 <Qd>, <Qn>, <Vm>.4S")]
         public void Sha256h2_V([Values(0u)]     uint Rd,
                                [Values(1u, 0u)] uint Rn,
                                [Values(2u, 0u)] uint Rm,
-                               [Random(3)] ulong Z0, [Random(3)] ulong Z1,
-                               [Random(3)] ulong A0, [Random(3)] ulong A1,
-                               [Random(3)] ulong B0, [Random(3)] ulong B1)
+                               [Random(RndCnt / 2)] ulong Z0, [Random(RndCnt / 2)] ulong Z1,
+                               [Random(RndCnt / 2)] ulong A0, [Random(RndCnt / 2)] ulong A1,
+                               [Random(RndCnt / 2)] ulong B0, [Random(RndCnt / 2)] ulong B1)
         {
             uint Opcode = 0x5E005000; // SHA256H2 Q0, Q0, V0.4S
             Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
@@ -1821,13 +1821,13 @@ namespace Ryujinx.Tests.Cpu
             });
         }
 
-        [Test, Explicit, Description("SHA256SU1 <Vd>.4S, <Vn>.4S, <Vm>.4S")] // 2916 tests.
+        [Test, Pairwise, Description("SHA256SU1 <Vd>.4S, <Vn>.4S, <Vm>.4S")]
         public void Sha256su1_V([Values(0u)]     uint Rd,
                                 [Values(1u, 0u)] uint Rn,
                                 [Values(2u, 0u)] uint Rm,
-                                [Random(3)] ulong Z0, [Random(3)] ulong Z1,
-                                [Random(3)] ulong A0, [Random(3)] ulong A1,
-                                [Random(3)] ulong B0, [Random(3)] ulong B1)
+                                [Random(RndCnt / 2)] ulong Z0, [Random(RndCnt / 2)] ulong Z1,
+                                [Random(RndCnt / 2)] ulong A0, [Random(RndCnt / 2)] ulong A1,
+                                [Random(RndCnt / 2)] ulong B0, [Random(RndCnt / 2)] ulong B1)
         {
             uint Opcode = 0x5E006000; // SHA256SU1 V0.4S, V0.4S, V0.4S
             Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
@@ -1858,6 +1858,130 @@ namespace Ryujinx.Tests.Cpu
             });
         }
 
+        [Test, Pairwise, Description("SHADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
+        public void Shadd_V_8B_4H_2S([Values(0u)]     uint Rd,
+                                     [Values(1u, 0u)] uint Rn,
+                                     [Values(2u, 0u)] uint Rm,
+                                     [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
+                                     [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
+                                     [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong B,
+                                     [Values(0b00u, 0b01u, 0b10u)] uint size) // <8B, 4H, 2S>
+        {
+            uint Opcode = 0x0E200400; // SHADD V0.8B, V0.8B, V0.8B
+            Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
+            Opcode |= ((size & 3) << 22);
+            Bits Op = new Bits(Opcode);
+
+            Vector128<float> V0 = MakeVectorE0E1(Z, Z);
+            Vector128<float> V1 = MakeVectorE0(A);
+            Vector128<float> V2 = MakeVectorE0(B);
+            AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
+
+            AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
+            AArch64.V(1, new Bits(A));
+            AArch64.V(2, new Bits(B));
+            SimdFp.Shadd_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]);
+
+            Assert.Multiple(() =>
+            {
+                Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
+                Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
+            });
+        }
+
+        [Test, Pairwise, Description("SHADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
+        public void Shadd_V_16B_8H_4S([Values(0u)]     uint Rd,
+                                      [Values(1u, 0u)] uint Rn,
+                                      [Values(2u, 0u)] uint Rm,
+                                      [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
+                                      [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
+                                      [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong B,
+                                      [Values(0b00u, 0b01u, 0b10u)] uint size) // <16B, 8H, 4S>
+        {
+            uint Opcode = 0x4E200400; // SHADD V0.16B, V0.16B, V0.16B
+            Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
+            Opcode |= ((size & 3) << 22);
+            Bits Op = new Bits(Opcode);
+
+            Vector128<float> V0 = MakeVectorE0E1(Z, Z);
+            Vector128<float> V1 = MakeVectorE0E1(A, A);
+            Vector128<float> V2 = MakeVectorE0E1(B, B);
+            AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
+
+            AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
+            AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A));
+            AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B));
+            SimdFp.Shadd_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]);
+
+            Assert.Multiple(() =>
+            {
+                Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
+                Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
+            });
+        }
+
+        [Test, Pairwise, Description("SHSUB <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
+        public void Shsub_V_8B_4H_2S([Values(0u)]     uint Rd,
+                                     [Values(1u, 0u)] uint Rn,
+                                     [Values(2u, 0u)] uint Rm,
+                                     [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
+                                     [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
+                                     [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong B,
+                                     [Values(0b00u, 0b01u, 0b10u)] uint size) // <8B, 4H, 2S>
+        {
+            uint Opcode = 0x0E202400; // SHSUB V0.8B, V0.8B, V0.8B
+            Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
+            Opcode |= ((size & 3) << 22);
+            Bits Op = new Bits(Opcode);
+
+            Vector128<float> V0 = MakeVectorE0E1(Z, Z);
+            Vector128<float> V1 = MakeVectorE0(A);
+            Vector128<float> V2 = MakeVectorE0(B);
+            AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
+
+            AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
+            AArch64.V(1, new Bits(A));
+            AArch64.V(2, new Bits(B));
+            SimdFp.Shsub_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]);
+
+            Assert.Multiple(() =>
+            {
+                Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
+                Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
+            });
+        }
+
+        [Test, Pairwise, Description("SHSUB <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
+        public void Shsub_V_16B_8H_4S([Values(0u)]     uint Rd,
+                                      [Values(1u, 0u)] uint Rn,
+                                      [Values(2u, 0u)] uint Rm,
+                                      [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
+                                      [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
+                                      [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong B,
+                                      [Values(0b00u, 0b01u, 0b10u)] uint size) // <16B, 8H, 4S>
+        {
+            uint Opcode = 0x4E202400; // SHSUB V0.16B, V0.16B, V0.16B
+            Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
+            Opcode |= ((size & 3) << 22);
+            Bits Op = new Bits(Opcode);
+
+            Vector128<float> V0 = MakeVectorE0E1(Z, Z);
+            Vector128<float> V1 = MakeVectorE0E1(A, A);
+            Vector128<float> V2 = MakeVectorE0E1(B, B);
+            AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
+
+            AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
+            AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A));
+            AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B));
+            SimdFp.Shsub_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]);
+
+            Assert.Multiple(() =>
+            {
+                Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
+                Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
+            });
+        }
+
         [Test, Pairwise, Description("SQADD <V><d>, <V><n>, <V><m>")]
         public void Sqadd_S_B_H_S_D([Values(0u)]     uint Rd,
                                     [Values(1u, 0u)] uint Rn,
@@ -2278,13 +2402,75 @@ namespace Ryujinx.Tests.Cpu
             Assert.That(ThreadState.Fpsr, Is.EqualTo((int)Shared.FPSR.ToUInt32()));
         }
 
+        [Test, Pairwise, Description("SRHADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
+        public void Srhadd_V_8B_4H_2S([Values(0u)]     uint Rd,
+                                      [Values(1u, 0u)] uint Rn,
+                                      [Values(2u, 0u)] uint Rm,
+                                      [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
+                                      [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
+                                      [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong B,
+                                      [Values(0b00u, 0b01u, 0b10u)] uint size) // <8B, 4H, 2S>
+        {
+            uint Opcode = 0x0E201400; // SRHADD V0.8B, V0.8B, V0.8B
+            Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
+            Opcode |= ((size & 3) << 22);
+            Bits Op = new Bits(Opcode);
+
+            Vector128<float> V0 = MakeVectorE0E1(Z, Z);
+            Vector128<float> V1 = MakeVectorE0(A);
+            Vector128<float> V2 = MakeVectorE0(B);
+            AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
+
+            AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
+            AArch64.V(1, new Bits(A));
+            AArch64.V(2, new Bits(B));
+            SimdFp.Srhadd_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]);
+
+            Assert.Multiple(() =>
+            {
+                Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
+                Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
+            });
+        }
+
+        [Test, Pairwise, Description("SRHADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
+        public void Srhadd_V_16B_8H_4S([Values(0u)]     uint Rd,
+                                       [Values(1u, 0u)] uint Rn,
+                                       [Values(2u, 0u)] uint Rm,
+                                       [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
+                                       [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
+                                       [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong B,
+                                       [Values(0b00u, 0b01u, 0b10u)] uint size) // <16B, 8H, 4S>
+        {
+            uint Opcode = 0x4E201400; // SRHADD V0.16B, V0.16B, V0.16B
+            Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
+            Opcode |= ((size & 3) << 22);
+            Bits Op = new Bits(Opcode);
+
+            Vector128<float> V0 = MakeVectorE0E1(Z, Z);
+            Vector128<float> V1 = MakeVectorE0E1(A, A);
+            Vector128<float> V2 = MakeVectorE0E1(B, B);
+            AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
+
+            AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
+            AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A));
+            AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B));
+            SimdFp.Srhadd_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]);
+
+            Assert.Multiple(() =>
+            {
+                Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
+                Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
+            });
+        }
+
         [Test, Pairwise, Description("SSUBW{2} <Vd>.<Ta>, <Vn>.<Ta>, <Vm>.<Tb>")]
         public void Ssubw_V_8B8H8H_4H4S4S_2S2D2D([Values(0u)]     uint Rd,
                                                  [Values(1u, 0u)] uint Rn,
                                                  [Values(2u, 0u)] uint Rm,
                                                  [ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z,
-                                                 [ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong A,
-                                                 [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong B,
+                                                 [ValueSource("_4H2S1D_")]   [Random(RndCnt)] ulong A,
+                                                 [ValueSource("_8B4H2S_")]   [Random(RndCnt)] ulong B,
                                                  [Values(0b00u, 0b01u, 0b10u)] uint size) // <8B8H8H, 4H4S4S, 2S2D2D>
         {
             uint Opcode = 0x0E203000; // SSUBW V0.8H, V0.8H, V0.8B
@@ -2314,8 +2500,8 @@ namespace Ryujinx.Tests.Cpu
                                                   [Values(1u, 0u)] uint Rn,
                                                   [Values(2u, 0u)] uint Rm,
                                                   [ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z,
-                                                  [ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong A,
-                                                  [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong B,
+                                                  [ValueSource("_4H2S1D_")]   [Random(RndCnt)] ulong A,
+                                                  [ValueSource("_8B4H2S_")]   [Random(RndCnt)] ulong B,
                                                   [Values(0b00u, 0b01u, 0b10u)] uint size) // <16B8H8H, 8H4S4S, 4S2D2D>
         {
             uint Opcode = 0x4E203000; // SSUBW2 V0.8H, V0.8H, V0.16B
@@ -2870,8 +3056,8 @@ namespace Ryujinx.Tests.Cpu
                                                  [Values(1u, 0u)] uint Rn,
                                                  [Values(2u, 0u)] uint Rm,
                                                  [ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z,
-                                                 [ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong A,
-                                                 [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong B,
+                                                 [ValueSource("_4H2S1D_")]   [Random(RndCnt)] ulong A,
+                                                 [ValueSource("_8B4H2S_")]   [Random(RndCnt)] ulong B,
                                                  [Values(0b00u, 0b01u, 0b10u)] uint size) // <8B8H8H, 4H4S4S, 2S2D2D>
         {
             uint Opcode = 0x2E201000; // UADDW V0.8H, V0.8H, V0.8B
@@ -2901,8 +3087,8 @@ namespace Ryujinx.Tests.Cpu
                                                   [Values(1u, 0u)] uint Rn,
                                                   [Values(2u, 0u)] uint Rm,
                                                   [ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z,
-                                                  [ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong A,
-                                                  [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong B,
+                                                  [ValueSource("_4H2S1D_")]   [Random(RndCnt)] ulong A,
+                                                  [ValueSource("_8B4H2S_")]   [Random(RndCnt)] ulong B,
                                                   [Values(0b00u, 0b01u, 0b10u)] uint size) // <16B8H8H, 8H4S4S, 4S2D2D>
         {
             uint Opcode = 0x6E201000; // UADDW2 V0.8H, V0.8H, V0.16B
@@ -2927,6 +3113,130 @@ namespace Ryujinx.Tests.Cpu
             });
         }
 
+        [Test, Pairwise, Description("UHADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
+        public void Uhadd_V_8B_4H_2S([Values(0u)]     uint Rd,
+                                     [Values(1u, 0u)] uint Rn,
+                                     [Values(2u, 0u)] uint Rm,
+                                     [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
+                                     [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
+                                     [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong B,
+                                     [Values(0b00u, 0b01u, 0b10u)] uint size) // <8B, 4H, 2S>
+        {
+            uint Opcode = 0x2E200400; // UHADD V0.8B, V0.8B, V0.8B
+            Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
+            Opcode |= ((size & 3) << 22);
+            Bits Op = new Bits(Opcode);
+
+            Vector128<float> V0 = MakeVectorE0E1(Z, Z);
+            Vector128<float> V1 = MakeVectorE0(A);
+            Vector128<float> V2 = MakeVectorE0(B);
+            AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
+
+            AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
+            AArch64.V(1, new Bits(A));
+            AArch64.V(2, new Bits(B));
+            SimdFp.Uhadd_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]);
+
+            Assert.Multiple(() =>
+            {
+                Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
+                Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
+            });
+        }
+
+        [Test, Pairwise, Description("UHADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
+        public void Uhadd_V_16B_8H_4S([Values(0u)]     uint Rd,
+                                      [Values(1u, 0u)] uint Rn,
+                                      [Values(2u, 0u)] uint Rm,
+                                      [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
+                                      [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
+                                      [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong B,
+                                      [Values(0b00u, 0b01u, 0b10u)] uint size) // <16B, 8H, 4S>
+        {
+            uint Opcode = 0x6E200400; // UHADD V0.16B, V0.16B, V0.16B
+            Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
+            Opcode |= ((size & 3) << 22);
+            Bits Op = new Bits(Opcode);
+
+            Vector128<float> V0 = MakeVectorE0E1(Z, Z);
+            Vector128<float> V1 = MakeVectorE0E1(A, A);
+            Vector128<float> V2 = MakeVectorE0E1(B, B);
+            AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
+
+            AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
+            AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A));
+            AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B));
+            SimdFp.Uhadd_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]);
+
+            Assert.Multiple(() =>
+            {
+                Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
+                Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
+            });
+        }
+
+        [Test, Pairwise, Description("UHSUB <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
+        public void Uhsub_V_8B_4H_2S([Values(0u)]     uint Rd,
+                                     [Values(1u, 0u)] uint Rn,
+                                     [Values(2u, 0u)] uint Rm,
+                                     [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
+                                     [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
+                                     [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong B,
+                                     [Values(0b00u, 0b01u, 0b10u)] uint size) // <8B, 4H, 2S>
+        {
+            uint Opcode = 0x2E202400; // UHSUB V0.8B, V0.8B, V0.8B
+            Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
+            Opcode |= ((size & 3) << 22);
+            Bits Op = new Bits(Opcode);
+
+            Vector128<float> V0 = MakeVectorE0E1(Z, Z);
+            Vector128<float> V1 = MakeVectorE0(A);
+            Vector128<float> V2 = MakeVectorE0(B);
+            AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
+
+            AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
+            AArch64.V(1, new Bits(A));
+            AArch64.V(2, new Bits(B));
+            SimdFp.Uhsub_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]);
+
+            Assert.Multiple(() =>
+            {
+                Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
+                Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
+            });
+        }
+
+        [Test, Pairwise, Description("UHSUB <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
+        public void Uhsub_V_16B_8H_4S([Values(0u)]     uint Rd,
+                                      [Values(1u, 0u)] uint Rn,
+                                      [Values(2u, 0u)] uint Rm,
+                                      [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
+                                      [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
+                                      [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong B,
+                                      [Values(0b00u, 0b01u, 0b10u)] uint size) // <16B, 8H, 4S>
+        {
+            uint Opcode = 0x6E202400; // UHSUB V0.16B, V0.16B, V0.16B
+            Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
+            Opcode |= ((size & 3) << 22);
+            Bits Op = new Bits(Opcode);
+
+            Vector128<float> V0 = MakeVectorE0E1(Z, Z);
+            Vector128<float> V1 = MakeVectorE0E1(A, A);
+            Vector128<float> V2 = MakeVectorE0E1(B, B);
+            AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
+
+            AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
+            AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A));
+            AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B));
+            SimdFp.Uhsub_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]);
+
+            Assert.Multiple(() =>
+            {
+                Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
+                Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
+            });
+        }
+
         [Test, Pairwise, Description("UQADD <V><d>, <V><n>, <V><m>")]
         public void Uqadd_S_B_H_S_D([Values(0u)]     uint Rd,
                                     [Values(1u, 0u)] uint Rn,
@@ -3137,13 +3447,75 @@ namespace Ryujinx.Tests.Cpu
             Assert.That(ThreadState.Fpsr, Is.EqualTo((int)Shared.FPSR.ToUInt32()));
         }
 
+        [Test, Pairwise, Description("URHADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
+        public void Urhadd_V_8B_4H_2S([Values(0u)]     uint Rd,
+                                      [Values(1u, 0u)] uint Rn,
+                                      [Values(2u, 0u)] uint Rm,
+                                      [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
+                                      [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
+                                      [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong B,
+                                      [Values(0b00u, 0b01u, 0b10u)] uint size) // <8B, 4H, 2S>
+        {
+            uint Opcode = 0x2E201400; // URHADD V0.8B, V0.8B, V0.8B
+            Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
+            Opcode |= ((size & 3) << 22);
+            Bits Op = new Bits(Opcode);
+
+            Vector128<float> V0 = MakeVectorE0E1(Z, Z);
+            Vector128<float> V1 = MakeVectorE0(A);
+            Vector128<float> V2 = MakeVectorE0(B);
+            AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
+
+            AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
+            AArch64.V(1, new Bits(A));
+            AArch64.V(2, new Bits(B));
+            SimdFp.Urhadd_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]);
+
+            Assert.Multiple(() =>
+            {
+                Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
+                Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
+            });
+        }
+
+        [Test, Pairwise, Description("URHADD <Vd>.<T>, <Vn>.<T>, <Vm>.<T>")]
+        public void Urhadd_V_16B_8H_4S([Values(0u)]     uint Rd,
+                                       [Values(1u, 0u)] uint Rn,
+                                       [Values(2u, 0u)] uint Rm,
+                                       [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong Z,
+                                       [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong A,
+                                       [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong B,
+                                       [Values(0b00u, 0b01u, 0b10u)] uint size) // <16B, 8H, 4S>
+        {
+            uint Opcode = 0x6E201400; // URHADD V0.16B, V0.16B, V0.16B
+            Opcode |= ((Rm & 31) << 16) | ((Rn & 31) << 5) | ((Rd & 31) << 0);
+            Opcode |= ((size & 3) << 22);
+            Bits Op = new Bits(Opcode);
+
+            Vector128<float> V0 = MakeVectorE0E1(Z, Z);
+            Vector128<float> V1 = MakeVectorE0E1(A, A);
+            Vector128<float> V2 = MakeVectorE0E1(B, B);
+            AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1, V2: V2);
+
+            AArch64.Vpart(0, 0, new Bits(Z)); AArch64.Vpart(0, 1, new Bits(Z));
+            AArch64.Vpart(1, 0, new Bits(A)); AArch64.Vpart(1, 1, new Bits(A));
+            AArch64.Vpart(2, 0, new Bits(B)); AArch64.Vpart(2, 1, new Bits(B));
+            SimdFp.Urhadd_V(Op[30], Op[23, 22], Op[20, 16], Op[9, 5], Op[4, 0]);
+
+            Assert.Multiple(() =>
+            {
+                Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 0).ToUInt64()));
+                Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64()));
+            });
+        }
+
         [Test, Pairwise, Description("USUBW{2} <Vd>.<Ta>, <Vn>.<Ta>, <Vm>.<Tb>")]
         public void Usubw_V_8B8H8H_4H4S4S_2S2D2D([Values(0u)]     uint Rd,
                                                  [Values(1u, 0u)] uint Rn,
                                                  [Values(2u, 0u)] uint Rm,
                                                  [ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z,
-                                                 [ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong A,
-                                                 [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong B,
+                                                 [ValueSource("_4H2S1D_")]   [Random(RndCnt)] ulong A,
+                                                 [ValueSource("_8B4H2S_")]   [Random(RndCnt)] ulong B,
                                                  [Values(0b00u, 0b01u, 0b10u)] uint size) // <8B8H8H, 4H4S4S, 2S2D2D>
         {
             uint Opcode = 0x2E203000; // USUBW V0.8H, V0.8H, V0.8B
@@ -3173,8 +3545,8 @@ namespace Ryujinx.Tests.Cpu
                                                   [Values(1u, 0u)] uint Rn,
                                                   [Values(2u, 0u)] uint Rm,
                                                   [ValueSource("_8B4H2S1D_")] [Random(RndCnt)] ulong Z,
-                                                  [ValueSource("_4H2S1D_")] [Random(RndCnt)] ulong A,
-                                                  [ValueSource("_8B4H2S_")] [Random(RndCnt)] ulong B,
+                                                  [ValueSource("_4H2S1D_")]   [Random(RndCnt)] ulong A,
+                                                  [ValueSource("_8B4H2S_")]   [Random(RndCnt)] ulong B,
                                                   [Values(0b00u, 0b01u, 0b10u)] uint size) // <16B8H8H, 8H4S4S, 4S2D2D>
         {
             uint Opcode = 0x6E203000; // USUBW2 V0.8H, V0.8H, V0.16B