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authorriperiperi <rhy3756547@hotmail.com>2020-03-13 23:29:58 +0000
committerGitHub <noreply@github.com>2020-03-14 10:29:58 +1100
commitdd433c1296bbd82e5e42bf8de1731a4eaadcfdb5 (patch)
treea77472d331a7b4af4fd516a5f6de44ca7417376d /Ryujinx.Tests/Cpu/CpuTestSimdLogical32.cs
parentff2bac9c9042ef23437b19a32f3f2b6869cc1274 (diff)
Implement AESMC, AESIMC, AESE, AESD and VEOR AArch32 instructions (#982)
* Add VEOR and AES instructions. * Add tests for crypto instructions. * Update ValueSource name.
Diffstat (limited to 'Ryujinx.Tests/Cpu/CpuTestSimdLogical32.cs')
-rw-r--r--Ryujinx.Tests/Cpu/CpuTestSimdLogical32.cs22
1 files changed, 12 insertions, 10 deletions
diff --git a/Ryujinx.Tests/Cpu/CpuTestSimdLogical32.cs b/Ryujinx.Tests/Cpu/CpuTestSimdLogical32.cs
index 459127de..b6c05b10 100644
--- a/Ryujinx.Tests/Cpu/CpuTestSimdLogical32.cs
+++ b/Ryujinx.Tests/Cpu/CpuTestSimdLogical32.cs
@@ -12,14 +12,16 @@ namespace Ryujinx.Tests.Cpu
#if SimdLogical32
#region "ValueSource (Opcodes)"
- private static uint[] _Vbif_Vbit_Vbsl_Vand_()
+ private static uint[] _Vbif_Vbit_Vbsl_Vand_Vorr_Veor_()
{
return new uint[]
{
0xf3300110u, // VBIF D0, D0, D0
0xf3200110u, // VBIT D0, D0, D0
0xf3100110u, // VBSL D0, D0, D0
- 0xf2000110u // VAND D0, D0, D0
+ 0xf2000110u, // VAND D0, D0, D0
+ 0xf2200110u, // VORR D0, D0, D0
+ 0xf3000110u // VEOR D0, D0, D0
};
}
#endregion
@@ -27,14 +29,14 @@ namespace Ryujinx.Tests.Cpu
private const int RndCnt = 2;
[Test, Pairwise]
- public void Vbif_Vbit_Vbsl_Vand([ValueSource("_Vbif_Vbit_Vbsl_Vand_")] uint opcode,
- [Range(0u, 4u)] uint rd,
- [Range(0u, 4u)] uint rn,
- [Range(0u, 4u)] uint rm,
- [Random(RndCnt)] ulong z,
- [Random(RndCnt)] ulong a,
- [Random(RndCnt)] ulong b,
- [Values] bool q)
+ public void Vbif_Vbit_Vbsl_Vand_Vorr_Veor([ValueSource("_Vbif_Vbit_Vbsl_Vand_Vorr_Veor_")] uint opcode,
+ [Range(0u, 4u)] uint rd,
+ [Range(0u, 4u)] uint rn,
+ [Range(0u, 4u)] uint rm,
+ [Random(RndCnt)] ulong z,
+ [Random(RndCnt)] ulong a,
+ [Random(RndCnt)] ulong b,
+ [Values] bool q)
{
if (q)
{