aboutsummaryrefslogtreecommitdiff
path: root/Ryujinx.Tests/Cpu/CpuTestSimdLogical32.cs
diff options
context:
space:
mode:
authorgdkchan <gab.dark.100@gmail.com>2021-06-23 18:21:23 -0300
committerGitHub <noreply@github.com>2021-06-23 23:21:23 +0200
commitab9d4b862d6ef5bc67cbb1afe0e1f55f24c028fa (patch)
tree0552530bbad4fabeeede6fd4935e6af482fee3ed /Ryujinx.Tests/Cpu/CpuTestSimdLogical32.cs
parent49edf14a3ea3139e3f5307007819b373425a3843 (diff)
Implement VORN (register) Arm32 instruction (#2396)
Diffstat (limited to 'Ryujinx.Tests/Cpu/CpuTestSimdLogical32.cs')
-rw-r--r--Ryujinx.Tests/Cpu/CpuTestSimdLogical32.cs19
1 files changed, 10 insertions, 9 deletions
diff --git a/Ryujinx.Tests/Cpu/CpuTestSimdLogical32.cs b/Ryujinx.Tests/Cpu/CpuTestSimdLogical32.cs
index 0818b680..b7cb2636 100644
--- a/Ryujinx.Tests/Cpu/CpuTestSimdLogical32.cs
+++ b/Ryujinx.Tests/Cpu/CpuTestSimdLogical32.cs
@@ -22,7 +22,7 @@ namespace Ryujinx.Tests.Cpu
#endregion
#region "ValueSource (Opcodes)"
- private static uint[] _Vbic_Vbif_Vbit_Vbsl_Vand_Vorr_Veor_I_()
+ private static uint[] _Vbic_Vbif_Vbit_Vbsl_Vand_Vorn_Vorr_Veor_I_()
{
return new uint[]
{
@@ -31,6 +31,7 @@ namespace Ryujinx.Tests.Cpu
0xf3200110u, // VBIT D0, D0, D0
0xf3100110u, // VBSL D0, D0, D0
0xf2000110u, // VAND D0, D0, D0
+ 0xf2300110u, // VORN D0, D0, D0
0xf2200110u, // VORR D0, D0, D0
0xf3000110u // VEOR D0, D0, D0
};
@@ -51,14 +52,14 @@ namespace Ryujinx.Tests.Cpu
private const int RndCnt = 2;
[Test, Pairwise]
- public void Vbic_Vbif_Vbit_Vbsl_Vand_Vorr_Veor_I([ValueSource("_Vbic_Vbif_Vbit_Vbsl_Vand_Vorr_Veor_I_")] uint opcode,
- [Range(0u, 5u)] uint rd,
- [Range(0u, 5u)] uint rn,
- [Range(0u, 5u)] uint rm,
- [Values(ulong.MinValue, ulong.MaxValue)] [Random(RndCnt)] ulong z,
- [Values(ulong.MinValue, ulong.MaxValue)] [Random(RndCnt)] ulong a,
- [Values(ulong.MinValue, ulong.MaxValue)] [Random(RndCnt)] ulong b,
- [Values] bool q)
+ public void Vbic_Vbif_Vbit_Vbsl_Vand_Vorn_Vorr_Veor_I([ValueSource("_Vbic_Vbif_Vbit_Vbsl_Vand_Vorn_Vorr_Veor_I_")] uint opcode,
+ [Range(0u, 5u)] uint rd,
+ [Range(0u, 5u)] uint rn,
+ [Range(0u, 5u)] uint rm,
+ [Values(ulong.MinValue, ulong.MaxValue)] [Random(RndCnt)] ulong z,
+ [Values(ulong.MinValue, ulong.MaxValue)] [Random(RndCnt)] ulong a,
+ [Values(ulong.MinValue, ulong.MaxValue)] [Random(RndCnt)] ulong b,
+ [Values] bool q)
{
if (q)
{