Implement the remaining tests for Simd and Fp instructions of data processing type. Small opts. for Fmov_Ftoi/1 & Fmov_Itof/1 Insts. (#709)

* Update CpuTestSimdShImm.cs

* Update OpCodeTable.cs

* Update CpuTestSimdReg.cs

* Add Ins_Gp & Ins_V Tests.

Improve Smov_S & Umov_S Tests.

* Add Bic_Vi & Orr_Vi Tests.

* OpTable Fixes for Bic_Vi & Orr_Vi Insts.

* Add Saddlv_V & Uaddlv_V Tests.

* Nit.

* Add Smull_V & Umull_V Tests.

Improve Simd Permute Tests.

* Nit.

* Add Fcsel_S Test.

* Add Fnmadd_S, Fnmsub_S & Fnmul_S Tests.

* Fmov_V -> Fmov_Vi

* OpTable Fixes for Fmov_Si & Fmov_Vi Insts.

* Add Fmov_Vi Test.

* Add Fmov_S Test.

* Add Fmov_Si Test.

Add new test category SimdFmov.

* Nit.

* OpTable Fixes for Fmov_Ftoi/1 & Fmov_Itof/1 Insts.

* Small opts. for Fmov_Ftoi/1 & Fmov_Itof/1 Insts.

Small simpl. for Smov_S Inst.
Remove unnecessary method EmitIntZeroUpperIfNeeded.

* Add Fmov_Ftoi/1 & Fmov_Itof/1 Tests.

1 files changed, 142 insertions, 12 deletions

diff --git a/Ryujinx.Tests/Cpu/CpuTestSimdImm.cs b/Ryujinx.Tests/Cpu/CpuTestSimdImm.cs
index bb6e1173..ce8f63bc 100644
--- a/Ryujinx.Tests/Cpu/CpuTestSimdImm.cs
+++ b/Ryujinx.Tests/Cpu/CpuTestSimdImm.cs
@@ -47,6 +47,18 @@ namespace Ryujinx.Tests.Cpu
 #endregion
 
 #region "ValueSource (Types)"
+        private static ulong[] _2S_()
+        {
+            return new ulong[] { 0x0000000000000000ul, 0x7FFFFFFF7FFFFFFFul,
+                                 0x8000000080000000ul, 0xFFFFFFFFFFFFFFFFul };
+        }
+
+        private static ulong[] _4H_()
+        {
+            return new ulong[] { 0x0000000000000000ul, 0x7FFF7FFF7FFF7FFFul,
+                                 0x8000800080008000ul, 0xFFFFFFFFFFFFFFFFul };
+        }
+
         private static IEnumerable<byte> _8BIT_IMM_()
         {
             yield return 0x00;
@@ -79,6 +91,48 @@ namespace Ryujinx.Tests.Cpu
 #endregion
 
 #region "ValueSource (Opcodes)"
+        private static uint[] _Bic_Orr_Vi_16bit_()
+        {
+            return new uint[]
+            {
+                0x2F009400u, // BIC V0.4H, #0
+                0x0F009400u  // ORR V0.4H, #0
+            };
+        }
+
+        private static uint[] _Bic_Orr_Vi_32bit_()
+        {
+            return new uint[]
+            {
+                0x2F001400u, // BIC V0.2S, #0
+                0x0F001400u  // ORR V0.2S, #0
+            };
+        }
+
+        private static uint[] _F_Mov_Vi_2S_()
+        {
+            return new uint[]
+            {
+                0x0F00F400u // FMOV V0.2S, #2.0
+            };
+        }
+
+        private static uint[] _F_Mov_Vi_4S_()
+        {
+            return new uint[]
+            {
+                0x4F00F400u // FMOV V0.4S, #2.0
+            };
+        }
+
+        private static uint[] _F_Mov_Vi_2D_()
+        {
+            return new uint[]
+            {
+                0x6F00F400u // FMOV V0.2D, #2.0
+            };
+        }
+
         private static uint[] _Movi_V_8bit_()
         {
             return new uint[]
@@ -131,19 +185,105 @@ namespace Ryujinx.Tests.Cpu
         }
 #endregion
 
+        private const int RndCnt      = 2;
         private const int RndCntImm8  = 2;
         private const int RndCntImm64 = 2;
 
         [Test, Pairwise]
+        public void Bic_Orr_Vi_16bit([ValueSource("_Bic_Orr_Vi_16bit_")] uint opcodes,
+                                     [ValueSource("_4H_")] [Random(RndCnt)] ulong z,
+                                     [ValueSource("_8BIT_IMM_")] byte imm8,
+                                     [Values(0b0u, 0b1u)] uint amount, // <0, 8>
+                                     [Values(0b0u, 0b1u)] uint q)      // <4H, 8H>
+        {
+            uint abc   = (imm8 & 0xE0u) >> 5;
+            uint defgh = (imm8 & 0x1Fu);
+
+            opcodes |= (abc << 16) | (defgh << 5);
+            opcodes |= ((amount & 1) << 13);
+            opcodes |= ((q & 1) << 30);
+
+            Vector128<float> v0 = MakeVectorE0E1(z, z);
+
+            SingleOpcode(opcodes, v0: v0);
+
+            CompareAgainstUnicorn();
+        }
+
+        [Test, Pairwise]
+        public void Bic_Orr_Vi_32bit([ValueSource("_Bic_Orr_Vi_32bit_")] uint opcodes,
+                                     [ValueSource("_2S_")] [Random(RndCnt)] ulong z,
+                                     [ValueSource("_8BIT_IMM_")] byte imm8,
+                                     [Values(0b00u, 0b01u, 0b10u, 0b11u)] uint amount, // <0, 8, 16, 24>
+                                     [Values(0b0u, 0b1u)] uint q)                      // <2S, 4S>
+        {
+            uint abc   = (imm8 & 0xE0u) >> 5;
+            uint defgh = (imm8 & 0x1Fu);
+
+            opcodes |= (abc << 16) | (defgh << 5);
+            opcodes |= ((amount & 3) << 13);
+            opcodes |= ((q & 1) << 30);
+
+            Vector128<float> v0 = MakeVectorE0E1(z, z);
+
+            SingleOpcode(opcodes, v0: v0);
+
+            CompareAgainstUnicorn();
+        }
+
+        [Test, Pairwise] [Explicit]
+        public void F_Mov_Vi_2S([ValueSource("_F_Mov_Vi_2S_")] uint opcodes,
+                                [Range(0u, 255u, 1u)] uint abcdefgh)
+        {
+            uint abc   = (abcdefgh & 0xE0u) >> 5;
+            uint defgh = (abcdefgh & 0x1Fu);
+
+            opcodes |= (abc << 16) | (defgh << 5);
+
+            ulong z = TestContext.CurrentContext.Random.NextULong();
+            Vector128<float> v0 = MakeVectorE1(z);
+
+            SingleOpcode(opcodes, v0: v0);
+
+            CompareAgainstUnicorn();
+        }
+
+        [Test, Pairwise] [Explicit]
+        public void F_Mov_Vi_4S([ValueSource("_F_Mov_Vi_4S_")] uint opcodes,
+                                [Range(0u, 255u, 1u)] uint abcdefgh)
+        {
+            uint abc   = (abcdefgh & 0xE0u) >> 5;
+            uint defgh = (abcdefgh & 0x1Fu);
+
+            opcodes |= (abc << 16) | (defgh << 5);
+
+            SingleOpcode(opcodes);
+
+            CompareAgainstUnicorn();
+        }
+
+        [Test, Pairwise] [Explicit]
+        public void F_Mov_Vi_2D([ValueSource("_F_Mov_Vi_2D_")] uint opcodes,
+                                [Range(0u, 255u, 1u)] uint abcdefgh)
+        {
+            uint abc   = (abcdefgh & 0xE0u) >> 5;
+            uint defgh = (abcdefgh & 0x1Fu);
+
+            opcodes |= (abc << 16) | (defgh << 5);
+
+            SingleOpcode(opcodes);
+
+            CompareAgainstUnicorn();
+        }
+
+        [Test, Pairwise]
         public void Movi_V_8bit([ValueSource("_Movi_V_8bit_")] uint opcodes,
-                                [Values(0u)] uint rd,
                                 [ValueSource("_8BIT_IMM_")] byte imm8,
                                 [Values(0b0u, 0b1u)] uint q) // <8B, 16B>
         {
             uint abc   = (imm8 & 0xE0u) >> 5;
             uint defgh = (imm8 & 0x1Fu);
 
-            opcodes |= ((rd & 31) << 0);
             opcodes |= (abc << 16) | (defgh << 5);
             opcodes |= ((q & 1) << 30);
 
@@ -157,7 +297,6 @@ namespace Ryujinx.Tests.Cpu
 
         [Test, Pairwise]
         public void Movi_Mvni_V_16bit_shifted_imm([ValueSource("_Movi_Mvni_V_16bit_shifted_imm_")] uint opcodes,
-                                                  [Values(0u)] uint rd,
                                                   [ValueSource("_8BIT_IMM_")] byte imm8,
                                                   [Values(0b0u, 0b1u)] uint amount, // <0, 8>
                                                   [Values(0b0u, 0b1u)] uint q)      // <4H, 8H>
@@ -165,7 +304,6 @@ namespace Ryujinx.Tests.Cpu
             uint abc   = (imm8 & 0xE0u) >> 5;
             uint defgh = (imm8 & 0x1Fu);
 
-            opcodes |= ((rd & 31) << 0);
             opcodes |= (abc << 16) | (defgh << 5);
             opcodes |= ((amount & 1) << 13);
             opcodes |= ((q & 1) << 30);
@@ -180,7 +318,6 @@ namespace Ryujinx.Tests.Cpu
 
         [Test, Pairwise]
         public void Movi_Mvni_V_32bit_shifted_imm([ValueSource("_Movi_Mvni_V_32bit_shifted_imm_")] uint opcodes,
-                                                  [Values(0u)] uint rd,
                                                   [ValueSource("_8BIT_IMM_")] byte imm8,
                                                   [Values(0b00u, 0b01u, 0b10u, 0b11u)] uint amount, // <0, 8, 16, 24>
                                                   [Values(0b0u, 0b1u)] uint q)                      // <2S, 4S>
@@ -188,7 +325,6 @@ namespace Ryujinx.Tests.Cpu
             uint abc   = (imm8 & 0xE0u) >> 5;
             uint defgh = (imm8 & 0x1Fu);
 
-            opcodes |= ((rd & 31) << 0);
             opcodes |= (abc << 16) | (defgh << 5);
             opcodes |= ((amount & 3) << 13);
             opcodes |= ((q & 1) << 30);
@@ -203,7 +339,6 @@ namespace Ryujinx.Tests.Cpu
 
         [Test, Pairwise]
         public void Movi_Mvni_V_32bit_shifting_ones([ValueSource("_Movi_Mvni_V_32bit_shifting_ones_")] uint opcodes,
-                                                    [Values(0u)] uint rd,
                                                     [ValueSource("_8BIT_IMM_")] byte imm8,
                                                     [Values(0b0u, 0b1u)] uint amount, // <8, 16>
                                                     [Values(0b0u, 0b1u)] uint q)      // <2S, 4S>
@@ -211,7 +346,6 @@ namespace Ryujinx.Tests.Cpu
             uint abc   = (imm8 & 0xE0u) >> 5;
             uint defgh = (imm8 & 0x1Fu);
 
-            opcodes |= ((rd & 31) << 0);
             opcodes |= (abc << 16) | (defgh << 5);
             opcodes |= ((amount & 1) << 12);
             opcodes |= ((q & 1) << 30);
@@ -226,7 +360,6 @@ namespace Ryujinx.Tests.Cpu
 
         [Test, Pairwise]
         public void Movi_V_64bit_scalar([ValueSource("_Movi_V_64bit_scalar_")] uint opcodes,
-                                        [Values(0u)] uint rd,
                                         [ValueSource("_64BIT_IMM_")] ulong imm)
         {
             byte imm8 = ShrinkImm64(imm);
@@ -234,7 +367,6 @@ namespace Ryujinx.Tests.Cpu
             uint abc   = (imm8 & 0xE0u) >> 5;
             uint defgh = (imm8 & 0x1Fu);
 
-            opcodes |= ((rd & 31) << 0);
             opcodes |= (abc << 16) | (defgh << 5);
 
             ulong z = TestContext.CurrentContext.Random.NextULong();
@@ -247,7 +379,6 @@ namespace Ryujinx.Tests.Cpu
 
         [Test, Pairwise]
         public void Movi_V_64bit_vector([ValueSource("_Movi_V_64bit_vector_")] uint opcodes,
-                                        [Values(0u)] uint rd,
                                         [ValueSource("_64BIT_IMM_")] ulong imm)
         {
             byte imm8 = ShrinkImm64(imm);
@@ -255,7 +386,6 @@ namespace Ryujinx.Tests.Cpu
             uint abc   = (imm8 & 0xE0u) >> 5;
             uint defgh = (imm8 & 0x1Fu);
 
-            opcodes |= ((rd & 31) << 0);
             opcodes |= (abc << 16) | (defgh << 5);
 
             SingleOpcode(opcodes);