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| author | LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com> | 2019-06-30 01:02:48 +0200 |
|---|---|---|
| committer | gdkchan <gab.dark.100@gmail.com> | 2019-06-29 20:02:48 -0300 |
| commit | 10c74182babaf8cf6bedaeffd64c3109df4ea816 (patch) | |
| tree | ee55c64d3a022e322f995e129187251583027aae /Ryujinx.Tests/Cpu/CpuTestSimdFmov.cs | |
| parent | ba86a5d7f3aa0127c4732c739af3f6086fb6acd9 (diff) | |
Implement the remaining tests for Simd and Fp instructions of data processing type. Small opts. for Fmov_Ftoi/1 & Fmov_Itof/1 Insts. (#709)
* Update CpuTestSimdShImm.cs
* Update OpCodeTable.cs
* Update CpuTestSimdReg.cs
* Add Ins_Gp & Ins_V Tests.
Improve Smov_S & Umov_S Tests.
* Add Bic_Vi & Orr_Vi Tests.
* OpTable Fixes for Bic_Vi & Orr_Vi Insts.
* Add Saddlv_V & Uaddlv_V Tests.
* Nit.
* Add Smull_V & Umull_V Tests.
Improve Simd Permute Tests.
* Nit.
* Add Fcsel_S Test.
* Add Fnmadd_S, Fnmsub_S & Fnmul_S Tests.
* Fmov_V -> Fmov_Vi
* OpTable Fixes for Fmov_Si & Fmov_Vi Insts.
* Add Fmov_Vi Test.
* Add Fmov_S Test.
* Add Fmov_Si Test.
Add new test category SimdFmov.
* Nit.
* OpTable Fixes for Fmov_Ftoi/1 & Fmov_Itof/1 Insts.
* Small opts. for Fmov_Ftoi/1 & Fmov_Itof/1 Insts.
Small simpl. for Smov_S Inst.
Remove unnecessary method EmitIntZeroUpperIfNeeded.
* Add Fmov_Ftoi/1 & Fmov_Itof/1 Tests.
Diffstat (limited to 'Ryujinx.Tests/Cpu/CpuTestSimdFmov.cs')
| -rw-r--r-- | Ryujinx.Tests/Cpu/CpuTestSimdFmov.cs | 61 |
1 files changed, 61 insertions, 0 deletions
diff --git a/Ryujinx.Tests/Cpu/CpuTestSimdFmov.cs b/Ryujinx.Tests/Cpu/CpuTestSimdFmov.cs new file mode 100644 index 00000000..a7e0e0f9 --- /dev/null +++ b/Ryujinx.Tests/Cpu/CpuTestSimdFmov.cs @@ -0,0 +1,61 @@ +#define SimdFmov + +using NUnit.Framework; + +using System.Runtime.Intrinsics; + +namespace Ryujinx.Tests.Cpu +{ + [Category("SimdFmov")] + public sealed class CpuTestSimdFmov : CpuTest + { +#if SimdFmov + +#region "ValueSource" + private static uint[] _F_Mov_Si_S_() + { + return new uint[] + { + 0x1E201000u // FMOV S0, #2.0 + }; + } + + private static uint[] _F_Mov_Si_D_() + { + return new uint[] + { + 0x1E601000u // FMOV D0, #2.0 + }; + } +#endregion + + [Test, Pairwise] [Explicit] + public void F_Mov_Si_S([ValueSource("_F_Mov_Si_S_")] uint opcodes, + [Range(0u, 255u, 1u)] uint imm8) + { + opcodes |= ((imm8 & 0xFFu) << 13); + + ulong z = TestContext.CurrentContext.Random.NextULong(); + Vector128<float> v0 = MakeVectorE0E1(z, z); + + SingleOpcode(opcodes, v0: v0); + + CompareAgainstUnicorn(); + } + + [Test, Pairwise] [Explicit] + public void F_Mov_Si_D([ValueSource("_F_Mov_Si_D_")] uint opcodes, + [Range(0u, 255u, 1u)] uint imm8) + { + opcodes |= ((imm8 & 0xFFu) << 13); + + ulong z = TestContext.CurrentContext.Random.NextULong(); + Vector128<float> v0 = MakeVectorE1(z); + + SingleOpcode(opcodes, v0: v0); + + CompareAgainstUnicorn(); + } +#endif + } +} |
