diff options
| author | LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com> | 2018-10-28 23:27:50 +0100 |
|---|---|---|
| committer | gdkchan <gab.dark.100@gmail.com> | 2018-10-28 19:27:50 -0300 |
| commit | b956bbc32c7f9fdffebfd9a9416e8e0a2a588abd (patch) | |
| tree | 7769acbc7d7c1f747642b2efb955e146ff8b923a /Ryujinx.Tests/Cpu/CpuTestSimd.cs | |
| parent | 111d14f74aca5e6467473ec73ab0825b9c0b4db1 (diff) | |
Add SHA1C, SHA1H, SHA1M, SHA1P, SHA1SU0, SHA1SU1 and Isb instructions; add 6 Tests (closed box). (#483)
* Update AOpCodeTable.cs
* Update AInstEmitSystem.cs
* Update AInstEmitSimdHash.cs
* Update ASoftFallback.cs
* Update CpuTestSimdReg.cs
* Update CpuTestSimd.cs
Diffstat (limited to 'Ryujinx.Tests/Cpu/CpuTestSimd.cs')
| -rw-r--r-- | Ryujinx.Tests/Cpu/CpuTestSimd.cs | 44 |
1 files changed, 39 insertions, 5 deletions
diff --git a/Ryujinx.Tests/Cpu/CpuTestSimd.cs b/Ryujinx.Tests/Cpu/CpuTestSimd.cs index 795d649a..3bb24f3a 100644 --- a/Ryujinx.Tests/Cpu/CpuTestSimd.cs +++ b/Ryujinx.Tests/Cpu/CpuTestSimd.cs @@ -371,6 +371,23 @@ namespace Ryujinx.Tests.Cpu 0x6EE1F800u // FSQRT V0.2D, V0.2D }; } + + private static uint[] _Sha1h_Sha1su1_V_() + { + return new uint[] + { + 0x5E280800u, // SHA1H S0, S0 + 0x5E281800u // SHA1SU1 V0.4S, V0.4S + }; + } + + private static uint[] _Sha256su0_V_() + { + return new uint[] + { + 0x5E282800u // SHA256SU0 V0.4S, V0.4S + }; + } #endregion private const int RndCnt = 2; @@ -1435,19 +1452,36 @@ namespace Ryujinx.Tests.Cpu CompareAgainstUnicorn(); } - [Test, Pairwise, Description("SHA256SU0 <Vd>.4S, <Vn>.4S")] - public void Sha256su0_V([Values(0u)] uint Rd, + [Test, Pairwise] + public void Sha1h_Sha1su1_V([ValueSource("_Sha1h_Sha1su1_V_")] uint Opcodes, + [Values(0u)] uint Rd, + [Values(1u, 0u)] uint Rn, + [Random(RndCnt / 2)] ulong Z0, [Random(RndCnt / 2)] ulong Z1, + [Random(RndCnt / 2)] ulong A0, [Random(RndCnt / 2)] ulong A1) + { + Opcodes |= ((Rn & 31) << 5) | ((Rd & 31) << 0); + + Vector128<float> V0 = MakeVectorE0E1(Z0, Z1); + Vector128<float> V1 = MakeVectorE0E1(A0, A1); + + AThreadState ThreadState = SingleOpcode(Opcodes, V0: V0, V1: V1); + + CompareAgainstUnicorn(); + } + + [Test, Pairwise] + public void Sha256su0_V([ValueSource("_Sha256su0_V_")] uint Opcodes, + [Values(0u)] uint Rd, [Values(1u, 0u)] uint Rn, [Random(RndCnt / 2)] ulong Z0, [Random(RndCnt / 2)] ulong Z1, [Random(RndCnt / 2)] ulong A0, [Random(RndCnt / 2)] ulong A1) { - uint Opcode = 0x5E282800; // SHA256SU0 V0.4S, V0.4S - Opcode |= ((Rn & 31) << 5) | ((Rd & 31) << 0); + Opcodes |= ((Rn & 31) << 5) | ((Rd & 31) << 0); Vector128<float> V0 = MakeVectorE0E1(Z0, Z1); Vector128<float> V1 = MakeVectorE0E1(A0, A1); - AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); + AThreadState ThreadState = SingleOpcode(Opcodes, V0: V0, V1: V1); CompareAgainstUnicorn(); } |