diff options
| author | LDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com> | 2018-06-30 17:40:41 +0200 |
|---|---|---|
| committer | gdkchan <gab.dark.100@gmail.com> | 2018-06-30 12:40:41 -0300 |
| commit | 53934e88727b3d86ccb5ac08a489b28c8f7fc991 (patch) | |
| tree | 39a3a5bb819b4999db6368125f345013b00ef88f /Ryujinx.Tests/Cpu/CpuTestSimd.cs | |
| parent | edfd4bc860e05698946605c740fdb5857d64e917 (diff) | |
Add Saba_V, Sabal_V, Sabd_V, Sabdl_V, Uaba_V, Uabal_V; Update Uabd_V, Uabdl_V. Add 16 tests. (#204)
* Update AOpCodeTable.cs
* Update AInstEmitSimdArithmetic.cs
* Update AInstEmitSimdHelper.cs
* Update Instructions.cs
* Update CpuTest.cs
* Update CpuTestSimd.cs
* Update CpuTestSimdReg.cs
Diffstat (limited to 'Ryujinx.Tests/Cpu/CpuTestSimd.cs')
| -rw-r--r-- | Ryujinx.Tests/Cpu/CpuTestSimd.cs | 18 |
1 files changed, 9 insertions, 9 deletions
diff --git a/Ryujinx.Tests/Cpu/CpuTestSimd.cs b/Ryujinx.Tests/Cpu/CpuTestSimd.cs index 100f6e0a..8bfa7e7c 100644 --- a/Ryujinx.Tests/Cpu/CpuTestSimd.cs +++ b/Ryujinx.Tests/Cpu/CpuTestSimd.cs @@ -834,8 +834,8 @@ namespace Ryujinx.Tests.Cpu Opcode |= ((size & 3) << 22); Bits Op = new Bits(Opcode); - ulong _X0 = TestContext.CurrentContext.Random.NextULong(); - Vector128<float> V0 = MakeVectorE0(_X0); + ulong _E0 = TestContext.CurrentContext.Random.NextULong(); + Vector128<float> V0 = MakeVectorE0(_E0); Vector128<float> V1 = MakeVectorE0E1(A0, A1); AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); @@ -845,7 +845,7 @@ namespace Ryujinx.Tests.Cpu Assert.Multiple(() => { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(_X0)); + Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(_E0)); Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); }); Assert.That(((ThreadState.Fpsr >> 27) & 1) != 0, Is.EqualTo(Shared.FPSR[27])); @@ -910,8 +910,8 @@ namespace Ryujinx.Tests.Cpu Opcode |= ((size & 3) << 22); Bits Op = new Bits(Opcode); - ulong _X0 = TestContext.CurrentContext.Random.NextULong(); - Vector128<float> V0 = MakeVectorE0(_X0); + ulong _E0 = TestContext.CurrentContext.Random.NextULong(); + Vector128<float> V0 = MakeVectorE0(_E0); Vector128<float> V1 = MakeVectorE0E1(A0, A1); AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); @@ -921,7 +921,7 @@ namespace Ryujinx.Tests.Cpu Assert.Multiple(() => { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(_X0)); + Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(_E0)); Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); }); Assert.That(((ThreadState.Fpsr >> 27) & 1) != 0, Is.EqualTo(Shared.FPSR[27])); @@ -986,8 +986,8 @@ namespace Ryujinx.Tests.Cpu Opcode |= ((size & 3) << 22); Bits Op = new Bits(Opcode); - ulong _X0 = TestContext.CurrentContext.Random.NextULong(); - Vector128<float> V0 = MakeVectorE0(_X0); + ulong _E0 = TestContext.CurrentContext.Random.NextULong(); + Vector128<float> V0 = MakeVectorE0(_E0); Vector128<float> V1 = MakeVectorE0E1(A0, A1); AThreadState ThreadState = SingleOpcode(Opcode, V0: V0, V1: V1); @@ -997,7 +997,7 @@ namespace Ryujinx.Tests.Cpu Assert.Multiple(() => { - Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(_X0)); + Assert.That(GetVectorE0(ThreadState.V0), Is.EqualTo(_E0)); Assert.That(GetVectorE1(ThreadState.V0), Is.EqualTo(AArch64.Vpart(64, 0, 1).ToUInt64())); }); Assert.That(((ThreadState.Fpsr >> 27) & 1) != 0, Is.EqualTo(Shared.FPSR[27])); |