aboutsummaryrefslogtreecommitdiff
path: root/Ryujinx.Tests/Cpu/CpuTestAlu.cs
diff options
context:
space:
mode:
authorLDj3SNuD <35856442+LDj3SNuD@users.noreply.github.com>2018-02-23 13:29:20 +0100
committergdkchan <gab.dark.100@gmail.com>2018-02-23 09:29:20 -0300
commitf09a0082bf86e5e03e8a86c4c72f1794bb664534 (patch)
treefb8cc614256e4dc69266300c43bd50b1f19273a5 /Ryujinx.Tests/Cpu/CpuTestAlu.cs
parent0ff5ec5cb50cd4afd65102434df277656956e868 (diff)
Review of cpu tests and creation of a class for mixed cpu tests. (#35)
* Update CpuTest.cs * Update CpuTestAlu.cs * Update CpuTestScalar.cs * Update CpuTestSimdMove.cs * Create CpuTestMisc.cs * Update CpuTest.cs * Update CpuTestScalar.cs * Update CpuTest.cs * Update CpuTestAlu.cs * Update CpuTestMisc.cs * Update CpuTestScalar.cs
Diffstat (limited to 'Ryujinx.Tests/Cpu/CpuTestAlu.cs')
-rw-r--r--Ryujinx.Tests/Cpu/CpuTestAlu.cs35
1 files changed, 16 insertions, 19 deletions
diff --git a/Ryujinx.Tests/Cpu/CpuTestAlu.cs b/Ryujinx.Tests/Cpu/CpuTestAlu.cs
index a05c0b19..fd535725 100644
--- a/Ryujinx.Tests/Cpu/CpuTestAlu.cs
+++ b/Ryujinx.Tests/Cpu/CpuTestAlu.cs
@@ -1,10 +1,9 @@
-using ChocolArm64.State;
+using ChocolArm64.State;
using NUnit.Framework;
namespace Ryujinx.Tests.Cpu
{
- [TestFixture]
- public partial class CpuTest
+ public class CpuTestAlu : CpuTest
{
[Test]
public void Add()
@@ -14,25 +13,17 @@ namespace Ryujinx.Tests.Cpu
Assert.AreEqual(3, ThreadState.X0);
}
- [Test]
- public void Ands()
+ [TestCase(0xFFFFFFFFu, 0xFFFFFFFFu, 0xFFFFFFFFul, true, false)]
+ [TestCase(0xFFFFFFFFu, 0x00000000u, 0x00000000ul, false, true)]
+ [TestCase(0x12345678u, 0x7324A993u, 0x12240010ul, false, false)]
+ public void Ands(uint A, uint B, ulong Result, bool Negative, bool Zero)
{
// ANDS W0, W1, W2
uint Opcode = 0x6A020020;
- var tests = new[]
- {
- new { W1 = 0xFFFFFFFFul, W2 = 0xFFFFFFFFul, Result = 0xFFFFFFFFul, Negative = true, Zero = false },
- new { W1 = 0xFFFFFFFFul, W2 = 0x00000000ul, Result = 0x00000000ul, Negative = false, Zero = true },
- new { W1 = 0x12345678ul, W2 = 0x7324A993ul, Result = 0x12240010ul, Negative = false, Zero = false },
- };
-
- foreach (var test in tests)
- {
- AThreadState ThreadState = SingleOpcode(Opcode, X1: test.W1, X2: test.W2);
- Assert.AreEqual(test.Result, ThreadState.X0);
- Assert.AreEqual(test.Negative, ThreadState.Negative);
- Assert.AreEqual(test.Zero, ThreadState.Zero);
- }
+ AThreadState ThreadState = SingleOpcode(Opcode, X1: A, X2: B);
+ Assert.AreEqual(Result, ThreadState.X0);
+ Assert.AreEqual(Negative, ThreadState.Negative);
+ Assert.AreEqual(Zero, ThreadState.Zero);
}
[Test]
@@ -40,8 +31,14 @@ namespace Ryujinx.Tests.Cpu
{
// ORR W0, WZR, #0x01010101
Assert.AreEqual(0x01010101, SingleOpcode(0x3200C3E0).X0);
+
+ Reset();
+
// ORR W1, WZR, #0x00F000F0
Assert.AreEqual(0x00F000F0, SingleOpcode(0x320C8FE1).X1);
+
+ Reset();
+
// ORR W2, WZR, #1
Assert.AreEqual(0x00000001, SingleOpcode(0x320003E2).X2);
}