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authormerry <git@mary.rs>2022-02-17 22:39:45 +0000
committerGitHub <noreply@github.com>2022-02-17 19:39:45 -0300
commit98e05ee4b7aa8a08088b1f0cd6c581bb50f11395 (patch)
treeaf9cf98afb6c44161fadd87bfe7946c7a4250e47 /Ryujinx.Tests/Cpu/CpuTest32.cs
parent868919e101ba5d5ad1cfccb5017b294fec11c6e3 (diff)
ARMeilleure: Thumb support (All T16 instructions) (#3105)
* Decoders: Add InITBlock argument * OpCodeTable: Minor cleanup * OpCodeTable: Remove existing thumb instruction implementations * OpCodeTable: Prepare for thumb instructions * OpCodeTables: Improve thumb fast lookup * Tests: Prepare for thumb tests * T16: Implement BX * T16: Implement LSL/LSR/ASR (imm) * T16: Implement ADDS, SUBS (reg) * T16: Implement ADDS, SUBS (3-bit immediate) * T16: Implement MOVS, CMP, ADDS, SUBS (8-bit immediate) * T16: Implement ANDS, EORS, LSLS, LSRS, ASRS, ADCS, SBCS, RORS, TST, NEGS, CMP, CMN, ORRS, MULS, BICS, MVNS (low registers) * T16: Implement ADD, CMP, MOV (high reg) * T16: Implement BLX (reg) * T16: Implement LDR (literal) * T16: Implement {LDR,STR}{,H,B,SB,SH} (register) * T16: Implement {LDR,STR}{,B,H} (immediate) * T16: Implement LDR/STR (SP) * T16: Implement ADR * T16: Implement Add to SP (immediate) * T16: Implement ADD/SUB (SP) * T16: Implement SXTH, SXTB, UXTH, UTXB * T16: Implement CBZ, CBNZ * T16: Implement PUSH, POP * T16: Implement REV, REV16, REVSH * T16: Implement NOP * T16: Implement LDM, STM * T16: Implement SVC * T16: Implement B (conditional) * T16: Implement B (unconditional) * T16: Implement IT * fixup! T16: Implement ADD/SUB (SP) * fixup! T16: Implement Add to SP (immediate) * fixup! T16: Implement IT * CpuTestThumb: Add randomized tests * Remove inITBlock argument * Address nits * Use index to handle IfThenBlockState * Reduce line noise * fixup * nit
Diffstat (limited to 'Ryujinx.Tests/Cpu/CpuTest32.cs')
-rw-r--r--Ryujinx.Tests/Cpu/CpuTest32.cs41
1 files changed, 40 insertions, 1 deletions
diff --git a/Ryujinx.Tests/Cpu/CpuTest32.cs b/Ryujinx.Tests/Cpu/CpuTest32.cs
index 5d24af39..7fa9ba09 100644
--- a/Ryujinx.Tests/Cpu/CpuTest32.cs
+++ b/Ryujinx.Tests/Cpu/CpuTest32.cs
@@ -106,6 +106,18 @@ namespace Ryujinx.Tests.Cpu
_currAddress += 4;
}
+ protected void ThumbOpcode(ushort opcode)
+ {
+ _memory.Write(_currAddress, opcode);
+
+ if (_unicornAvailable)
+ {
+ _unicornEmu.MemoryWrite16(_currAddress, opcode);
+ }
+
+ _currAddress += 2;
+ }
+
protected ExecutionContext GetContext() => _context;
protected void SetContext(uint r0 = 0,
@@ -126,7 +138,8 @@ namespace Ryujinx.Tests.Cpu
bool carry = false,
bool zero = false,
bool negative = false,
- int fpscr = 0)
+ int fpscr = 0,
+ bool thumb = false)
{
_context.SetX(0, r0);
_context.SetX(1, r1);
@@ -151,6 +164,8 @@ namespace Ryujinx.Tests.Cpu
SetFpscr((uint)fpscr);
+ _context.SetPstateFlag(PState.TFlag, thumb);
+
if (_unicornAvailable)
{
_unicornEmu.R[0] = r0;
@@ -175,6 +190,8 @@ namespace Ryujinx.Tests.Cpu
_unicornEmu.NegativeFlag = negative;
_unicornEmu.Fpscr = fpscr;
+
+ _unicornEmu.ThumbFlag = thumb;
}
}
@@ -218,6 +235,28 @@ namespace Ryujinx.Tests.Cpu
return GetContext();
}
+ protected ExecutionContext SingleThumbOpcode(ushort opcode,
+ uint r0 = 0,
+ uint r1 = 0,
+ uint r2 = 0,
+ uint r3 = 0,
+ uint sp = 0,
+ bool saturation = false,
+ bool overflow = false,
+ bool carry = false,
+ bool zero = false,
+ bool negative = false,
+ int fpscr = 0,
+ bool runUnicorn = true)
+ {
+ ThumbOpcode(opcode);
+ ThumbOpcode(0x4770); // BX LR
+ SetContext(r0, r1, r2, r3, sp, default, default, default, default, default, default, default, default, saturation, overflow, carry, zero, negative, fpscr, thumb: true);
+ ExecuteOpcodes(runUnicorn);
+
+ return GetContext();
+ }
+
protected void SetWorkingMemory(uint offset, byte[] data)
{
_memory.Write(DataBaseAddress + offset, data);