Add a new JIT compiler for CPU code (#693)

* Start of the ARMeilleure project

* Refactoring around the old IRAdapter, now renamed to PreAllocator

* Optimize the LowestBitSet method

* Add CLZ support and fix CLS implementation

* Add missing Equals and GetHashCode overrides on some structs, misc small tweaks

* Implement the ByteSwap IR instruction, and some refactoring on the assembler

* Implement the DivideUI IR instruction and fix 64-bits IDIV

* Correct constant operand type on CSINC

* Move division instructions implementation to InstEmitDiv

* Fix destination type for the ConditionalSelect IR instruction

* Implement UMULH and SMULH, with new IR instructions

* Fix some issues with shift instructions

* Fix constant types for BFM instructions

* Fix up new tests using the new V128 struct

* Update tests

* Move DIV tests to a separate file

* Add support for calls, and some instructions that depends on them

* Start adding support for SIMD & FP types, along with some of the related ARM instructions

* Fix some typos and the divide instruction with FP operands

* Fix wrong method call on Clz_V

* Implement ARM FP & SIMD move instructions, Saddlv_V, and misc. fixes

* Implement SIMD logical instructions and more misc. fixes

* Fix PSRAD x86 instruction encoding, TRN, UABD and UABDL implementations

* Implement float conversion instruction, merge in LDj3SNuD fixes, and some other misc. fixes

* Implement SIMD shift instruction and fix Dup_V

* Add SCVTF and UCVTF (vector, fixed-point) variants to the opcode table

* Fix check with tolerance on tester

* Implement FP & SIMD comparison instructions, and some fixes

* Update FCVT (Scalar) encoding on the table to support the Half-float variants

* Support passing V128 structs, some cleanup on the register allocator, merge LDj3SNuD fixes

* Use old memory access methods, made a start on SIMD memory insts support, some fixes

* Fix float constant passed to functions, save and restore non-volatile XMM registers, other fixes

* Fix arguments count with struct return values, other fixes

* More instructions

* Misc. fixes and integrate LDj3SNuD fixes

* Update tests

* Add a faster linear scan allocator, unwinding support on windows, and other changes

* Update Ryujinx.HLE

* Update Ryujinx.Graphics

* Fix V128 return pointer passing, RCX is clobbered

* Update Ryujinx.Tests

* Update ITimeZoneService

* Stop using GetFunctionPointer as that can't be called from native code, misc. fixes and tweaks

* Use generic GetFunctionPointerForDelegate method and other tweaks

* Some refactoring on the code generator, assert on invalid operations and use a separate enum for intrinsics

* Remove some unused code on the assembler

* Fix REX.W prefix regression on float conversion instructions, add some sort of profiler

* Add hardware capability detection

* Fix regression on Sha1h and revert Fcm** changes

* Add SSE2-only paths on vector extract and insert, some refactoring on the pre-allocator

* Fix silly mistake introduced on last commit on CpuId

* Generate inline stack probes when the stack allocation is too large

* Initial support for the System-V ABI

* Support multiple destination operands

* Fix SSE2 VectorInsert8 path, and other fixes

* Change placement of XMM callee save and restore code to match other compilers

* Rename Dest to Destination and Inst to Instruction

* Fix a regression related to calls and the V128 type

* Add an extra space on comments to match code style

* Some refactoring

* Fix vector insert FP32 SSE2 path

* Port over the ARM32 instructions

* Avoid memory protection races on JIT Cache

* Another fix on VectorInsert FP32 (thanks to LDj3SNuD

* Float operands don't need to use the same register when VEX is supported

* Add a new register allocator, higher quality code for hot code (tier up), and other tweaks

* Some nits, small improvements on the pre allocator

* CpuThreadState is gone

* Allow changing CPU emulators with a config entry

* Add runtime identifiers on the ARMeilleure project

* Allow switching between CPUs through a config entry (pt. 2)

* Change win10-x64 to win-x64 on projects

* Update the Ryujinx project to use ARMeilleure

* Ensure that the selected register is valid on the hybrid allocator

* Allow exiting on returns to 0 (should fix test regression)

* Remove register assignments for most used variables on the hybrid allocator

* Do not use fixed registers as spill temp

* Add missing namespace and remove unneeded using

* Address PR feedback

* Fix types, etc

* Enable AssumeStrictAbiCompliance by default

* Ensure that Spill and Fill don't load or store any more than necessary

7 files changed, 211 insertions, 102 deletions

diff --git a/Ryujinx.Tests.Unicorn/IndexedProperty.cs b/Ryujinx.Tests.Unicorn/IndexedProperty.cs
index a4365026..65d445fc 100644
--- a/Ryujinx.Tests.Unicorn/IndexedProperty.cs
+++ b/Ryujinx.Tests.Unicorn/IndexedProperty.cs
@@ -4,24 +4,24 @@ namespace Ryujinx.Tests.Unicorn
 {
     public class IndexedProperty<TIndex, TValue>
     {
-        readonly Action<TIndex, TValue> SetAction;
-        readonly Func<TIndex, TValue> GetFunc;
+        private Func<TIndex, TValue>   _getFunc;
+        private Action<TIndex, TValue> _setAction;
 
         public IndexedProperty(Func<TIndex, TValue> getFunc, Action<TIndex, TValue> setAction)
         {
-            GetFunc   = getFunc;
-            SetAction = setAction;
+            _getFunc   = getFunc;
+            _setAction = setAction;
         }
 
-        public TValue this[TIndex i]
+        public TValue this[TIndex index]
         {
             get
             {
-                return GetFunc(i);
+                return _getFunc(index);
             }
             set
             {
-                SetAction(i, value);
+                _setAction(index, value);
             }
         }
     }
diff --git a/Ryujinx.Tests.Unicorn/Native/Interface.cs b/Ryujinx.Tests.Unicorn/Native/Interface.cs
index 006585b5..59b1da07 100644
--- a/Ryujinx.Tests.Unicorn/Native/Interface.cs
+++ b/Ryujinx.Tests.Unicorn/Native/Interface.cs
@@ -16,11 +16,13 @@ namespace Ryujinx.Tests.Unicorn.Native
         public static void MarshalArrayOf<T>(IntPtr input, int length, out T[] output)
         {
             int size = Marshal.SizeOf(typeof(T));
+
             output = new T[length];
 
             for (int i = 0; i < length; i++)
             {
                 IntPtr item = new IntPtr(input.ToInt64() + i * size);
+
                 output[i] = Marshal.PtrToStructure<T>(item);
             }
         }
@@ -29,7 +31,7 @@ namespace Ryujinx.Tests.Unicorn.Native
         public static extern uint uc_version(out uint major, out uint minor);
 
         [DllImport("unicorn", CallingConvention = CallingConvention.Cdecl)]
-        public static extern UnicornError uc_open(uint arch, uint mode, out IntPtr uc);
+        public static extern UnicornError uc_open(UnicornArch arch, UnicornMode mode, out IntPtr uc);
 
         [DllImport("unicorn", CallingConvention = CallingConvention.Cdecl)]
         public static extern UnicornError uc_close(IntPtr uc);
diff --git a/Ryujinx.Tests.Unicorn/Native/UnicornArch.cs b/Ryujinx.Tests.Unicorn/Native/UnicornArch.cs
index 73710faa..ff633293 100644
--- a/Ryujinx.Tests.Unicorn/Native/UnicornArch.cs
+++ b/Ryujinx.Tests.Unicorn/Native/UnicornArch.cs
@@ -1,6 +1,6 @@
 namespace Ryujinx.Tests.Unicorn.Native
 {
-    public enum UnicornArch
+    public enum UnicornArch : uint
     {
         UC_ARCH_ARM = 1,    // ARM architecture (including Thumb, Thumb-2)
         UC_ARCH_ARM64,      // ARM-64, also called AArch64
diff --git a/Ryujinx.Tests.Unicorn/Native/UnicornMode.cs b/Ryujinx.Tests.Unicorn/Native/UnicornMode.cs
index 5cd83516..8045f2da 100644
--- a/Ryujinx.Tests.Unicorn/Native/UnicornMode.cs
+++ b/Ryujinx.Tests.Unicorn/Native/UnicornMode.cs
@@ -1,7 +1,7 @@
 // ReSharper disable InconsistentNaming
 namespace Ryujinx.Tests.Unicorn.Native
 {
-    public enum UnicornMode
+    public enum UnicornMode : uint
     {
         UC_MODE_LITTLE_ENDIAN = 0,    // little-endian mode (default mode)
         UC_MODE_BIG_ENDIAN = 1 << 30, // big-endian mode
diff --git a/Ryujinx.Tests.Unicorn/Ryujinx.Tests.Unicorn.csproj b/Ryujinx.Tests.Unicorn/Ryujinx.Tests.Unicorn.csproj
index 5a99b39f..d15a405b 100644
--- a/Ryujinx.Tests.Unicorn/Ryujinx.Tests.Unicorn.csproj
+++ b/Ryujinx.Tests.Unicorn/Ryujinx.Tests.Unicorn.csproj
@@ -2,7 +2,7 @@
 
   <PropertyGroup>
     <TargetFramework>netcoreapp2.1</TargetFramework>
-    <RuntimeIdentifiers>win10-x64;osx-x64;linux-x64</RuntimeIdentifiers>
+    <RuntimeIdentifiers>win-x64;osx-x64;linux-x64</RuntimeIdentifiers>
     <AllowUnsafeBlocks>true</AllowUnsafeBlocks>
     <Configurations>Debug;Release;Profile Debug;Profile Release</Configurations>
   </PropertyGroup>
@@ -23,7 +23,6 @@
 
   <ItemGroup>
     <PackageReference Include="Microsoft.NET.Test.Sdk" Version="15.8.0" />
-    <PackageReference Include="System.Runtime.Intrinsics.Experimental" Version="4.5.0-rc1" />
   </ItemGroup>
 
 </Project>
diff --git a/Ryujinx.Tests.Unicorn/SimdValue.cs b/Ryujinx.Tests.Unicorn/SimdValue.cs
new file mode 100644
index 00000000..2b528430
--- /dev/null
+++ b/Ryujinx.Tests.Unicorn/SimdValue.cs
@@ -0,0 +1,112 @@
+using System;
+
+namespace Ryujinx.Tests.Unicorn
+{
+    public struct SimdValue : IEquatable<SimdValue>
+    {
+        private ulong _e0;
+        private ulong _e1;
+
+        public SimdValue(ulong e0, ulong e1)
+        {
+            _e0 = e0;
+            _e1 = e1;
+        }
+
+        public SimdValue(byte[] data)
+        {
+            _e0 = (ulong)BitConverter.ToInt64(data, 0);
+            _e1 = (ulong)BitConverter.ToInt64(data, 8);
+        }
+
+        public float AsFloat()
+        {
+            return GetFloat(0);
+        }
+
+        public double AsDouble()
+        {
+            return GetDouble(0);
+        }
+
+        public float GetFloat(int index)
+        {
+            return BitConverter.Int32BitsToSingle(GetInt32(index));
+        }
+
+        public double GetDouble(int index)
+        {
+            return BitConverter.Int64BitsToDouble(GetInt64(index));
+        }
+
+        public int  GetInt32(int index) => (int)GetUInt32(index);
+        public long GetInt64(int index) => (long)GetUInt64(index);
+
+        public uint GetUInt32(int index)
+        {
+            switch (index)
+            {
+                case 0: return (uint)(_e0 >> 0);
+                case 1: return (uint)(_e0 >> 32);
+                case 2: return (uint)(_e1 >> 0);
+                case 3: return (uint)(_e1 >> 32);
+            }
+
+            throw new ArgumentOutOfRangeException(nameof(index));
+        }
+
+        public ulong GetUInt64(int index)
+        {
+            switch (index)
+            {
+                case 0: return _e0;
+                case 1: return _e1;
+            }
+
+            throw new ArgumentOutOfRangeException(nameof(index));
+        }
+
+        public byte[] ToArray()
+        {
+            byte[] e0Data = BitConverter.GetBytes(_e0);
+            byte[] e1Data = BitConverter.GetBytes(_e1);
+
+            byte[] data = new byte[16];
+
+            Buffer.BlockCopy(e0Data, 0, data, 0, 8);
+            Buffer.BlockCopy(e1Data, 0, data, 8, 8);
+
+            return data;
+        }
+
+        public override int GetHashCode()
+        {
+            return HashCode.Combine(_e0, _e1);
+        }
+
+        public static bool operator ==(SimdValue x, SimdValue y)
+        {
+            return x.Equals(y);
+        }
+
+        public static bool operator !=(SimdValue x, SimdValue y)
+        {
+            return !x.Equals(y);
+        }
+
+        public override bool Equals(object obj)
+        {
+            return obj is SimdValue vector && Equals(vector);
+        }
+
+        public bool Equals(SimdValue other)
+        {
+            return other._e0 == _e0 && other._e1 == _e1;
+        }
+
+        public override string ToString()
+        {
+            return $"0x{_e1:X16}{_e0:X16}";
+        }
+    }
+}
\ No newline at end of file
diff --git a/Ryujinx.Tests.Unicorn/UnicornAArch64.cs b/Ryujinx.Tests.Unicorn/UnicornAArch64.cs
index 0425d1d3..4453d18d 100644
--- a/Ryujinx.Tests.Unicorn/UnicornAArch64.cs
+++ b/Ryujinx.Tests.Unicorn/UnicornAArch64.cs
@@ -1,8 +1,5 @@
 using Ryujinx.Tests.Unicorn.Native;
 using System;
-using System.Diagnostics.Contracts;
-using System.Runtime.Intrinsics;
-using System.Runtime.Intrinsics.X86;
 
 namespace Ryujinx.Tests.Unicorn
 {
@@ -15,95 +12,96 @@ namespace Ryujinx.Tests.Unicorn
             get
             {
                 return new IndexedProperty<int, ulong>(
-                    (int i) => GetX(i),
+                    (int i)              => GetX(i),
                     (int i, ulong value) => SetX(i, value));
             }
         }
 
-        public IndexedProperty<int, Vector128<float>> Q
+        public IndexedProperty<int, SimdValue> Q
         {
             get
             {
-                return new IndexedProperty<int, Vector128<float>>(
-                    (int i) => GetQ(i),
-                    (int i, Vector128<float> value) => SetQ(i, value));
+                return new IndexedProperty<int, SimdValue>(
+                    (int i)                  => GetQ(i),
+                    (int i, SimdValue value) => SetQ(i, value));
             }
         }
 
         public ulong LR
         {
-            get { return GetRegister(ArmRegister.LR); }
-            set { SetRegister(ArmRegister.LR, value); }
+            get => GetRegister(ArmRegister.LR);
+            set => SetRegister(ArmRegister.LR, value);
         }
 
         public ulong SP
         {
-            get { return GetRegister(ArmRegister.SP); }
-            set { SetRegister(ArmRegister.SP, value); }
+            get => GetRegister(ArmRegister.SP);
+            set => SetRegister(ArmRegister.SP, value);
         }
 
         public ulong PC
         {
-            get { return GetRegister(ArmRegister.PC); }
-            set { SetRegister(ArmRegister.PC, value); }
+            get => GetRegister(ArmRegister.PC);
+            set => SetRegister(ArmRegister.PC, value);
         }
 
         public uint Pstate
         {
-            get { return (uint)GetRegister(ArmRegister.PSTATE); }
-            set { SetRegister(ArmRegister.PSTATE, (uint)value); }
+            get => (uint)GetRegister(ArmRegister.PSTATE);
+            set =>       SetRegister(ArmRegister.PSTATE, (uint)value);
         }
 
         public int Fpcr
         {
-            get { return (int)GetRegister(ArmRegister.FPCR); }
-            set { SetRegister(ArmRegister.FPCR, (uint)value); }
+            get => (int)GetRegister(ArmRegister.FPCR);
+            set =>      SetRegister(ArmRegister.FPCR, (uint)value);
         }
 
         public int Fpsr
         {
-            get { return (int)GetRegister(ArmRegister.FPSR); }
-            set { SetRegister(ArmRegister.FPSR, (uint)value); }
+            get => (int)GetRegister(ArmRegister.FPSR);
+            set =>      SetRegister(ArmRegister.FPSR, (uint)value);
         }
 
         public bool OverflowFlag
         {
-            get { return (Pstate & 0x10000000u) != 0; }
-            set { Pstate = (Pstate & ~0x10000000u) | (value ? 0x10000000u : 0u); }
+            get =>          (Pstate &  0x10000000u) != 0;
+            set => Pstate = (Pstate & ~0x10000000u) | (value ? 0x10000000u : 0u);
         }
 
         public bool CarryFlag
         {
-            get { return (Pstate & 0x20000000u) != 0; }
-            set { Pstate = (Pstate & ~0x20000000u) | (value ? 0x20000000u : 0u); }
+            get =>          (Pstate &  0x20000000u) != 0;
+            set => Pstate = (Pstate & ~0x20000000u) | (value ? 0x20000000u : 0u);
         }
 
         public bool ZeroFlag
         {
-            get { return (Pstate & 0x40000000u) != 0; }
-            set { Pstate = (Pstate & ~0x40000000u) | (value ? 0x40000000u : 0u); }
+            get =>          (Pstate &  0x40000000u) != 0;
+            set => Pstate = (Pstate & ~0x40000000u) | (value ? 0x40000000u : 0u);
         }
 
         public bool NegativeFlag
         {
-            get { return (Pstate & 0x80000000u) != 0; }
-            set { Pstate = (Pstate & ~0x80000000u) | (value ? 0x80000000u : 0u); }
+            get =>          (Pstate &  0x80000000u) != 0;
+            set => Pstate = (Pstate & ~0x80000000u) | (value ? 0x80000000u : 0u);
         }
 
         public UnicornAArch64()
         {
-            Interface.Checked(Interface.uc_open((uint)UnicornArch.UC_ARCH_ARM64, (uint)UnicornMode.UC_MODE_LITTLE_ENDIAN, out uc));
+            Interface.Checked(Interface.uc_open(UnicornArch.UC_ARCH_ARM64, UnicornMode.UC_MODE_LITTLE_ENDIAN, out uc));
+
             SetRegister(ArmRegister.CPACR_EL1, 0x00300000);
         }
 
         ~UnicornAArch64()
         {
-            Interface.Checked(Interface.uc_close(uc));
+            Interface.Checked(Native.Interface.uc_close(uc));
         }
 
         public void RunForCount(ulong count)
         {
-            Interface.Checked(Interface.uc_emu_start(uc, PC, 0xFFFFFFFFFFFFFFFFu, 0, count));
+            Interface.Checked(Native.Interface.uc_emu_start(uc, this.PC, 0xFFFFFFFFFFFFFFFFu, 0, count));
         }
 
         public void Step()
@@ -111,7 +109,7 @@ namespace Ryujinx.Tests.Unicorn
             RunForCount(1);
         }
 
-        internal static ArmRegister[] X_registers = new ArmRegister[31]
+        private static ArmRegister[] XRegisters = new ArmRegister[31]
         {
             ArmRegister.X0,
             ArmRegister.X1,
@@ -146,7 +144,7 @@ namespace Ryujinx.Tests.Unicorn
             ArmRegister.X30,
         };
 
-        internal static ArmRegister[] Q_registers = new ArmRegister[32]
+        private static ArmRegister[] QRegisters = new ArmRegister[32]
         {
             ArmRegister.Q0,
             ArmRegister.Q1,
@@ -182,97 +180,104 @@ namespace Ryujinx.Tests.Unicorn
             ArmRegister.Q31,
         };
 
-        internal ulong GetRegister(ArmRegister register)
+        public ulong GetX(int index)
         {
-            byte[] value_bytes = new byte[8];
-            Interface.Checked(Interface.uc_reg_read(uc, (int)register, value_bytes));
-            return (ulong)BitConverter.ToInt64(value_bytes, 0);
+            if ((uint)index > 30)
+            {
+                throw new ArgumentOutOfRangeException(nameof(index));
+            }
+
+            return GetRegister(XRegisters[index]);
         }
 
-        internal void SetRegister(ArmRegister register, ulong value)
+        public void SetX(int index, ulong value)
         {
-            byte[] value_bytes = BitConverter.GetBytes(value);
-            Interface.Checked(Interface.uc_reg_write(uc, (int)register, value_bytes));
+            if ((uint)index > 30)
+            {
+                throw new ArgumentOutOfRangeException(nameof(index));
+            }
+
+            SetRegister(XRegisters[index], value);
         }
 
-        internal Vector128<float> GetVector(ArmRegister register)
+        public SimdValue GetQ(int index)
         {
-            byte[] value_bytes = new byte[16];
-            Interface.Checked(Interface.uc_reg_read(uc, (int)register, value_bytes));
-            unsafe
+            if ((uint)index > 31)
             {
-                fixed (byte* p = &value_bytes[0])
-                {
-                    return Sse.LoadVector128((float*)p);
-                }
+                throw new ArgumentOutOfRangeException(nameof(index));
             }
+
+            return GetVector(QRegisters[index]);
         }
 
-        internal void SetVector(ArmRegister register, Vector128<float> value)
+        public void SetQ(int index, SimdValue value)
         {
-            byte[] value_bytes = new byte[16];
-            unsafe
+            if ((uint)index > 31)
             {
-                fixed (byte* p = &value_bytes[0])
-                {
-                    Sse.Store((float*)p, value);
-                }
+                throw new ArgumentOutOfRangeException(nameof(index));
             }
-            Interface.Checked(Interface.uc_reg_write(uc, (int)register, value_bytes));
+
+            SetVector(QRegisters[index], value);
         }
 
-        public ulong GetX(int index)
+        private ulong GetRegister(ArmRegister register)
         {
-            Contract.Requires(index <= 30, "invalid register");
+            byte[] data = new byte[8];
 
-            return GetRegister(X_registers[index]);
+            Interface.Checked(Native.Interface.uc_reg_read(uc, (int)register, data));
+
+            return (ulong)BitConverter.ToInt64(data, 0);
         }
 
-        public void SetX(int index, ulong value)
+        private void SetRegister(ArmRegister register, ulong value)
         {
-            Contract.Requires(index <= 30, "invalid register");
+            byte[] data = BitConverter.GetBytes(value);
 
-            SetRegister(X_registers[index], value);
+            Interface.Checked(Interface.uc_reg_write(uc, (int)register, data));
         }
 
-        public Vector128<float> GetQ(int index)
+        private SimdValue GetVector(ArmRegister register)
         {
-            Contract.Requires(index <= 31, "invalid vector");
+            byte[] data = new byte[16];
+
+            Interface.Checked(Interface.uc_reg_read(uc, (int)register, data));
 
-            return GetVector(Q_registers[index]);
+            return new SimdValue(data);
         }
 
-        public void SetQ(int index, Vector128<float> value)
+        private void SetVector(ArmRegister register, SimdValue value)
         {
-            Contract.Requires(index <= 31, "invalid vector");
+            byte[] data = value.ToArray();
 
-            SetVector(Q_registers[index], value);
+            Interface.Checked(Interface.uc_reg_write(uc, (int)register, data));
         }
 
         public byte[] MemoryRead(ulong address, ulong size)
         {
             byte[] value = new byte[size];
+
             Interface.Checked(Interface.uc_mem_read(uc, address, value, size));
+
             return value;
         }
 
-        public byte   MemoryRead8 (ulong address) { return MemoryRead(address, 1)[0]; }
-        public UInt16 MemoryRead16(ulong address) { return (UInt16)BitConverter.ToInt16(MemoryRead(address, 2), 0); }
-        public UInt32 MemoryRead32(ulong address) { return (UInt32)BitConverter.ToInt32(MemoryRead(address, 4), 0); }
-        public UInt64 MemoryRead64(ulong address) { return (UInt64)BitConverter.ToInt64(MemoryRead(address, 8), 0); }
+        public byte   MemoryRead8 (ulong address) => MemoryRead(address, 1)[0];
+        public UInt16 MemoryRead16(ulong address) => (UInt16)BitConverter.ToInt16(MemoryRead(address, 2), 0);
+        public UInt32 MemoryRead32(ulong address) => (UInt32)BitConverter.ToInt32(MemoryRead(address, 4), 0);
+        public UInt64 MemoryRead64(ulong address) => (UInt64)BitConverter.ToInt64(MemoryRead(address, 8), 0);
 
         public void MemoryWrite(ulong address, byte[] value)
         {
             Interface.Checked(Interface.uc_mem_write(uc, address, value, (ulong)value.Length));
         }
 
-        public void MemoryWrite8 (ulong address, byte value)   { MemoryWrite(address, new byte[]{value}); }
-        public void MemoryWrite16(ulong address, Int16 value)  { MemoryWrite(address, BitConverter.GetBytes(value)); }
-        public void MemoryWrite16(ulong address, UInt16 value) { MemoryWrite(address, BitConverter.GetBytes(value)); }
-        public void MemoryWrite32(ulong address, Int32 value)  { MemoryWrite(address, BitConverter.GetBytes(value)); }
-        public void MemoryWrite32(ulong address, UInt32 value) { MemoryWrite(address, BitConverter.GetBytes(value)); }
-        public void MemoryWrite64(ulong address, Int64 value)  { MemoryWrite(address, BitConverter.GetBytes(value)); }
-        public void MemoryWrite64(ulong address, UInt64 value) { MemoryWrite(address, BitConverter.GetBytes(value)); }
+        public void MemoryWrite8 (ulong address, byte value)   => MemoryWrite(address, new byte[]{value});
+        public void MemoryWrite16(ulong address, Int16 value)  => MemoryWrite(address, BitConverter.GetBytes(value));
+        public void MemoryWrite16(ulong address, UInt16 value) => MemoryWrite(address, BitConverter.GetBytes(value));
+        public void MemoryWrite32(ulong address, Int32 value)  => MemoryWrite(address, BitConverter.GetBytes(value));
+        public void MemoryWrite32(ulong address, UInt32 value) => MemoryWrite(address, BitConverter.GetBytes(value));
+        public void MemoryWrite64(ulong address, Int64 value)  => MemoryWrite(address, BitConverter.GetBytes(value));
+        public void MemoryWrite64(ulong address, UInt64 value) => MemoryWrite(address, BitConverter.GetBytes(value));
 
         public void MemoryMap(ulong address, ulong size, MemoryPermission permissions)
         {
@@ -289,21 +294,12 @@ namespace Ryujinx.Tests.Unicorn
             Interface.Checked(Interface.uc_mem_protect(uc, address, size, (uint)permissions));
         }
 
-        public void DumpMemoryInformation()
-        {
-            Interface.Checked(Interface.uc_mem_regions(uc, out IntPtr regions_raw, out uint length));
-            Interface.MarshalArrayOf<UnicornMemoryRegion>(regions_raw, (int)length, out var regions);
-            foreach (var region in regions)
-            {
-                Console.WriteLine("region: begin {0:X16} end {1:X16} perms {2:X8}", region.begin, region.end, region.perms);
-            }
-        }
-
         public static bool IsAvailable()
         {
             try
             {
-                Interface.uc_version(out uint major, out uint minor);
+                Interface.uc_version(out _, out _);
+
                 return true;
             }
             catch (DllNotFoundException)