diff options
| author | merry <git@mary.rs> | 2022-02-17 22:39:45 +0000 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-02-17 19:39:45 -0300 |
| commit | 98e05ee4b7aa8a08088b1f0cd6c581bb50f11395 (patch) | |
| tree | af9cf98afb6c44161fadd87bfe7946c7a4250e47 /Ryujinx.Tests.Unicorn | |
| parent | 868919e101ba5d5ad1cfccb5017b294fec11c6e3 (diff) | |
ARMeilleure: Thumb support (All T16 instructions) (#3105)
* Decoders: Add InITBlock argument
* OpCodeTable: Minor cleanup
* OpCodeTable: Remove existing thumb instruction implementations
* OpCodeTable: Prepare for thumb instructions
* OpCodeTables: Improve thumb fast lookup
* Tests: Prepare for thumb tests
* T16: Implement BX
* T16: Implement LSL/LSR/ASR (imm)
* T16: Implement ADDS, SUBS (reg)
* T16: Implement ADDS, SUBS (3-bit immediate)
* T16: Implement MOVS, CMP, ADDS, SUBS (8-bit immediate)
* T16: Implement ANDS, EORS, LSLS, LSRS, ASRS, ADCS, SBCS, RORS, TST, NEGS, CMP, CMN, ORRS, MULS, BICS, MVNS (low registers)
* T16: Implement ADD, CMP, MOV (high reg)
* T16: Implement BLX (reg)
* T16: Implement LDR (literal)
* T16: Implement {LDR,STR}{,H,B,SB,SH} (register)
* T16: Implement {LDR,STR}{,B,H} (immediate)
* T16: Implement LDR/STR (SP)
* T16: Implement ADR
* T16: Implement Add to SP (immediate)
* T16: Implement ADD/SUB (SP)
* T16: Implement SXTH, SXTB, UXTH, UTXB
* T16: Implement CBZ, CBNZ
* T16: Implement PUSH, POP
* T16: Implement REV, REV16, REVSH
* T16: Implement NOP
* T16: Implement LDM, STM
* T16: Implement SVC
* T16: Implement B (conditional)
* T16: Implement B (unconditional)
* T16: Implement IT
* fixup! T16: Implement ADD/SUB (SP)
* fixup! T16: Implement Add to SP (immediate)
* fixup! T16: Implement IT
* CpuTestThumb: Add randomized tests
* Remove inITBlock argument
* Address nits
* Use index to handle IfThenBlockState
* Reduce line noise
* fixup
* nit
Diffstat (limited to 'Ryujinx.Tests.Unicorn')
| -rw-r--r-- | Ryujinx.Tests.Unicorn/UnicornAArch32.cs | 14 |
1 files changed, 12 insertions, 2 deletions
diff --git a/Ryujinx.Tests.Unicorn/UnicornAArch32.cs b/Ryujinx.Tests.Unicorn/UnicornAArch32.cs index 45d2da7a..e1efb52f 100644 --- a/Ryujinx.Tests.Unicorn/UnicornAArch32.cs +++ b/Ryujinx.Tests.Unicorn/UnicornAArch32.cs @@ -41,8 +41,8 @@ namespace Ryujinx.Tests.Unicorn public uint PC { - get => GetRegister(Arm32Register.PC); - set => SetRegister(Arm32Register.PC, value); + get => GetRegister(Arm32Register.PC) & 0xfffffffeu; + set => SetRegister(Arm32Register.PC, (value & 0xfffffffeu) | (ThumbFlag ? 1u : 0u)); } public uint CPSR @@ -87,6 +87,16 @@ namespace Ryujinx.Tests.Unicorn set => CPSR = (CPSR & ~0x80000000u) | (value ? 0x80000000u : 0u); } + public bool ThumbFlag + { + get => (CPSR & 0x00000020u) != 0; + set + { + CPSR = (CPSR & ~0x00000020u) | (value ? 0x00000020u : 0u); + SetRegister(Arm32Register.PC, (GetRegister(Arm32Register.PC) & 0xfffffffeu) | (value ? 1u : 0u)); + } + } + public UnicornAArch32() { Interface.Checked(Interface.uc_open(UnicornArch.UC_ARCH_ARM, UnicornMode.UC_MODE_LITTLE_ENDIAN, out uc)); |